[linux-block.git] / arch / m68k / coldfire / m527x.c

// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/

/*
 *	m527x.c  -- platform support for ColdFire 527x based boards
 *
 *	Sub-architcture dependent initialization code for the Freescale
 *	5270/5271 and 5274/5275 CPUs.
 *
 *	Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
 *	Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
 */

/***************************************************************************/

#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfclk.h>

/***************************************************************************/

DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);

struct clk *mcf_clks[] = {
	&clk_pll,
	&clk_sys,
	&clk_mcfpit0,
	&clk_mcfpit1,
	&clk_mcfpit2,
	&clk_mcfpit3,
	&clk_mcfuart0,
	&clk_mcfuart1,
	&clk_mcfuart2,
	&clk_mcfqspi0,
	&clk_fec0,
	&clk_fec1,
	&clk_mcfi2c0,
	NULL
};

/***************************************************************************/

static void __init m527x_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
#if defined(CONFIG_M5271)
	u16 par;

	/* setup QSPS pins for QSPI with gpio CS control */
	writeb(0x1f, MCFGPIO_PAR_QSPI);
	/* and CS2 & CS3 as gpio */
	par = readw(MCFGPIO_PAR_TIMER);
	par &= 0x3f3f;
	writew(par, MCFGPIO_PAR_TIMER);
#elif defined(CONFIG_M5275)
	/* setup QSPS pins for QSPI with gpio CS control */
	writew(0x003e, MCFGPIO_PAR_QSPI);
#endif
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}

/***************************************************************************/

static void __init m527x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
#if defined(CONFIG_M5271)
	u8 par;

	/* setup Port FECI2C Pin Assignment Register for I2C */
	/*  set PAR_SCL to SCL and PAR_SDA to SDA */
	par = readb(MCFGPIO_PAR_FECI2C);
	par |= 0x0f;
	writeb(par, MCFGPIO_PAR_FECI2C);
#elif defined(CONFIG_M5275)
	u16 par;

	/* setup Port FECI2C Pin Assignment Register for I2C */
	/*  set PAR_SCL to SCL and PAR_SDA to SDA */
	par = readw(MCFGPIO_PAR_FECI2C);
	par |= 0x0f;
	writew(par, MCFGPIO_PAR_FECI2C);
#endif
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}

/***************************************************************************/

static void __init m527x_uarts_init(void)
{
	u16 sepmask;

	/*
	 * External Pin Mask Setting & Enable External Pin for Interface
	 */
	sepmask = readw(MCFGPIO_PAR_UART);
	sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
	writew(sepmask, MCFGPIO_PAR_UART);
}

/***************************************************************************/

static void __init m527x_fec_init(void)
{
	u8 v;

	/* Set multi-function pins to ethernet mode for fec0 */
#if defined(CONFIG_M5271)
	v = readb(MCFGPIO_PAR_FECI2C);
	writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
#else
	u16 par;

	par = readw(MCFGPIO_PAR_FECI2C);
	writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
	v = readb(MCFGPIO_PAR_FEC0HL);
	writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);

	/* Set multi-function pins to ethernet mode for fec1 */
	par = readw(MCFGPIO_PAR_FECI2C);
	writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
	v = readb(MCFGPIO_PAR_FEC1HL);
	writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
#endif
}

/***************************************************************************/

void __init config_BSP(char *commandp, int size)
{
	mach_sched_init = hw_timer_init;
	m527x_uarts_init();
	m527x_fec_init();
	m527x_qspi_init();
	m527x_i2c_init();
}

/***************************************************************************/
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/***************************************************************************/
	3
	4	/*
ece9ae65	5	* m527x.c -- platform support for ColdFire 527x based boards
1da177e4	6	*
25985edc	7	* Sub-architcture dependent initialization code for the Freescale
ece9ae65	8	* 5270/5271 and 5274/5275 CPUs.
1da177e4 LT	9	*
	10	* Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
	11	* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
	12	*/
	13
	14	/***************************************************************************/
	15
1da177e4	16	#include <linux/kernel.h>
1da177e4 LT	17	#include <linux/param.h>
1da177e4 LT	18	#include <linux/init.h>
e206da0b	19	#include <linux/io.h>
1da177e4 LT	20	#include <asm/machdep.h>
	21	#include <asm/coldfire.h>
	22	#include <asm/mcfsim.h>
e206da0b	23	#include <asm/mcfuart.h>
a3d8eb0d GU	24	#include <asm/mcfclk.h>
	25
	26	/***************************************************************************/
	27
	28	DEFINE_CLK(pll, "pll.0", MCF_CLK);
	29	DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
	30	DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
	31	DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
	32	DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
	33	DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
	34	DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
	35	DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
	36	DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
74859523	37	DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
a3d8eb0d GU	38	DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
a3d8eb0d GU	39	DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
2d24b532	40	DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
a3d8eb0d GU	41
	42	struct clk *mcf_clks[] = {
	43	&clk_pll,
	44	&clk_sys,
	45	&clk_mcfpit0,
	46	&clk_mcfpit1,
	47	&clk_mcfpit2,
	48	&clk_mcfpit3,
	49	&clk_mcfuart0,
	50	&clk_mcfuart1,
	51	&clk_mcfuart2,
74859523	52	&clk_mcfqspi0,
a3d8eb0d GU	53	&clk_fec0,
a3d8eb0d GU	54	&clk_fec1,
2d24b532	55	&clk_mcfi2c0,
a3d8eb0d GU	56	NULL
a3d8eb0d GU	57	};
1da177e4 LT	58
	59	/***************************************************************************/
	60
91d60417 SK	61	static void __init m527x_qspi_init(void)
91d60417 SK	62	{
151d14f4	63	#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
91d60417 SK	64	#if defined(CONFIG_M5271)
	65	u16 par;
	66
	67	/* setup QSPS pins for QSPI with gpio CS control */
	68	writeb(0x1f, MCFGPIO_PAR_QSPI);
	69	/* and CS2 & CS3 as gpio */
	70	par = readw(MCFGPIO_PAR_TIMER);
	71	par &= 0x3f3f;
	72	writew(par, MCFGPIO_PAR_TIMER);
	73	#elif defined(CONFIG_M5275)
	74	/* setup QSPS pins for QSPI with gpio CS control */
	75	writew(0x003e, MCFGPIO_PAR_QSPI);
	76	#endif
83ca6009	77	#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
151d14f4	78	}
e206da0b GU	79
	80	/***************************************************************************/
	81
2d24b532 SK	82	static void __init m527x_i2c_init(void)
	83	{
	84	#if IS_ENABLED(CONFIG_I2C_IMX)
	85	#if defined(CONFIG_M5271)
	86	u8 par;
	87
	88	/* setup Port FECI2C Pin Assignment Register for I2C */
	89	/* set PAR_SCL to SCL and PAR_SDA to SDA */
	90	par = readb(MCFGPIO_PAR_FECI2C);
	91	par \|= 0x0f;
	92	writeb(par, MCFGPIO_PAR_FECI2C);
	93	#elif defined(CONFIG_M5275)
	94	u16 par;
	95
	96	/* setup Port FECI2C Pin Assignment Register for I2C */
	97	/* set PAR_SCL to SCL and PAR_SDA to SDA */
	98	par = readw(MCFGPIO_PAR_FECI2C);
	99	par \|= 0x0f;
	100	writew(par, MCFGPIO_PAR_FECI2C);
	101	#endif
	102	#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
	103	}
	104
	105	/***************************************************************************/
	106
1eb13916	107	static void __init m527x_uarts_init(void)
e206da0b GU	108	{
e206da0b GU	109	u16 sepmask;
e206da0b	110
e206da0b GU	111	/*
	112	* External Pin Mask Setting & Enable External Pin for Interface
	113	*/
f821e349	114	sepmask = readw(MCFGPIO_PAR_UART);
1eb13916	115	sepmask \|= UART0_ENABLE_MASK \| UART1_ENABLE_MASK \| UART2_ENABLE_MASK;
f821e349	116	writew(sepmask, MCFGPIO_PAR_UART);
e206da0b GU	117	}
e206da0b GU	118
1da177e4 LT	119	/***************************************************************************/
1da177e4 LT	120
ffba3f48 GU	121	static void __init m527x_fec_init(void)
ffba3f48 GU	122	{
ffba3f48 GU	123	u8 v;
ffba3f48 GU	124
ffba3f48	125	/* Set multi-function pins to ethernet mode for fec0 */
592578a1	126	#if defined(CONFIG_M5271)
f821e349 GU	127	v = readb(MCFGPIO_PAR_FECI2C);
f821e349 GU	128	writeb(v \| 0xf0, MCFGPIO_PAR_FECI2C);
592578a1	129	#else
6e420613 GU	130	u16 par;
6e420613 GU	131
f821e349 GU	132	par = readw(MCFGPIO_PAR_FECI2C);
	133	writew(par \| 0xf00, MCFGPIO_PAR_FECI2C);
	134	v = readb(MCFGPIO_PAR_FEC0HL);
	135	writeb(v \| 0xc0, MCFGPIO_PAR_FEC0HL);
ffba3f48	136
ffba3f48	137	/* Set multi-function pins to ethernet mode for fec1 */
f821e349 GU	138	par = readw(MCFGPIO_PAR_FECI2C);
	139	writew(par \| 0xa0, MCFGPIO_PAR_FECI2C);
	140	v = readb(MCFGPIO_PAR_FEC1HL);
	141	writeb(v \| 0xc0, MCFGPIO_PAR_FEC1HL);
ffba3f48 GU	142	#endif
	143	}
	144
	145	/***************************************************************************/
	146
e206da0b	147	void __init config_BSP(char *commandp, int size)
1da177e4	148	{
35aefb26	149	mach_sched_init = hw_timer_init;
ffba3f48 GU	150	m527x_uarts_init();
ffba3f48 GU	151	m527x_fec_init();
91d60417	152	m527x_qspi_init();
2d24b532	153	m527x_i2c_init();
1da177e4 LT	154	}
	155
	156	/***************************************************************************/