[linux-2.6-block.git] / arch / m32r / platforms / oaks32r / setup.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  linux/arch/m32r/platforms/oaks32r/setup.c
 *
 *  Setup routines for OAKS32R Board
 *
 *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
 *                           Hitoshi Yamamoto, Mamoru Sakugawa
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>

#include <asm/m32r.h>
#include <asm/io.h>

#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))

icu_data_t icu_data[NR_IRQS];

static void disable_oaks32r_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
	outl(data, port);
}

static void enable_oaks32r_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
	outl(data, port);
}

static void mask_oaks32r(struct irq_data *data)
{
	disable_oaks32r_irq(data->irq);
}

static void unmask_oaks32r(struct irq_data *data)
{
	enable_oaks32r_irq(data->irq);
}

static void shutdown_oaks32r(struct irq_data *data)
{
	unsigned long port;

	port = irq2port(data->irq);
	outl(M32R_ICUCR_ILEVEL7, port);
}

static struct irq_chip oaks32r_irq_type =
{
	.name		= "OAKS32R-IRQ",
	.irq_shutdown	= shutdown_oaks32r,
	.irq_mask	= mask_oaks32r,
	.irq_unmask	= unmask_oaks32r,
};

void __init init_IRQ(void)
{
	static int once = 0;

	if (once)
		return;
	else
		once++;

#ifdef CONFIG_NE2000
	/* INT3 : LAN controller (RTL8019AS) */
	irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_oaks32r_irq(M32R_IRQ_INT3);
#endif /* CONFIG_M32R_NE2000 */

	/* MFT2 : system timer */
	irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	disable_oaks32r_irq(M32R_IRQ_MFT2);

#ifdef CONFIG_SERIAL_M32R_SIO
	/* SIO0_R : uart receive data */
	irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	disable_oaks32r_irq(M32R_IRQ_SIO0_R);

	/* SIO0_S : uart send data */
	irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	disable_oaks32r_irq(M32R_IRQ_SIO0_S);

	/* SIO1_R : uart receive data */
	irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	disable_oaks32r_irq(M32R_IRQ_SIO1_R);

	/* SIO1_S : uart send data */
	irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	disable_oaks32r_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_SERIAL_M32R_SIO */
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4	2	/*
3264f976	3	* linux/arch/m32r/platforms/oaks32r/setup.c
1da177e4 LT	4	*
	5	* Setup routines for OAKS32R Board
	6	*
316240f6 HT	7	* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
316240f6 HT	8	* Hitoshi Yamamoto, Mamoru Sakugawa
1da177e4 LT	9	*/
1da177e4 LT	10
1da177e4 LT	11	#include <linux/irq.h>
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
	14
1da177e4 LT	15	#include <asm/m32r.h>
	16	#include <asm/io.h>
	17
	18	#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
	19
1da177e4 LT	20	icu_data_t icu_data[NR_IRQS];
	21
	22	static void disable_oaks32r_irq(unsigned int irq)
	23	{
	24	unsigned long port, data;
	25
	26	port = irq2port(irq);
	27	data = icu_data[irq].icucr\|M32R_ICUCR_ILEVEL7;
	28	outl(data, port);
	29	}
	30
	31	static void enable_oaks32r_irq(unsigned int irq)
	32	{
	33	unsigned long port, data;
	34
	35	port = irq2port(irq);
	36	data = icu_data[irq].icucr\|M32R_ICUCR_IEN\|M32R_ICUCR_ILEVEL6;
	37	outl(data, port);
	38	}
	39
ce1104ce	40	static void mask_oaks32r(struct irq_data *data)
1da177e4	41	{
ce1104ce	42	disable_oaks32r_irq(data->irq);
1da177e4 LT	43	}
1da177e4 LT	44
ce1104ce	45	static void unmask_oaks32r(struct irq_data *data)
1da177e4	46	{
ce1104ce	47	enable_oaks32r_irq(data->irq);
1da177e4 LT	48	}
1da177e4 LT	49
ce1104ce	50	static void shutdown_oaks32r(struct irq_data *data)
1da177e4 LT	51	{
	52	unsigned long port;
	53
ce1104ce	54	port = irq2port(data->irq);
1da177e4 LT	55	outl(M32R_ICUCR_ILEVEL7, port);
	56	}
	57
189e91f5	58	static struct irq_chip oaks32r_irq_type =
1da177e4	59	{
ce1104ce TG	60	.name = "OAKS32R-IRQ",
	61	.irq_shutdown = shutdown_oaks32r,
	62	.irq_mask = mask_oaks32r,
	63	.irq_unmask = unmask_oaks32r,
1da177e4 LT	64	};
	65
	66	void __init init_IRQ(void)
	67	{
	68	static int once = 0;
	69
	70	if (once)
	71	return;
	72	else
	73	once++;
	74
	75	#ifdef CONFIG_NE2000
	76	/* INT3 : LAN controller (RTL8019AS) */
27e5c5a9	77	irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
ce1104ce	78	handle_level_irq);
1da177e4 LT	79	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
	80	disable_oaks32r_irq(M32R_IRQ_INT3);
	81	#endif /* CONFIG_M32R_NE2000 */
	82
	83	/* MFT2 : system timer */
27e5c5a9	84	irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
ce1104ce	85	handle_level_irq);
1da177e4 LT	86	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	87	disable_oaks32r_irq(M32R_IRQ_MFT2);
	88
	89	#ifdef CONFIG_SERIAL_M32R_SIO
	90	/* SIO0_R : uart receive data */
27e5c5a9	91	irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
ce1104ce	92	handle_level_irq);
1da177e4 LT	93	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	94	disable_oaks32r_irq(M32R_IRQ_SIO0_R);
	95
	96	/* SIO0_S : uart send data */
27e5c5a9	97	irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
ce1104ce	98	handle_level_irq);
1da177e4 LT	99	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	100	disable_oaks32r_irq(M32R_IRQ_SIO0_S);
	101
	102	/* SIO1_R : uart receive data */
27e5c5a9	103	irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
ce1104ce	104	handle_level_irq);
1da177e4 LT	105	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	106	disable_oaks32r_irq(M32R_IRQ_SIO1_R);
	107
	108	/* SIO1_S : uart send data */
27e5c5a9	109	irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
ce1104ce	110	handle_level_irq);
1da177e4 LT	111	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	112	disable_oaks32r_irq(M32R_IRQ_SIO1_S);
	113	#endif /* CONFIG_SERIAL_M32R_SIO */
1da177e4	114	}