[linux-block.git] / arch / m32r / platforms / m32700ut / setup.c

/*
 *  linux/arch/m32r/platforms/m32700ut/setup.c
 *
 *  Setup routines for Renesas M32700UT Board
 *
 *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
 *                           Hitoshi Yamamoto, Takeo Takahashi
 *
 *  This file is subject to the terms and conditions of the GNU General
 *  Public License.  See the file "COPYING" in the main directory of this
 *  archive for more details.
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>

#include <asm/system.h>
#include <asm/m32r.h>
#include <asm/io.h>

/*
 * M32700 Interrupt Control Unit (Level 1)
 */
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))

icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];

static void disable_m32700ut_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
	outl(data, port);
}

static void enable_m32700ut_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
	outl(data, port);
}

static void mask_m32700ut(struct irq_data *data)
{
	disable_m32700ut_irq(data->irq);
}

static void unmask_m32700ut(struct irq_data *data)
{
	enable_m32700ut_irq(data->irq);
}

static void shutdown_m32700ut(struct irq_data *data)
{
	unsigned long port;

	port = irq2port(data->irq);
	outl(M32R_ICUCR_ILEVEL7, port);
}

static struct irq_chip m32700ut_irq_type =
{
	.name		= "M32700UT-IRQ",
	.irq_shutdown	= shutdown_m32700ut,
	.irq_mask	= mask_m32700ut,
	.irq_unmask	= unmask_m32700ut
};

/*
 * Interrupt Control Unit of PLD on M32700UT (Level 2)
 */
#define irq2pldirq(x)		((x) - M32700UT_PLD_IRQ_BASE)
#define pldirq2port(x)		(unsigned long)((int)PLD_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

typedef struct {
	unsigned short icucr;  /* ICU Control Register */
} pld_icu_data_t;

static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];

static void disable_m32700ut_pld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
	port = pldirq2port(pldirq);
	data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_m32700ut_pld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
	port = pldirq2port(pldirq);
	data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_m32700ut_pld(struct irq_data *data)
{
	disable_m32700ut_pld_irq(data->irq);
}

static void unmask_m32700ut_pld(struct irq_data *data)
{
	enable_m32700ut_pld_irq(data->irq);
	enable_m32700ut_irq(M32R_IRQ_INT1);
}

static void shutdown_m32700ut_pld_irq(struct irq_data *data)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2pldirq(data->irq);
	port = pldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct irq_chip m32700ut_pld_irq_type =
{
	.name		= "M32700UT-PLD-IRQ",
	.irq_shutdown	= shutdown_m32700ut_pld_irq,
	.irq_mask	= mask_m32700ut_pld,
	.irq_unmask	= unmask_m32700ut_pld,
};

/*
 * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
 */
#define irq2lanpldirq(x)	((x) - M32700UT_LAN_PLD_IRQ_BASE)
#define lanpldirq2port(x)	(unsigned long)((int)M32700UT_LAN_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];

static void disable_m32700ut_lanpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_m32700ut_lanpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_m32700ut_lanpld(struct irq_data *data)
{
	disable_m32700ut_lanpld_irq(data->irq);
}

static void unmask_m32700ut_lanpld(struct irq_data *data)
{
	enable_m32700ut_lanpld_irq(data->irq);
	enable_m32700ut_irq(M32R_IRQ_INT0);
}

static void shutdown_m32700ut_lanpld(struct irq_data *data)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(data->irq);
	port = lanpldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct irq_chip m32700ut_lanpld_irq_type =
{
	.name		= "M32700UT-PLD-LAN-IRQ",
	.irq_shutdown	= shutdown_m32700ut_lanpld,
	.irq_mask	= mask_m32700ut_lanpld,
	.irq_unmask	= unmask_m32700ut_lanpld,
};

/*
 * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
 */
#define irq2lcdpldirq(x)	((x) - M32700UT_LCD_PLD_IRQ_BASE)
#define lcdpldirq2port(x)	(unsigned long)((int)M32700UT_LCD_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];

static void disable_m32700ut_lcdpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_m32700ut_lcdpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
{
	disable_m32700ut_lcdpld_irq(irq);
}

static void end_m32700ut_lcdpld_irq(unsigned int irq)
{
	enable_m32700ut_lcdpld_irq(irq);
	enable_m32700ut_irq(M32R_IRQ_INT2);
}

static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
{
	enable_m32700ut_lcdpld_irq(irq);
	return (0);
}

static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct irq_chip m32700ut_lcdpld_irq_type =
{
	.name = "M32700UT-PLD-LCD-IRQ",
	.startup = startup_m32700ut_lcdpld_irq,
	.shutdown = shutdown_m32700ut_lcdpld_irq,
	.enable = enable_m32700ut_lcdpld_irq,
	.disable = disable_m32700ut_lcdpld_irq,
	.ack = mask_and_ack_m32700ut_lcdpld,
	.end = end_m32700ut_lcdpld_irq
};

void __init init_IRQ(void)
{
#if defined(CONFIG_SMC91X)
	/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
	set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN,
				 &m32700ut_lanpld_irq_type, handle_level_irq);
	lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* "H" edge sense */
	disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
#endif  /* CONFIG_SMC91X */

	/* MFT2 : system timer */
	set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	disable_m32700ut_irq(M32R_IRQ_MFT2);

	/* SIO0 : receive */
	set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	disable_m32700ut_irq(M32R_IRQ_SIO0_R);

	/* SIO0 : send */
	set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	disable_m32700ut_irq(M32R_IRQ_SIO0_S);

	/* SIO1 : receive */
	set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	disable_m32700ut_irq(M32R_IRQ_SIO1_R);

	/* SIO1 : send */
	set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	disable_m32700ut_irq(M32R_IRQ_SIO1_S);

	/* DMA1 : */
	set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_DMA1].icucr = 0;
	disable_m32700ut_irq(M32R_IRQ_DMA1);

#ifdef CONFIG_SERIAL_M32R_PLDSIO
	/* INT#1: SIO0 Receive on PLD */
	set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
				 handle_level_irq);
	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);

	/* INT#1: SIO0 Send on PLD */
	set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
				 handle_level_irq);
	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
#endif  /* CONFIG_SERIAL_M32R_PLDSIO */

	/* INT#1: CFC IREQ on PLD */
	set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
				 handle_level_irq);
	pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* 'L' level sense */
	disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);

	/* INT#1: CFC Insert on PLD */
	set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
				 handle_level_irq);
	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;	/* 'L' edge sense */
	disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);

	/* INT#1: CFC Eject on PLD */
	set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
				 handle_level_irq);
	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* 'H' edge sense */
	disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);

	/*
	 * INT0# is used for LAN, DIO
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
	enable_m32700ut_irq(M32R_IRQ_INT0);

	/*
	 * INT1# is used for UART, MMC, CF Controller in FPGA.
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
	enable_m32700ut_irq(M32R_IRQ_INT1);

#if defined(CONFIG_USB)
	outw(USBCR_OTGS, USBCR); 	/* USBCR: non-OTG */
	set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type);

	lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* "L" level sense */
	disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
#endif
	/*
	 * INT2# is used for BAT, USB, AUDIO
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
	enable_m32700ut_irq(M32R_IRQ_INT2);

#if defined(CONFIG_VIDEO_M32R_AR)
	/*
	 * INT3# is used for AR
	 */
	set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_m32700ut_irq(M32R_IRQ_INT3);
#endif	/* CONFIG_VIDEO_M32R_AR */
}

#if defined(CONFIG_SMC91X)

#define LAN_IOSTART     0x300
#define LAN_IOEND       0x320
static struct resource smc91x_resources[] = {
	[0] = {
		.start  = (LAN_IOSTART),
		.end    = (LAN_IOEND),
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = M32700UT_LAN_IRQ_LAN,
		.end    = M32700UT_LAN_IRQ_LAN,
		.flags  = IORESOURCE_IRQ,
	}
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources  = ARRAY_SIZE(smc91x_resources),
	.resource       = smc91x_resources,
};
#endif

#if defined(CONFIG_FB_S1D13XXX)

#include <video/s1d13xxxfb.h>
#include <asm/s1d13806.h>

static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
	.initregs		= s1d13xxxfb_initregs,
	.initregssize		= ARRAY_SIZE(s1d13xxxfb_initregs),
	.platform_init_video	= NULL,
#ifdef CONFIG_PM
	.platform_suspend_video	= NULL,
	.platform_resume_video	= NULL,
#endif
};

static struct resource s1d13xxxfb_resources[] = {
	[0] = {
		.start  = 0x10600000UL,
		.end    = 0x1073FFFFUL,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 0x10400000UL,
		.end    = 0x104001FFUL,
		.flags  = IORESOURCE_MEM,
	}
};

static struct platform_device s1d13xxxfb_device = {
	.name		= S1D_DEVICENAME,
	.id		= 0,
	.dev            = {
		.platform_data  = &s1d13xxxfb_data,
	},
	.num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
	.resource       = s1d13xxxfb_resources,
};
#endif

static int __init platform_init(void)
{
#if defined(CONFIG_SMC91X)
	platform_device_register(&smc91x_device);
#endif
#if defined(CONFIG_FB_S1D13XXX)
	platform_device_register(&s1d13xxxfb_device);
#endif
	return 0;
}
arch_initcall(platform_init);
Commit	Line	Data
1da177e4	1	/*
3264f976	2	* linux/arch/m32r/platforms/m32700ut/setup.c
1da177e4 LT	3	*
	4	* Setup routines for Renesas M32700UT Board
	5	*
316240f6 HT	6	* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
316240f6 HT	7	* Hitoshi Yamamoto, Takeo Takahashi
1da177e4 LT	8	*
	9	* This file is subject to the terms and conditions of the GNU General
	10	* Public License. See the file "COPYING" in the main directory of this
	11	* archive for more details.
	12	*/
	13
1da177e4 LT	14	#include <linux/irq.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
d052d1be	17	#include <linux/platform_device.h>
1da177e4 LT	18
	19	#include <asm/system.h>
	20	#include <asm/m32r.h>
	21	#include <asm/io.h>
	22
	23	/*
	24	* M32700 Interrupt Control Unit (Level 1)
	25	*/
	26	#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
	27
c51d9943	28	icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
1da177e4 LT	29
	30	static void disable_m32700ut_irq(unsigned int irq)
	31	{
	32	unsigned long port, data;
	33
	34	port = irq2port(irq);
	35	data = icu_data[irq].icucr\|M32R_ICUCR_ILEVEL7;
	36	outl(data, port);
	37	}
	38
	39	static void enable_m32700ut_irq(unsigned int irq)
	40	{
	41	unsigned long port, data;
	42
	43	port = irq2port(irq);
	44	data = icu_data[irq].icucr\|M32R_ICUCR_IEN\|M32R_ICUCR_ILEVEL6;
	45	outl(data, port);
	46	}
	47
364a9ba0	48	static void mask_m32700ut(struct irq_data *data)
1da177e4	49	{
364a9ba0	50	disable_m32700ut_irq(data->irq);
1da177e4 LT	51	}
1da177e4 LT	52
364a9ba0	53	static void unmask_m32700ut(struct irq_data *data)
1da177e4	54	{
364a9ba0	55	enable_m32700ut_irq(data->irq);
1da177e4 LT	56	}
1da177e4 LT	57
364a9ba0	58	static void shutdown_m32700ut(struct irq_data *data)
1da177e4 LT	59	{
	60	unsigned long port;
	61
364a9ba0	62	port = irq2port(data->irq);
1da177e4 LT	63	outl(M32R_ICUCR_ILEVEL7, port);
	64	}
	65
189e91f5	66	static struct irq_chip m32700ut_irq_type =
1da177e4	67	{
364a9ba0 TG	68	.name = "M32700UT-IRQ",
	69	.irq_shutdown = shutdown_m32700ut,
	70	.irq_mask = mask_m32700ut,
	71	.irq_unmask = unmask_m32700ut
1da177e4 LT	72	};
	73
	74	/*
	75	* Interrupt Control Unit of PLD on M32700UT (Level 2)
	76	*/
	77	#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
	78	#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
	79	(((x) - 1) * sizeof(unsigned short)))
	80
	81	typedef struct {
	82	unsigned short icucr; /* ICU Control Register */
	83	} pld_icu_data_t;
	84
	85	static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
	86
	87	static void disable_m32700ut_pld_irq(unsigned int irq)
	88	{
	89	unsigned long port, data;
	90	unsigned int pldirq;
	91
	92	pldirq = irq2pldirq(irq);
1da177e4 LT	93	port = pldirq2port(pldirq);
	94	data = pld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
	95	outw(data, port);
	96	}
	97
	98	static void enable_m32700ut_pld_irq(unsigned int irq)
	99	{
	100	unsigned long port, data;
	101	unsigned int pldirq;
	102
	103	pldirq = irq2pldirq(irq);
1da177e4 LT	104	port = pldirq2port(pldirq);
	105	data = pld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
	106	outw(data, port);
	107	}
	108
63b549b6	109	static void mask_m32700ut_pld(struct irq_data *data)
1da177e4	110	{
63b549b6	111	disable_m32700ut_pld_irq(data->irq);
1da177e4 LT	112	}
1da177e4 LT	113
63b549b6	114	static void unmask_m32700ut_pld(struct irq_data *data)
1da177e4	115	{
63b549b6	116	enable_m32700ut_pld_irq(data->irq);
364a9ba0	117	enable_m32700ut_irq(M32R_IRQ_INT1);
1da177e4 LT	118	}
1da177e4 LT	119
63b549b6	120	static void shutdown_m32700ut_pld_irq(struct irq_data *data)
1da177e4 LT	121	{
	122	unsigned long port;
	123	unsigned int pldirq;
	124
63b549b6	125	pldirq = irq2pldirq(data->irq);
1da177e4 LT	126	port = pldirq2port(pldirq);
	127	outw(PLD_ICUCR_ILEVEL7, port);
	128	}
	129
189e91f5	130	static struct irq_chip m32700ut_pld_irq_type =
1da177e4	131	{
63b549b6 TG	132	.name = "M32700UT-PLD-IRQ",
	133	.irq_shutdown = shutdown_m32700ut_pld_irq,
	134	.irq_mask = mask_m32700ut_pld,
	135	.irq_unmask = unmask_m32700ut_pld,
1da177e4 LT	136	};
	137
	138	/*
	139	* Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
	140	*/
	141	#define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
	142	#define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
	143	(((x) - 1) * sizeof(unsigned short)))
	144
	145	static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
	146
	147	static void disable_m32700ut_lanpld_irq(unsigned int irq)
	148	{
	149	unsigned long port, data;
	150	unsigned int pldirq;
	151
	152	pldirq = irq2lanpldirq(irq);
	153	port = lanpldirq2port(pldirq);
	154	data = lanpld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
	155	outw(data, port);
	156	}
	157
	158	static void enable_m32700ut_lanpld_irq(unsigned int irq)
	159	{
	160	unsigned long port, data;
	161	unsigned int pldirq;
	162
	163	pldirq = irq2lanpldirq(irq);
	164	port = lanpldirq2port(pldirq);
	165	data = lanpld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
	166	outw(data, port);
	167	}
	168
72bd198f	169	static void mask_m32700ut_lanpld(struct irq_data *data)
1da177e4	170	{
72bd198f	171	disable_m32700ut_lanpld_irq(data->irq);
1da177e4 LT	172	}
1da177e4 LT	173
72bd198f	174	static void unmask_m32700ut_lanpld(struct irq_data *data)
1da177e4	175	{
72bd198f	176	enable_m32700ut_lanpld_irq(data->irq);
364a9ba0	177	enable_m32700ut_irq(M32R_IRQ_INT0);
1da177e4 LT	178	}
1da177e4 LT	179
72bd198f	180	static void shutdown_m32700ut_lanpld(struct irq_data *data)
1da177e4 LT	181	{
	182	unsigned long port;
	183	unsigned int pldirq;
	184
72bd198f	185	pldirq = irq2lanpldirq(data->irq);
1da177e4 LT	186	port = lanpldirq2port(pldirq);
	187	outw(PLD_ICUCR_ILEVEL7, port);
	188	}
	189
189e91f5	190	static struct irq_chip m32700ut_lanpld_irq_type =
1da177e4	191	{
72bd198f TG	192	.name = "M32700UT-PLD-LAN-IRQ",
	193	.irq_shutdown = shutdown_m32700ut_lanpld,
	194	.irq_mask = mask_m32700ut_lanpld,
	195	.irq_unmask = unmask_m32700ut_lanpld,
1da177e4 LT	196	};
	197
	198	/*
	199	* Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
	200	*/
	201	#define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
	202	#define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
	203	(((x) - 1) * sizeof(unsigned short)))
	204
	205	static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
	206
	207	static void disable_m32700ut_lcdpld_irq(unsigned int irq)
	208	{
	209	unsigned long port, data;
	210	unsigned int pldirq;
	211
	212	pldirq = irq2lcdpldirq(irq);
	213	port = lcdpldirq2port(pldirq);
	214	data = lcdpld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
	215	outw(data, port);
	216	}
	217
	218	static void enable_m32700ut_lcdpld_irq(unsigned int irq)
	219	{
	220	unsigned long port, data;
	221	unsigned int pldirq;
	222
	223	pldirq = irq2lcdpldirq(irq);
	224	port = lcdpldirq2port(pldirq);
	225	data = lcdpld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
	226	outw(data, port);
	227	}
	228
	229	static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
	230	{
	231	disable_m32700ut_lcdpld_irq(irq);
	232	}
	233
	234	static void end_m32700ut_lcdpld_irq(unsigned int irq)
	235	{
	236	enable_m32700ut_lcdpld_irq(irq);
364a9ba0	237	enable_m32700ut_irq(M32R_IRQ_INT2);
1da177e4 LT	238	}
	239
	240	static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
	241	{
	242	enable_m32700ut_lcdpld_irq(irq);
	243	return (0);
	244	}
	245
	246	static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
	247	{
	248	unsigned long port;
	249	unsigned int pldirq;
	250
	251	pldirq = irq2lcdpldirq(irq);
	252	port = lcdpldirq2port(pldirq);
	253	outw(PLD_ICUCR_ILEVEL7, port);
	254	}
	255
189e91f5	256	static struct irq_chip m32700ut_lcdpld_irq_type =
1da177e4	257	{
d1ea13c6	258	.name = "M32700UT-PLD-LCD-IRQ",
6f973b00 HT	259	.startup = startup_m32700ut_lcdpld_irq,
	260	.shutdown = shutdown_m32700ut_lcdpld_irq,
	261	.enable = enable_m32700ut_lcdpld_irq,
	262	.disable = disable_m32700ut_lcdpld_irq,
	263	.ack = mask_and_ack_m32700ut_lcdpld,
	264	.end = end_m32700ut_lcdpld_irq
1da177e4 LT	265	};
	266
	267	void __init init_IRQ(void)
	268	{
	269	#if defined(CONFIG_SMC91X)
	270	/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
72bd198f TG	271	set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN,
72bd198f TG	272	&m32700ut_lanpld_irq_type, handle_level_irq);
1da177e4 LT	273	lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD02; /* "H" edge sense */
	274	disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
	275	#endif /* CONFIG_SMC91X */
	276
	277	/* MFT2 : system timer */
364a9ba0 TG	278	set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
364a9ba0 TG	279	handle_level_irq);
1da177e4 LT	280	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	281	disable_m32700ut_irq(M32R_IRQ_MFT2);
	282
	283	/* SIO0 : receive */
364a9ba0 TG	284	set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
364a9ba0 TG	285	handle_level_irq);
1da177e4 LT	286	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	287	disable_m32700ut_irq(M32R_IRQ_SIO0_R);
	288
	289	/* SIO0 : send */
364a9ba0 TG	290	set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
364a9ba0 TG	291	handle_level_irq);
1da177e4 LT	292	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	293	disable_m32700ut_irq(M32R_IRQ_SIO0_S);
	294
	295	/* SIO1 : receive */
364a9ba0 TG	296	set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
364a9ba0 TG	297	handle_level_irq);
1da177e4 LT	298	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	299	disable_m32700ut_irq(M32R_IRQ_SIO1_R);
	300
	301	/* SIO1 : send */
364a9ba0 TG	302	set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
364a9ba0 TG	303	handle_level_irq);
1da177e4 LT	304	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	305	disable_m32700ut_irq(M32R_IRQ_SIO1_S);
	306
	307	/* DMA1 : */
364a9ba0 TG	308	set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
364a9ba0 TG	309	handle_level_irq);
1da177e4 LT	310	icu_data[M32R_IRQ_DMA1].icucr = 0;
	311	disable_m32700ut_irq(M32R_IRQ_DMA1);
	312
	313	#ifdef CONFIG_SERIAL_M32R_PLDSIO
	314	/* INT#1: SIO0 Receive on PLD */
63b549b6 TG	315	set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
63b549b6 TG	316	handle_level_irq);
1da177e4 LT	317	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD03;
	318	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
	319
	320	/* INT#1: SIO0 Send on PLD */
63b549b6 TG	321	set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
63b549b6 TG	322	handle_level_irq);
1da177e4 LT	323	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD03;
	324	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
	325	#endif /* CONFIG_SERIAL_M32R_PLDSIO */
	326
	327	/* INT#1: CFC IREQ on PLD */
63b549b6 TG	328	set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
63b549b6 TG	329	handle_level_irq);
1da177e4 LT	330	pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD01; /* 'L' level sense */
	331	disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
	332
	333	/* INT#1: CFC Insert on PLD */
63b549b6 TG	334	set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
63b549b6 TG	335	handle_level_irq);
1da177e4 LT	336	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
	337	disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
	338
	339	/* INT#1: CFC Eject on PLD */
63b549b6 TG	340	set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
63b549b6 TG	341	handle_level_irq);
1da177e4 LT	342	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
	343	disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
	344
	345	/*
	346	* INT0# is used for LAN, DIO
	347	* We enable it here.
	348	*/
	349	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD11;
	350	enable_m32700ut_irq(M32R_IRQ_INT0);
	351
	352	/*
	353	* INT1# is used for UART, MMC, CF Controller in FPGA.
	354	* We enable it here.
	355	*/
	356	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD11;
	357	enable_m32700ut_irq(M32R_IRQ_INT1);
	358
	359	#if defined(CONFIG_USB)
	360	outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
863018a7	361	set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type);
1da177e4	362
863018a7 TG	363	lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD01; /* "L" level sense */
863018a7 TG	364	disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
1da177e4 LT	365	#endif
	366	/*
	367	* INT2# is used for BAT, USB, AUDIO
	368	* We enable it here.
	369	*/
	370	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD01;
	371	enable_m32700ut_irq(M32R_IRQ_INT2);
	372
316240f6	373	#if defined(CONFIG_VIDEO_M32R_AR)
1da177e4 LT	374	/*
	375	* INT3# is used for AR
	376	*/
364a9ba0 TG	377	set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
364a9ba0 TG	378	handle_level_irq);
1da177e4 LT	379	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
1da177e4 LT	380	disable_m32700ut_irq(M32R_IRQ_INT3);
316240f6	381	#endif /* CONFIG_VIDEO_M32R_AR */
1da177e4 LT	382	}
1da177e4 LT	383
316240f6 HT	384	#if defined(CONFIG_SMC91X)
316240f6 HT	385
1da177e4 LT	386	#define LAN_IOSTART 0x300
	387	#define LAN_IOEND 0x320
	388	static struct resource smc91x_resources[] = {
	389	[0] = {
	390	.start = (LAN_IOSTART),
	391	.end = (LAN_IOEND),
	392	.flags = IORESOURCE_MEM,
	393	},
	394	[1] = {
	395	.start = M32700UT_LAN_IRQ_LAN,
	396	.end = M32700UT_LAN_IRQ_LAN,
	397	.flags = IORESOURCE_IRQ,
	398	}
	399	};
	400
	401	static struct platform_device smc91x_device = {
	402	.name = "smc91x",
	403	.id = 0,
	404	.num_resources = ARRAY_SIZE(smc91x_resources),
	405	.resource = smc91x_resources,
	406	};
316240f6 HT	407	#endif
	408
	409	#if defined(CONFIG_FB_S1D13XXX)
	410
	411	#include <video/s1d13xxxfb.h>
	412	#include <asm/s1d13806.h>
	413
	414	static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
	415	.initregs = s1d13xxxfb_initregs,
	416	.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
	417	.platform_init_video = NULL,
	418	#ifdef CONFIG_PM
	419	.platform_suspend_video = NULL,
	420	.platform_resume_video = NULL,
	421	#endif
	422	};
	423
	424	static struct resource s1d13xxxfb_resources[] = {
	425	[0] = {
	426	.start = 0x10600000UL,
	427	.end = 0x1073FFFFUL,
	428	.flags = IORESOURCE_MEM,
	429	},
	430	[1] = {
	431	.start = 0x10400000UL,
	432	.end = 0x104001FFUL,
	433	.flags = IORESOURCE_MEM,
	434	}
	435	};
	436
	437	static struct platform_device s1d13xxxfb_device = {
	438	.name = S1D_DEVICENAME,
	439	.id = 0,
	440	.dev = {
	441	.platform_data = &s1d13xxxfb_data,
	442	},
	443	.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
	444	.resource = s1d13xxxfb_resources,
	445	};
	446	#endif
1da177e4 LT	447
	448	static int __init platform_init(void)
	449	{
316240f6	450	#if defined(CONFIG_SMC91X)
1da177e4	451	platform_device_register(&smc91x_device);
316240f6 HT	452	#endif
	453	#if defined(CONFIG_FB_S1D13XXX)
	454	platform_device_register(&s1d13xxxfb_device);
	455	#endif
1da177e4 LT	456	return 0;
	457	}
	458	arch_initcall(platform_init);