[linux-2.6-block.git] / arch / m32r / kernel / setup_opsput.c

/*
 *  linux/arch/m32r/kernel/setup_opsput.c
 *
 *  Setup routines for Renesas OPSPUT Board
 *
 *  Copyright (c) 2002-2005
 * 	Hiroyuki Kondo, Hirokazu Takata,
 *      Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
 *
 *  This file is subject to the terms and conditions of the GNU General
 *  Public License.  See the file "COPYING" in the main directory of this
 *  archive for more details.
 */

#include <linux/config.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>

#include <asm/system.h>
#include <asm/m32r.h>
#include <asm/io.h>

/*
 * OPSP Interrupt Control Unit (Level 1)
 */
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))

#ifndef CONFIG_SMP
typedef struct {
	unsigned long icucr;  /* ICU Control Register */
} icu_data_t;
static icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
#else
icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
#endif /* CONFIG_SMP */


static void disable_opsput_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
	outl(data, port);
}

static void enable_opsput_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
	outl(data, port);
}

static void mask_and_ack_opsput(unsigned int irq)
{
	disable_opsput_irq(irq);
}

static void end_opsput_irq(unsigned int irq)
{
	enable_opsput_irq(irq);
}

static unsigned int startup_opsput_irq(unsigned int irq)
{
	enable_opsput_irq(irq);
	return (0);
}

static void shutdown_opsput_irq(unsigned int irq)
{
	unsigned long port;

	port = irq2port(irq);
	outl(M32R_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type opsput_irq_type =
{
	.typename = "OPSPUT-IRQ",
	.startup = startup_opsput_irq,
	.shutdown = shutdown_opsput_irq,
	.enable = enable_opsput_irq,
	.disable = disable_opsput_irq,
	.ack = mask_and_ack_opsput,
	.end = end_opsput_irq
};

/*
 * Interrupt Control Unit of PLD on OPSPUT (Level 2)
 */
#define irq2pldirq(x)		((x) - OPSPUT_PLD_IRQ_BASE)
#define pldirq2port(x)		(unsigned long)((int)PLD_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

typedef struct {
	unsigned short icucr;  /* ICU Control Register */
} pld_icu_data_t;

static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];

static void disable_opsput_pld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
//	disable_opsput_irq(M32R_IRQ_INT1);
	port = pldirq2port(pldirq);
	data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_opsput_pld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
//	enable_opsput_irq(M32R_IRQ_INT1);
	port = pldirq2port(pldirq);
	data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_and_ack_opsput_pld(unsigned int irq)
{
	disable_opsput_pld_irq(irq);
//	mask_and_ack_opsput(M32R_IRQ_INT1);
}

static void end_opsput_pld_irq(unsigned int irq)
{
	enable_opsput_pld_irq(irq);
	end_opsput_irq(M32R_IRQ_INT1);
}

static unsigned int startup_opsput_pld_irq(unsigned int irq)
{
	enable_opsput_pld_irq(irq);
	return (0);
}

static void shutdown_opsput_pld_irq(unsigned int irq)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
//	shutdown_opsput_irq(M32R_IRQ_INT1);
	port = pldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type opsput_pld_irq_type =
{
	.typename = "OPSPUT-PLD-IRQ",
	.startup = startup_opsput_pld_irq,
	.shutdown = shutdown_opsput_pld_irq,
	.enable = enable_opsput_pld_irq,
	.disable = disable_opsput_pld_irq,
	.ack = mask_and_ack_opsput_pld,
	.end = end_opsput_pld_irq
};

/*
 * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
 */
#define irq2lanpldirq(x)	((x) - OPSPUT_LAN_PLD_IRQ_BASE)
#define lanpldirq2port(x)	(unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];

static void disable_opsput_lanpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_opsput_lanpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_and_ack_opsput_lanpld(unsigned int irq)
{
	disable_opsput_lanpld_irq(irq);
}

static void end_opsput_lanpld_irq(unsigned int irq)
{
	enable_opsput_lanpld_irq(irq);
	end_opsput_irq(M32R_IRQ_INT0);
}

static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
{
	enable_opsput_lanpld_irq(irq);
	return (0);
}

static void shutdown_opsput_lanpld_irq(unsigned int irq)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type opsput_lanpld_irq_type =
{
	"OPSPUT-PLD-LAN-IRQ",
	startup_opsput_lanpld_irq,
	shutdown_opsput_lanpld_irq,
	enable_opsput_lanpld_irq,
	disable_opsput_lanpld_irq,
	mask_and_ack_opsput_lanpld,
	end_opsput_lanpld_irq
};

/*
 * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
 */
#define irq2lcdpldirq(x)	((x) - OPSPUT_LCD_PLD_IRQ_BASE)
#define lcdpldirq2port(x)	(unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];

static void disable_opsput_lcdpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_opsput_lcdpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_and_ack_opsput_lcdpld(unsigned int irq)
{
	disable_opsput_lcdpld_irq(irq);
}

static void end_opsput_lcdpld_irq(unsigned int irq)
{
	enable_opsput_lcdpld_irq(irq);
	end_opsput_irq(M32R_IRQ_INT2);
}

static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
{
	enable_opsput_lcdpld_irq(irq);
	return (0);
}

static void shutdown_opsput_lcdpld_irq(unsigned int irq)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type opsput_lcdpld_irq_type =
{
	"OPSPUT-PLD-LCD-IRQ",
	startup_opsput_lcdpld_irq,
	shutdown_opsput_lcdpld_irq,
	enable_opsput_lcdpld_irq,
	disable_opsput_lcdpld_irq,
	mask_and_ack_opsput_lcdpld,
	end_opsput_lcdpld_irq
};

void __init init_IRQ(void)
{
#if defined(CONFIG_SMC91X)
	/* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
	irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
	irq_desc[OPSPUT_LAN_IRQ_LAN].handler = &opsput_lanpld_irq_type;
	irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
	irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1;	/* disable nested irq */
	lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* "H" edge sense */
	disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
#endif  /* CONFIG_SMC91X */

	/* MFT2 : system timer */
	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_MFT2].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_MFT2].action = 0;
	irq_desc[M32R_IRQ_MFT2].depth = 1;
	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	disable_opsput_irq(M32R_IRQ_MFT2);

	/* SIO0 : receive */
	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_R].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_SIO0_R].action = 0;
	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	disable_opsput_irq(M32R_IRQ_SIO0_R);

	/* SIO0 : send */
	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_S].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_SIO0_S].action = 0;
	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	disable_opsput_irq(M32R_IRQ_SIO0_S);

	/* SIO1 : receive */
	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_R].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_SIO1_R].action = 0;
	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	disable_opsput_irq(M32R_IRQ_SIO1_R);

	/* SIO1 : send */
	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_S].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_SIO1_S].action = 0;
	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	disable_opsput_irq(M32R_IRQ_SIO1_S);

	/* DMA1 : */
	irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_DMA1].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_DMA1].action = 0;
	irq_desc[M32R_IRQ_DMA1].depth = 1;
	icu_data[M32R_IRQ_DMA1].icucr = 0;
	disable_opsput_irq(M32R_IRQ_DMA1);

#ifdef CONFIG_SERIAL_M32R_PLDSIO
	/* INT#1: SIO0 Receive on PLD */
	irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_SIO0_RCV].handler = &opsput_pld_irq_type;
	irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
	irq_desc[PLD_IRQ_SIO0_RCV].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
	disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);

	/* INT#1: SIO0 Send on PLD */
	irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_SIO0_SND].handler = &opsput_pld_irq_type;
	irq_desc[PLD_IRQ_SIO0_SND].action = 0;
	irq_desc[PLD_IRQ_SIO0_SND].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
	disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
#endif  /* CONFIG_SERIAL_M32R_PLDSIO */

#if defined(CONFIG_M32R_CFC)
	/* INT#1: CFC IREQ on PLD */
	irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFIREQ].handler = &opsput_pld_irq_type;
	irq_desc[PLD_IRQ_CFIREQ].action = 0;
	irq_desc[PLD_IRQ_CFIREQ].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* 'L' level sense */
	disable_opsput_pld_irq(PLD_IRQ_CFIREQ);

	/* INT#1: CFC Insert on PLD */
	irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFC_INSERT].handler = &opsput_pld_irq_type;
	irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
	irq_desc[PLD_IRQ_CFC_INSERT].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;	/* 'L' edge sense */
	disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);

	/* INT#1: CFC Eject on PLD */
	irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFC_EJECT].handler = &opsput_pld_irq_type;
	irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
	irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* 'H' edge sense */
	disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
#endif /* CONFIG_M32R_CFC */


	/*
	 * INT0# is used for LAN, DIO
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
	enable_opsput_irq(M32R_IRQ_INT0);

	/*
	 * INT1# is used for UART, MMC, CF Controller in FPGA.
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
	enable_opsput_irq(M32R_IRQ_INT1);

#if defined(CONFIG_USB)
	outw(USBCR_OTGS, USBCR); 	/* USBCR: non-OTG */

    irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
    irq_desc[OPSPUT_LCD_IRQ_USB_INT1].handler = &opsput_lcdpld_irq_type;
    irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
    irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
    lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* "L" level sense */
    disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
#endif
	/*
	 * INT2# is used for BAT, USB, AUDIO
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
	enable_opsput_irq(M32R_IRQ_INT2);

#if defined(CONFIG_VIDEO_M32R_AR)
	/*
	 * INT3# is used for AR
	 */
	irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_INT3].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_INT3].action = 0;
	irq_desc[M32R_IRQ_INT3].depth = 1;
	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_opsput_irq(M32R_IRQ_INT3);
#endif /* CONFIG_VIDEO_M32R_AR */
}

#if defined(CONFIG_SMC91X)

#define LAN_IOSTART     0x300
#define LAN_IOEND       0x320
static struct resource smc91x_resources[] = {
	[0] = {
		.start  = (LAN_IOSTART),
		.end    = (LAN_IOEND),
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = OPSPUT_LAN_IRQ_LAN,
		.end    = OPSPUT_LAN_IRQ_LAN,
		.flags  = IORESOURCE_IRQ,
	}
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources  = ARRAY_SIZE(smc91x_resources),
	.resource       = smc91x_resources,
};
#endif

#if defined(CONFIG_FB_S1D13XXX)

#include <video/s1d13xxxfb.h>
#include <asm/s1d13806.h>

static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
	.initregs		= s1d13xxxfb_initregs,
	.initregssize		= ARRAY_SIZE(s1d13xxxfb_initregs),
	.platform_init_video	= NULL,
#ifdef CONFIG_PM
	.platform_suspend_video	= NULL,
	.platform_resume_video	= NULL,
#endif
};

static struct resource s1d13xxxfb_resources[] = {
	[0] = {
		.start  = 0x10600000UL,
		.end    = 0x1073FFFFUL,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 0x10400000UL,
		.end    = 0x104001FFUL,
		.flags  = IORESOURCE_MEM,
	}
};

static struct platform_device s1d13xxxfb_device = {
	.name		= S1D_DEVICENAME,
	.id		= 0,
	.dev            = {
		.platform_data  = &s1d13xxxfb_data,
	},
	.num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
	.resource       = s1d13xxxfb_resources,
};
#endif

static int __init platform_init(void)
{
#if defined(CONFIG_SMC91X)
	platform_device_register(&smc91x_device);
#endif
#if defined(CONFIG_FB_S1D13XXX)
	platform_device_register(&s1d13xxxfb_device);
#endif
	return 0;
}
arch_initcall(platform_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/m32r/kernel/setup_opsput.c
	3	*
	4	* Setup routines for Renesas OPSPUT Board
	5	*
316240f6	6	* Copyright (c) 2002-2005
1da177e4 LT	7	* Hiroyuki Kondo, Hirokazu Takata,
	8	* Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
	9	*
	10	* This file is subject to the terms and conditions of the GNU General
	11	* Public License. See the file "COPYING" in the main directory of this
	12	* archive for more details.
	13	*/
	14
	15	#include <linux/config.h>
	16	#include <linux/irq.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
d052d1be	19	#include <linux/platform_device.h>
1da177e4 LT	20
	21	#include <asm/system.h>
	22	#include <asm/m32r.h>
	23	#include <asm/io.h>
	24
	25	/*
	26	* OPSP Interrupt Control Unit (Level 1)
	27	*/
	28	#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
	29
	30	#ifndef CONFIG_SMP
	31	typedef struct {
	32	unsigned long icucr; /* ICU Control Register */
	33	} icu_data_t;
c51d9943 AV	34	static icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
	35	#else
	36	icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
1da177e4 LT	37	#endif /* CONFIG_SMP */
1da177e4 LT	38
1da177e4 LT	39
	40	static void disable_opsput_irq(unsigned int irq)
	41	{
	42	unsigned long port, data;
	43
	44	port = irq2port(irq);
	45	data = icu_data[irq].icucr\|M32R_ICUCR_ILEVEL7;
	46	outl(data, port);
	47	}
	48
	49	static void enable_opsput_irq(unsigned int irq)
	50	{
	51	unsigned long port, data;
	52
	53	port = irq2port(irq);
	54	data = icu_data[irq].icucr\|M32R_ICUCR_IEN\|M32R_ICUCR_ILEVEL6;
	55	outl(data, port);
	56	}
	57
	58	static void mask_and_ack_opsput(unsigned int irq)
	59	{
	60	disable_opsput_irq(irq);
	61	}
	62
	63	static void end_opsput_irq(unsigned int irq)
	64	{
	65	enable_opsput_irq(irq);
	66	}
	67
	68	static unsigned int startup_opsput_irq(unsigned int irq)
	69	{
	70	enable_opsput_irq(irq);
	71	return (0);
	72	}
	73
	74	static void shutdown_opsput_irq(unsigned int irq)
	75	{
	76	unsigned long port;
	77
	78	port = irq2port(irq);
	79	outl(M32R_ICUCR_ILEVEL7, port);
	80	}
	81
	82	static struct hw_interrupt_type opsput_irq_type =
	83	{
6f973b00 HT	84	.typename = "OPSPUT-IRQ",
	85	.startup = startup_opsput_irq,
	86	.shutdown = shutdown_opsput_irq,
	87	.enable = enable_opsput_irq,
	88	.disable = disable_opsput_irq,
	89	.ack = mask_and_ack_opsput,
	90	.end = end_opsput_irq
1da177e4 LT	91	};
	92
	93	/*
	94	* Interrupt Control Unit of PLD on OPSPUT (Level 2)
	95	*/
	96	#define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE)
	97	#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
	98	(((x) - 1) * sizeof(unsigned short)))
	99
	100	typedef struct {
	101	unsigned short icucr; /* ICU Control Register */
	102	} pld_icu_data_t;
	103
	104	static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
	105
	106	static void disable_opsput_pld_irq(unsigned int irq)
	107	{
	108	unsigned long port, data;
	109	unsigned int pldirq;
	110
	111	pldirq = irq2pldirq(irq);
	112	// disable_opsput_irq(M32R_IRQ_INT1);
	113	port = pldirq2port(pldirq);
	114	data = pld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
	115	outw(data, port);
	116	}
	117
	118	static void enable_opsput_pld_irq(unsigned int irq)
	119	{
	120	unsigned long port, data;
	121	unsigned int pldirq;
	122
	123	pldirq = irq2pldirq(irq);
	124	// enable_opsput_irq(M32R_IRQ_INT1);
	125	port = pldirq2port(pldirq);
	126	data = pld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
	127	outw(data, port);
	128	}
	129
	130	static void mask_and_ack_opsput_pld(unsigned int irq)
	131	{
	132	disable_opsput_pld_irq(irq);
	133	// mask_and_ack_opsput(M32R_IRQ_INT1);
	134	}
	135
	136	static void end_opsput_pld_irq(unsigned int irq)
	137	{
	138	enable_opsput_pld_irq(irq);
	139	end_opsput_irq(M32R_IRQ_INT1);
	140	}
	141
	142	static unsigned int startup_opsput_pld_irq(unsigned int irq)
	143	{
	144	enable_opsput_pld_irq(irq);
	145	return (0);
	146	}
	147
	148	static void shutdown_opsput_pld_irq(unsigned int irq)
	149	{
	150	unsigned long port;
	151	unsigned int pldirq;
	152
	153	pldirq = irq2pldirq(irq);
	154	// shutdown_opsput_irq(M32R_IRQ_INT1);
155	port = pldirq2port(pldirq);
156	outw(PLD_ICUCR_ILEVEL7, port);
157	}
158
159	static struct hw_interrupt_type opsput_pld_irq_type =
160	{
6f973b00 HT	161	.typename = "OPSPUT-PLD-IRQ",
	162	.startup = startup_opsput_pld_irq,
	163	.shutdown = shutdown_opsput_pld_irq,
	164	.enable = enable_opsput_pld_irq,
	165	.disable = disable_opsput_pld_irq,
	166	.ack = mask_and_ack_opsput_pld,
	167	.end = end_opsput_pld_irq
1da177e4 LT	168	};
	169
	170	/*
	171	* Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
	172	*/
	173	#define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
	174	#define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
	175	(((x) - 1) * sizeof(unsigned short)))
	176
	177	static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
	178
	179	static void disable_opsput_lanpld_irq(unsigned int irq)
	180	{
	181	unsigned long port, data;
	182	unsigned int pldirq;
	183
	184	pldirq = irq2lanpldirq(irq);
	185	port = lanpldirq2port(pldirq);
	186	data = lanpld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
	187	outw(data, port);
	188	}
	189
	190	static void enable_opsput_lanpld_irq(unsigned int irq)
	191	{
	192	unsigned long port, data;
	193	unsigned int pldirq;
	194
	195	pldirq = irq2lanpldirq(irq);
	196	port = lanpldirq2port(pldirq);
	197	data = lanpld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
	198	outw(data, port);
	199	}
	200
	201	static void mask_and_ack_opsput_lanpld(unsigned int irq)
	202	{
	203	disable_opsput_lanpld_irq(irq);
	204	}
	205
	206	static void end_opsput_lanpld_irq(unsigned int irq)
	207	{
	208	enable_opsput_lanpld_irq(irq);
	209	end_opsput_irq(M32R_IRQ_INT0);
	210	}
	211
	212	static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
	213	{
	214	enable_opsput_lanpld_irq(irq);
	215	return (0);
	216	}
	217
	218	static void shutdown_opsput_lanpld_irq(unsigned int irq)
	219	{
	220	unsigned long port;
	221	unsigned int pldirq;
	222
	223	pldirq = irq2lanpldirq(irq);
	224	port = lanpldirq2port(pldirq);
	225	outw(PLD_ICUCR_ILEVEL7, port);
	226	}
	227
	228	static struct hw_interrupt_type opsput_lanpld_irq_type =
	229	{
	230	"OPSPUT-PLD-LAN-IRQ",
	231	startup_opsput_lanpld_irq,
232	shutdown_opsput_lanpld_irq,
233	enable_opsput_lanpld_irq,
234	disable_opsput_lanpld_irq,
235	mask_and_ack_opsput_lanpld,
236	end_opsput_lanpld_irq
237	};
238
239	/*
240	* Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
241	*/
242	#define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
243	#define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
244	(((x) - 1) * sizeof(unsigned short)))
245
246	static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
247
248	static void disable_opsput_lcdpld_irq(unsigned int irq)
249	{
250	unsigned long port, data;
251	unsigned int pldirq;
252
253	pldirq = irq2lcdpldirq(irq);
254	port = lcdpldirq2port(pldirq);
255	data = lcdpld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
256	outw(data, port);
257	}
258
259	static void enable_opsput_lcdpld_irq(unsigned int irq)
260	{
261	unsigned long port, data;
262	unsigned int pldirq;
263
264	pldirq = irq2lcdpldirq(irq);
265	port = lcdpldirq2port(pldirq);
266	data = lcdpld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
267	outw(data, port);
268	}
269
270	static void mask_and_ack_opsput_lcdpld(unsigned int irq)
271	{
272	disable_opsput_lcdpld_irq(irq);
273	}
274
275	static void end_opsput_lcdpld_irq(unsigned int irq)
276	{
277	enable_opsput_lcdpld_irq(irq);
278	end_opsput_irq(M32R_IRQ_INT2);
279	}
280
281	static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
282	{
283	enable_opsput_lcdpld_irq(irq);
284	return (0);
285	}
286
287	static void shutdown_opsput_lcdpld_irq(unsigned int irq)
288	{
289	unsigned long port;
290	unsigned int pldirq;
291
292	pldirq = irq2lcdpldirq(irq);
293	port = lcdpldirq2port(pldirq);
294	outw(PLD_ICUCR_ILEVEL7, port);
295	}
296
297	static struct hw_interrupt_type opsput_lcdpld_irq_type =
298	{
299	"OPSPUT-PLD-LCD-IRQ",
300	startup_opsput_lcdpld_irq,
301	shutdown_opsput_lcdpld_irq,
302	enable_opsput_lcdpld_irq,
303	disable_opsput_lcdpld_irq,
304	mask_and_ack_opsput_lcdpld,
305	end_opsput_lcdpld_irq
306	};
307
308	void __init init_IRQ(void)
309	{
310	#if defined(CONFIG_SMC91X)
311	/* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
312	irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
313	irq_desc[OPSPUT_LAN_IRQ_LAN].handler = &opsput_lanpld_irq_type;
314	irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
315	irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
316	lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD02; /* "H" edge sense */
317	disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
318	#endif /* CONFIG_SMC91X */
319
320	/* MFT2 : system timer */
321	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
322	irq_desc[M32R_IRQ_MFT2].handler = &opsput_irq_type;
323	irq_desc[M32R_IRQ_MFT2].action = 0;
324	irq_desc[M32R_IRQ_MFT2].depth = 1;
325	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
326	disable_opsput_irq(M32R_IRQ_MFT2);
327
328	/* SIO0 : receive */
329	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
330	irq_desc[M32R_IRQ_SIO0_R].handler = &opsput_irq_type;
331	irq_desc[M32R_IRQ_SIO0_R].action = 0;
332	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
333	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
334	disable_opsput_irq(M32R_IRQ_SIO0_R);
335
336	/* SIO0 : send */
337	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
338	irq_desc[M32R_IRQ_SIO0_S].handler = &opsput_irq_type;
339	irq_desc[M32R_IRQ_SIO0_S].action = 0;
340	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
341	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
342	disable_opsput_irq(M32R_IRQ_SIO0_S);
343
344	/* SIO1 : receive */
345	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
346	irq_desc[M32R_IRQ_SIO1_R].handler = &opsput_irq_type;
347	irq_desc[M32R_IRQ_SIO1_R].action = 0;
348	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
349	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
350	disable_opsput_irq(M32R_IRQ_SIO1_R);
351
352	/* SIO1 : send */
353	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
354	irq_desc[M32R_IRQ_SIO1_S].handler = &opsput_irq_type;
355	irq_desc[M32R_IRQ_SIO1_S].action = 0;
356	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
357	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
358	disable_opsput_irq(M32R_IRQ_SIO1_S);
359
360	/* DMA1 : */
361	irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
362	irq_desc[M32R_IRQ_DMA1].handler = &opsput_irq_type;
363	irq_desc[M32R_IRQ_DMA1].action = 0;
364	irq_desc[M32R_IRQ_DMA1].depth = 1;
365	icu_data[M32R_IRQ_DMA1].icucr = 0;
366	disable_opsput_irq(M32R_IRQ_DMA1);
367
368	#ifdef CONFIG_SERIAL_M32R_PLDSIO
369	/* INT#1: SIO0 Receive on PLD */
370	irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
371	irq_desc[PLD_IRQ_SIO0_RCV].handler = &opsput_pld_irq_type;
372	irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
373	irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
374	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD03;
375	disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
376
377	/* INT#1: SIO0 Send on PLD */
378	irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
379	irq_desc[PLD_IRQ_SIO0_SND].handler = &opsput_pld_irq_type;
380	irq_desc[PLD_IRQ_SIO0_SND].action = 0;
381	irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
382	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD03;
383	disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
384	#endif /* CONFIG_SERIAL_M32R_PLDSIO */
385
386	#if defined(CONFIG_M32R_CFC)
387	/* INT#1: CFC IREQ on PLD */
388	irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
389	irq_desc[PLD_IRQ_CFIREQ].handler = &opsput_pld_irq_type;
390	irq_desc[PLD_IRQ_CFIREQ].action = 0;
391	irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
392	pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD01; /* 'L' level sense */
393	disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
394
395	/* INT#1: CFC Insert on PLD */
396	irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
397	irq_desc[PLD_IRQ_CFC_INSERT].handler = &opsput_pld_irq_type;
398	irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
399	irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
400	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
401	disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
402
403	/* INT#1: CFC Eject on PLD */
404	irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
405	irq_desc[PLD_IRQ_CFC_EJECT].handler = &opsput_pld_irq_type;
406	irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
407	irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
408	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
409	disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
410	#endif /* CONFIG_M32R_CFC */
411
412
413	/*
414	* INT0# is used for LAN, DIO
415	* We enable it here.
416	*/
417	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD11;
418	enable_opsput_irq(M32R_IRQ_INT0);
419
420	/*
421	* INT1# is used for UART, MMC, CF Controller in FPGA.
422	* We enable it here.
423	*/
424	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD11;
425	enable_opsput_irq(M32R_IRQ_INT1);
426
427	#if defined(CONFIG_USB)
428	outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
429
430	irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
431	irq_desc[OPSPUT_LCD_IRQ_USB_INT1].handler = &opsput_lcdpld_irq_type;
432	irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
433	irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
434	lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD01; /* "L" level sense */
435	disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
436	#endif
437	/*
438	* INT2# is used for BAT, USB, AUDIO
439	* We enable it here.
440	*/
441	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD01;
442	enable_opsput_irq(M32R_IRQ_INT2);
443
316240f6	444	#if defined(CONFIG_VIDEO_M32R_AR)
1da177e4 LT	445	/*
	446	* INT3# is used for AR
	447	*/
	448	irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
	449	irq_desc[M32R_IRQ_INT3].handler = &opsput_irq_type;
	450	irq_desc[M32R_IRQ_INT3].action = 0;
	451	irq_desc[M32R_IRQ_INT3].depth = 1;
	452	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
	453	disable_opsput_irq(M32R_IRQ_INT3);
316240f6	454	#endif /* CONFIG_VIDEO_M32R_AR */
1da177e4 LT	455	}
1da177e4 LT	456
316240f6 HT	457	#if defined(CONFIG_SMC91X)
316240f6 HT	458
1da177e4 LT	459	#define LAN_IOSTART 0x300
	460	#define LAN_IOEND 0x320
	461	static struct resource smc91x_resources[] = {
	462	[0] = {
	463	.start = (LAN_IOSTART),
	464	.end = (LAN_IOEND),
	465	.flags = IORESOURCE_MEM,
	466	},
	467	[1] = {
	468	.start = OPSPUT_LAN_IRQ_LAN,
	469	.end = OPSPUT_LAN_IRQ_LAN,
	470	.flags = IORESOURCE_IRQ,
	471	}
	472	};
	473
	474	static struct platform_device smc91x_device = {
	475	.name = "smc91x",
	476	.id = 0,
	477	.num_resources = ARRAY_SIZE(smc91x_resources),
	478	.resource = smc91x_resources,
	479	};
316240f6 HT	480	#endif
	481
	482	#if defined(CONFIG_FB_S1D13XXX)
	483
	484	#include <video/s1d13xxxfb.h>
	485	#include <asm/s1d13806.h>
	486
	487	static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
	488	.initregs = s1d13xxxfb_initregs,
	489	.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
	490	.platform_init_video = NULL,
	491	#ifdef CONFIG_PM
	492	.platform_suspend_video = NULL,
	493	.platform_resume_video = NULL,
	494	#endif
	495	};
	496
	497	static struct resource s1d13xxxfb_resources[] = {
	498	[0] = {
	499	.start = 0x10600000UL,
	500	.end = 0x1073FFFFUL,
	501	.flags = IORESOURCE_MEM,
	502	},
	503	[1] = {
	504	.start = 0x10400000UL,
	505	.end = 0x104001FFUL,
	506	.flags = IORESOURCE_MEM,
	507	}
	508	};
	509
	510	static struct platform_device s1d13xxxfb_device = {
	511	.name = S1D_DEVICENAME,
	512	.id = 0,
	513	.dev = {
	514	.platform_data = &s1d13xxxfb_data,
	515	},
	516	.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
	517	.resource = s1d13xxxfb_resources,
	518	};
	519	#endif
1da177e4 LT	520
	521	static int __init platform_init(void)
	522	{
316240f6	523	#if defined(CONFIG_SMC91X)
1da177e4	524	platform_device_register(&smc91x_device);
316240f6 HT	525	#endif
	526	#if defined(CONFIG_FB_S1D13XXX)
	527	platform_device_register(&s1d13xxxfb_device);
	528	#endif
1da177e4 LT	529	return 0;
	530	}
	531	arch_initcall(platform_init);