[linux-2.6-block.git] / arch / m32r / kernel / setup_opsput.c

/*
 *  linux/arch/m32r/kernel/setup_opsput.c
 *
 *  Setup routines for Renesas OPSPUT Board
 *
 *  Copyright (c) 2002-2004
 * 	Hiroyuki Kondo, Hirokazu Takata,
 *      Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
 *
 *  This file is subject to the terms and conditions of the GNU General
 *  Public License.  See the file "COPYING" in the main directory of this
 *  archive for more details.
 */

#include <linux/config.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>

#include <asm/system.h>
#include <asm/m32r.h>
#include <asm/io.h>

/*
 * OPSP Interrupt Control Unit (Level 1)
 */
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))

#ifndef CONFIG_SMP
typedef struct {
	unsigned long icucr;  /* ICU Control Register */
} icu_data_t;
#endif /* CONFIG_SMP */

static icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];

static void disable_opsput_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
	outl(data, port);
}

static void enable_opsput_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
	outl(data, port);
}

static void mask_and_ack_opsput(unsigned int irq)
{
	disable_opsput_irq(irq);
}

static void end_opsput_irq(unsigned int irq)
{
	enable_opsput_irq(irq);
}

static unsigned int startup_opsput_irq(unsigned int irq)
{
	enable_opsput_irq(irq);
	return (0);
}

static void shutdown_opsput_irq(unsigned int irq)
{
	unsigned long port;

	port = irq2port(irq);
	outl(M32R_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type opsput_irq_type =
{
	"OPSPUT-IRQ",
	startup_opsput_irq,
	shutdown_opsput_irq,
	enable_opsput_irq,
	disable_opsput_irq,
	mask_and_ack_opsput,
	end_opsput_irq
};

/*
 * Interrupt Control Unit of PLD on OPSPUT (Level 2)
 */
#define irq2pldirq(x)		((x) - OPSPUT_PLD_IRQ_BASE)
#define pldirq2port(x)		(unsigned long)((int)PLD_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

typedef struct {
	unsigned short icucr;  /* ICU Control Register */
} pld_icu_data_t;

static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];

static void disable_opsput_pld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
//	disable_opsput_irq(M32R_IRQ_INT1);
	port = pldirq2port(pldirq);
	data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_opsput_pld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
//	enable_opsput_irq(M32R_IRQ_INT1);
	port = pldirq2port(pldirq);
	data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_and_ack_opsput_pld(unsigned int irq)
{
	disable_opsput_pld_irq(irq);
//	mask_and_ack_opsput(M32R_IRQ_INT1);
}

static void end_opsput_pld_irq(unsigned int irq)
{
	enable_opsput_pld_irq(irq);
	end_opsput_irq(M32R_IRQ_INT1);
}

static unsigned int startup_opsput_pld_irq(unsigned int irq)
{
	enable_opsput_pld_irq(irq);
	return (0);
}

static void shutdown_opsput_pld_irq(unsigned int irq)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
//	shutdown_opsput_irq(M32R_IRQ_INT1);
	port = pldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type opsput_pld_irq_type =
{
	"OPSPUT-PLD-IRQ",
	startup_opsput_pld_irq,
	shutdown_opsput_pld_irq,
	enable_opsput_pld_irq,
	disable_opsput_pld_irq,
	mask_and_ack_opsput_pld,
	end_opsput_pld_irq
};

/*
 * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
 */
#define irq2lanpldirq(x)	((x) - OPSPUT_LAN_PLD_IRQ_BASE)
#define lanpldirq2port(x)	(unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];

static void disable_opsput_lanpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_opsput_lanpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_and_ack_opsput_lanpld(unsigned int irq)
{
	disable_opsput_lanpld_irq(irq);
}

static void end_opsput_lanpld_irq(unsigned int irq)
{
	enable_opsput_lanpld_irq(irq);
	end_opsput_irq(M32R_IRQ_INT0);
}

static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
{
	enable_opsput_lanpld_irq(irq);
	return (0);
}

static void shutdown_opsput_lanpld_irq(unsigned int irq)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type opsput_lanpld_irq_type =
{
	"OPSPUT-PLD-LAN-IRQ",
	startup_opsput_lanpld_irq,
	shutdown_opsput_lanpld_irq,
	enable_opsput_lanpld_irq,
	disable_opsput_lanpld_irq,
	mask_and_ack_opsput_lanpld,
	end_opsput_lanpld_irq
};

/*
 * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
 */
#define irq2lcdpldirq(x)	((x) - OPSPUT_LCD_PLD_IRQ_BASE)
#define lcdpldirq2port(x)	(unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];

static void disable_opsput_lcdpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_opsput_lcdpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_and_ack_opsput_lcdpld(unsigned int irq)
{
	disable_opsput_lcdpld_irq(irq);
}

static void end_opsput_lcdpld_irq(unsigned int irq)
{
	enable_opsput_lcdpld_irq(irq);
	end_opsput_irq(M32R_IRQ_INT2);
}

static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
{
	enable_opsput_lcdpld_irq(irq);
	return (0);
}

static void shutdown_opsput_lcdpld_irq(unsigned int irq)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type opsput_lcdpld_irq_type =
{
	"OPSPUT-PLD-LCD-IRQ",
	startup_opsput_lcdpld_irq,
	shutdown_opsput_lcdpld_irq,
	enable_opsput_lcdpld_irq,
	disable_opsput_lcdpld_irq,
	mask_and_ack_opsput_lcdpld,
	end_opsput_lcdpld_irq
};

void __init init_IRQ(void)
{
#if defined(CONFIG_SMC91X)
	/* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
	irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
	irq_desc[OPSPUT_LAN_IRQ_LAN].handler = &opsput_lanpld_irq_type;
	irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
	irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1;	/* disable nested irq */
	lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* "H" edge sense */
	disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
#endif  /* CONFIG_SMC91X */

	/* MFT2 : system timer */
	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_MFT2].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_MFT2].action = 0;
	irq_desc[M32R_IRQ_MFT2].depth = 1;
	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	disable_opsput_irq(M32R_IRQ_MFT2);

	/* SIO0 : receive */
	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_R].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_SIO0_R].action = 0;
	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	disable_opsput_irq(M32R_IRQ_SIO0_R);

	/* SIO0 : send */
	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_S].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_SIO0_S].action = 0;
	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	disable_opsput_irq(M32R_IRQ_SIO0_S);

	/* SIO1 : receive */
	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_R].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_SIO1_R].action = 0;
	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	disable_opsput_irq(M32R_IRQ_SIO1_R);

	/* SIO1 : send */
	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_S].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_SIO1_S].action = 0;
	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	disable_opsput_irq(M32R_IRQ_SIO1_S);

	/* DMA1 : */
	irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_DMA1].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_DMA1].action = 0;
	irq_desc[M32R_IRQ_DMA1].depth = 1;
	icu_data[M32R_IRQ_DMA1].icucr = 0;
	disable_opsput_irq(M32R_IRQ_DMA1);

#ifdef CONFIG_SERIAL_M32R_PLDSIO
	/* INT#1: SIO0 Receive on PLD */
	irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_SIO0_RCV].handler = &opsput_pld_irq_type;
	irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
	irq_desc[PLD_IRQ_SIO0_RCV].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
	disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);

	/* INT#1: SIO0 Send on PLD */
	irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_SIO0_SND].handler = &opsput_pld_irq_type;
	irq_desc[PLD_IRQ_SIO0_SND].action = 0;
	irq_desc[PLD_IRQ_SIO0_SND].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
	disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
#endif  /* CONFIG_SERIAL_M32R_PLDSIO */

#if defined(CONFIG_M32R_CFC)
	/* INT#1: CFC IREQ on PLD */
	irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFIREQ].handler = &opsput_pld_irq_type;
	irq_desc[PLD_IRQ_CFIREQ].action = 0;
	irq_desc[PLD_IRQ_CFIREQ].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* 'L' level sense */
	disable_opsput_pld_irq(PLD_IRQ_CFIREQ);

	/* INT#1: CFC Insert on PLD */
	irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFC_INSERT].handler = &opsput_pld_irq_type;
	irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
	irq_desc[PLD_IRQ_CFC_INSERT].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;	/* 'L' edge sense */
	disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);

	/* INT#1: CFC Eject on PLD */
	irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFC_EJECT].handler = &opsput_pld_irq_type;
	irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
	irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* 'H' edge sense */
	disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
#endif /* CONFIG_M32R_CFC */


	/*
	 * INT0# is used for LAN, DIO
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
	enable_opsput_irq(M32R_IRQ_INT0);

	/*
	 * INT1# is used for UART, MMC, CF Controller in FPGA.
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
	enable_opsput_irq(M32R_IRQ_INT1);

#if defined(CONFIG_USB)
	outw(USBCR_OTGS, USBCR); 	/* USBCR: non-OTG */

    irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
    irq_desc[OPSPUT_LCD_IRQ_USB_INT1].handler = &opsput_lcdpld_irq_type;
    irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
    irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
    lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* "L" level sense */
    disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
#endif
	/*
	 * INT2# is used for BAT, USB, AUDIO
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
	enable_opsput_irq(M32R_IRQ_INT2);

//#if defined(CONFIG_VIDEO_M32R_AR)
	/*
	 * INT3# is used for AR
	 */
	irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_INT3].handler = &opsput_irq_type;
	irq_desc[M32R_IRQ_INT3].action = 0;
	irq_desc[M32R_IRQ_INT3].depth = 1;
	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_opsput_irq(M32R_IRQ_INT3);
//#endif	/* CONFIG_VIDEO_M32R_AR */
}

#define LAN_IOSTART     0x300
#define LAN_IOEND       0x320
static struct resource smc91x_resources[] = {
	[0] = {
		.start  = (LAN_IOSTART),
		.end    = (LAN_IOEND),
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = OPSPUT_LAN_IRQ_LAN,
		.end    = OPSPUT_LAN_IRQ_LAN,
		.flags  = IORESOURCE_IRQ,
	}
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources  = ARRAY_SIZE(smc91x_resources),
	.resource       = smc91x_resources,
};

static int __init platform_init(void)
{
	platform_device_register(&smc91x_device);
	return 0;
}
arch_initcall(platform_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/m32r/kernel/setup_opsput.c
	3	*
	4	* Setup routines for Renesas OPSPUT Board
	5	*
	6	* Copyright (c) 2002-2004
	7	* Hiroyuki Kondo, Hirokazu Takata,
	8	* Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
	9	*
	10	* This file is subject to the terms and conditions of the GNU General
	11	* Public License. See the file "COPYING" in the main directory of this
	12	* archive for more details.
	13	*/
	14
	15	#include <linux/config.h>
	16	#include <linux/irq.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/device.h>
	20
	21	#include <asm/system.h>
	22	#include <asm/m32r.h>
	23	#include <asm/io.h>
	24
	25	/*
	26	* OPSP Interrupt Control Unit (Level 1)
	27	*/
	28	#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
	29
	30	#ifndef CONFIG_SMP
	31	typedef struct {
	32	unsigned long icucr; /* ICU Control Register */
	33	} icu_data_t;
	34	#endif /* CONFIG_SMP */
	35
	36	static icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
	37
	38	static void disable_opsput_irq(unsigned int irq)
	39	{
	40	unsigned long port, data;
	41
	42	port = irq2port(irq);
	43	data = icu_data[irq].icucr\|M32R_ICUCR_ILEVEL7;
	44	outl(data, port);
	45	}
	46
	47	static void enable_opsput_irq(unsigned int irq)
	48	{
	49	unsigned long port, data;
	50
	51	port = irq2port(irq);
	52	data = icu_data[irq].icucr\|M32R_ICUCR_IEN\|M32R_ICUCR_ILEVEL6;
	53	outl(data, port);
	54	}
	55
	56	static void mask_and_ack_opsput(unsigned int irq)
	57	{
	58	disable_opsput_irq(irq);
	59	}
	60
	61	static void end_opsput_irq(unsigned int irq)
	62	{
	63	enable_opsput_irq(irq);
	64	}
65
66	static unsigned int startup_opsput_irq(unsigned int irq)
67	{
68	enable_opsput_irq(irq);
69	return (0);
70	}
71
72	static void shutdown_opsput_irq(unsigned int irq)
73	{
74	unsigned long port;
75
76	port = irq2port(irq);
77	outl(M32R_ICUCR_ILEVEL7, port);
78	}
79
80	static struct hw_interrupt_type opsput_irq_type =
81	{
82	"OPSPUT-IRQ",
83	startup_opsput_irq,
84	shutdown_opsput_irq,
85	enable_opsput_irq,
86	disable_opsput_irq,
87	mask_and_ack_opsput,
88	end_opsput_irq
89	};
90
91	/*
92	* Interrupt Control Unit of PLD on OPSPUT (Level 2)
93	*/
94	#define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE)
95	#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
96	(((x) - 1) * sizeof(unsigned short)))
97
98	typedef struct {
99	unsigned short icucr; /* ICU Control Register */
100	} pld_icu_data_t;
101
102	static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
103
104	static void disable_opsput_pld_irq(unsigned int irq)
105	{
106	unsigned long port, data;
107	unsigned int pldirq;
108
109	pldirq = irq2pldirq(irq);
110	// disable_opsput_irq(M32R_IRQ_INT1);
111	port = pldirq2port(pldirq);
112	data = pld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
113	outw(data, port);
114	}
115
116	static void enable_opsput_pld_irq(unsigned int irq)
117	{
118	unsigned long port, data;
119	unsigned int pldirq;
120
121	pldirq = irq2pldirq(irq);
122	// enable_opsput_irq(M32R_IRQ_INT1);
123	port = pldirq2port(pldirq);
124	data = pld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
125	outw(data, port);
126	}
127
128	static void mask_and_ack_opsput_pld(unsigned int irq)
129	{
130	disable_opsput_pld_irq(irq);
131	// mask_and_ack_opsput(M32R_IRQ_INT1);
132	}
133
134	static void end_opsput_pld_irq(unsigned int irq)
135	{
136	enable_opsput_pld_irq(irq);
137	end_opsput_irq(M32R_IRQ_INT1);
138	}
139
140	static unsigned int startup_opsput_pld_irq(unsigned int irq)
141	{
142	enable_opsput_pld_irq(irq);
143	return (0);
144	}
145
146	static void shutdown_opsput_pld_irq(unsigned int irq)
147	{
148	unsigned long port;
149	unsigned int pldirq;
150
151	pldirq = irq2pldirq(irq);
152	// shutdown_opsput_irq(M32R_IRQ_INT1);
153	port = pldirq2port(pldirq);
154	outw(PLD_ICUCR_ILEVEL7, port);
155	}
156
157	static struct hw_interrupt_type opsput_pld_irq_type =
158	{
159	"OPSPUT-PLD-IRQ",
160	startup_opsput_pld_irq,
161	shutdown_opsput_pld_irq,
162	enable_opsput_pld_irq,
163	disable_opsput_pld_irq,
164	mask_and_ack_opsput_pld,
165	end_opsput_pld_irq
166	};
167
168	/*
169	* Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
170	*/
171	#define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
172	#define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
173	(((x) - 1) * sizeof(unsigned short)))
174
175	static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
176
177	static void disable_opsput_lanpld_irq(unsigned int irq)
178	{
179	unsigned long port, data;
180	unsigned int pldirq;
181
182	pldirq = irq2lanpldirq(irq);
183	port = lanpldirq2port(pldirq);
184	data = lanpld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
185	outw(data, port);
186	}
187
188	static void enable_opsput_lanpld_irq(unsigned int irq)
189	{
190	unsigned long port, data;
191	unsigned int pldirq;
192
193	pldirq = irq2lanpldirq(irq);
194	port = lanpldirq2port(pldirq);
195	data = lanpld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
196	outw(data, port);
197	}
198
199	static void mask_and_ack_opsput_lanpld(unsigned int irq)
200	{
201	disable_opsput_lanpld_irq(irq);
202	}
203
204	static void end_opsput_lanpld_irq(unsigned int irq)
205	{
206	enable_opsput_lanpld_irq(irq);
207	end_opsput_irq(M32R_IRQ_INT0);
208	}
209
210	static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
211	{
212	enable_opsput_lanpld_irq(irq);
213	return (0);
214	}
215
216	static void shutdown_opsput_lanpld_irq(unsigned int irq)
217	{
218	unsigned long port;
219	unsigned int pldirq;
220
221	pldirq = irq2lanpldirq(irq);
222	port = lanpldirq2port(pldirq);
223	outw(PLD_ICUCR_ILEVEL7, port);
224	}
225
226	static struct hw_interrupt_type opsput_lanpld_irq_type =
227	{
228	"OPSPUT-PLD-LAN-IRQ",
229	startup_opsput_lanpld_irq,
230	shutdown_opsput_lanpld_irq,
231	enable_opsput_lanpld_irq,
232	disable_opsput_lanpld_irq,
233	mask_and_ack_opsput_lanpld,
234	end_opsput_lanpld_irq
235	};
236
237	/*
238	* Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
239	*/
240	#define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
241	#define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
242	(((x) - 1) * sizeof(unsigned short)))
243
244	static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
245
246	static void disable_opsput_lcdpld_irq(unsigned int irq)
247	{
248	unsigned long port, data;
249	unsigned int pldirq;
250
251	pldirq = irq2lcdpldirq(irq);
252	port = lcdpldirq2port(pldirq);
253	data = lcdpld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
254	outw(data, port);
255	}
256
257	static void enable_opsput_lcdpld_irq(unsigned int irq)
258	{
259	unsigned long port, data;
260	unsigned int pldirq;
261
262	pldirq = irq2lcdpldirq(irq);
263	port = lcdpldirq2port(pldirq);
264	data = lcdpld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
265	outw(data, port);
266	}
267
268	static void mask_and_ack_opsput_lcdpld(unsigned int irq)
269	{
270	disable_opsput_lcdpld_irq(irq);
271	}
272
273	static void end_opsput_lcdpld_irq(unsigned int irq)
274	{
275	enable_opsput_lcdpld_irq(irq);
276	end_opsput_irq(M32R_IRQ_INT2);
277	}
278
279	static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
280	{
281	enable_opsput_lcdpld_irq(irq);
282	return (0);
283	}
284
285	static void shutdown_opsput_lcdpld_irq(unsigned int irq)
286	{
287	unsigned long port;
288	unsigned int pldirq;
289
290	pldirq = irq2lcdpldirq(irq);
291	port = lcdpldirq2port(pldirq);
292	outw(PLD_ICUCR_ILEVEL7, port);
293	}
294
295	static struct hw_interrupt_type opsput_lcdpld_irq_type =
296	{
297	"OPSPUT-PLD-LCD-IRQ",
298	startup_opsput_lcdpld_irq,
299	shutdown_opsput_lcdpld_irq,
300	enable_opsput_lcdpld_irq,
301	disable_opsput_lcdpld_irq,
302	mask_and_ack_opsput_lcdpld,
303	end_opsput_lcdpld_irq
304	};
305
306	void __init init_IRQ(void)
307	{
308	#if defined(CONFIG_SMC91X)
309	/* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
310	irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
311	irq_desc[OPSPUT_LAN_IRQ_LAN].handler = &opsput_lanpld_irq_type;
312	irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
313	irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
314	lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD02; /* "H" edge sense */
315	disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
316	#endif /* CONFIG_SMC91X */
317
318	/* MFT2 : system timer */
319	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
320	irq_desc[M32R_IRQ_MFT2].handler = &opsput_irq_type;
321	irq_desc[M32R_IRQ_MFT2].action = 0;
322	irq_desc[M32R_IRQ_MFT2].depth = 1;
323	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
324	disable_opsput_irq(M32R_IRQ_MFT2);
325
326	/* SIO0 : receive */
327	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
328	irq_desc[M32R_IRQ_SIO0_R].handler = &opsput_irq_type;
329	irq_desc[M32R_IRQ_SIO0_R].action = 0;
330	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
331	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
332	disable_opsput_irq(M32R_IRQ_SIO0_R);
333
334	/* SIO0 : send */
335	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
336	irq_desc[M32R_IRQ_SIO0_S].handler = &opsput_irq_type;
337	irq_desc[M32R_IRQ_SIO0_S].action = 0;
338	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
339	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
340	disable_opsput_irq(M32R_IRQ_SIO0_S);
341
342	/* SIO1 : receive */
343	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
344	irq_desc[M32R_IRQ_SIO1_R].handler = &opsput_irq_type;
345	irq_desc[M32R_IRQ_SIO1_R].action = 0;
346	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
347	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
348	disable_opsput_irq(M32R_IRQ_SIO1_R);
349
350	/* SIO1 : send */
351	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
352	irq_desc[M32R_IRQ_SIO1_S].handler = &opsput_irq_type;
353	irq_desc[M32R_IRQ_SIO1_S].action = 0;
354	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
355	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
356	disable_opsput_irq(M32R_IRQ_SIO1_S);
357
358	/* DMA1 : */
359	irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
360	irq_desc[M32R_IRQ_DMA1].handler = &opsput_irq_type;
361	irq_desc[M32R_IRQ_DMA1].action = 0;
362	irq_desc[M32R_IRQ_DMA1].depth = 1;
363	icu_data[M32R_IRQ_DMA1].icucr = 0;
364	disable_opsput_irq(M32R_IRQ_DMA1);
365
366	#ifdef CONFIG_SERIAL_M32R_PLDSIO
367	/* INT#1: SIO0 Receive on PLD */
368	irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
369	irq_desc[PLD_IRQ_SIO0_RCV].handler = &opsput_pld_irq_type;
370	irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
371	irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
372	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD03;
373	disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
374
375	/* INT#1: SIO0 Send on PLD */
376	irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
377	irq_desc[PLD_IRQ_SIO0_SND].handler = &opsput_pld_irq_type;
378	irq_desc[PLD_IRQ_SIO0_SND].action = 0;
379	irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
380	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD03;
381	disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
382	#endif /* CONFIG_SERIAL_M32R_PLDSIO */
383
384	#if defined(CONFIG_M32R_CFC)
385	/* INT#1: CFC IREQ on PLD */
386	irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
387	irq_desc[PLD_IRQ_CFIREQ].handler = &opsput_pld_irq_type;
388	irq_desc[PLD_IRQ_CFIREQ].action = 0;
389	irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
390	pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD01; /* 'L' level sense */
391	disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
392
393	/* INT#1: CFC Insert on PLD */
394	irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
395	irq_desc[PLD_IRQ_CFC_INSERT].handler = &opsput_pld_irq_type;
396	irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
397	irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
398	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
399	disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
400
401	/* INT#1: CFC Eject on PLD */
402	irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
403	irq_desc[PLD_IRQ_CFC_EJECT].handler = &opsput_pld_irq_type;
404	irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
405	irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
406	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
407	disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
408	#endif /* CONFIG_M32R_CFC */
409
410
411	/*
412	* INT0# is used for LAN, DIO
413	* We enable it here.
414	*/
415	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD11;
416	enable_opsput_irq(M32R_IRQ_INT0);
417
418	/*
419	* INT1# is used for UART, MMC, CF Controller in FPGA.
420	* We enable it here.
421	*/
422	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD11;
423	enable_opsput_irq(M32R_IRQ_INT1);
424
425	#if defined(CONFIG_USB)
426	outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
427
428	irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
429	irq_desc[OPSPUT_LCD_IRQ_USB_INT1].handler = &opsput_lcdpld_irq_type;
430	irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
431	irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
432	lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD01; /* "L" level sense */
433	disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
434	#endif
435	/*
436	* INT2# is used for BAT, USB, AUDIO
437	* We enable it here.
438	*/
439	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD01;
440	enable_opsput_irq(M32R_IRQ_INT2);
441
442	//#if defined(CONFIG_VIDEO_M32R_AR)
443	/*
444	* INT3# is used for AR
445	*/
446	irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
447	irq_desc[M32R_IRQ_INT3].handler = &opsput_irq_type;
448	irq_desc[M32R_IRQ_INT3].action = 0;
449	irq_desc[M32R_IRQ_INT3].depth = 1;
450	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
451	disable_opsput_irq(M32R_IRQ_INT3);
452	//#endif /* CONFIG_VIDEO_M32R_AR */
453	}
454
455	#define LAN_IOSTART 0x300
456	#define LAN_IOEND 0x320
457	static struct resource smc91x_resources[] = {
458	[0] = {
459	.start = (LAN_IOSTART),
460	.end = (LAN_IOEND),
461	.flags = IORESOURCE_MEM,
462	},
463	[1] = {
464	.start = OPSPUT_LAN_IRQ_LAN,
465	.end = OPSPUT_LAN_IRQ_LAN,
466	.flags = IORESOURCE_IRQ,
467	}
468	};
469
470	static struct platform_device smc91x_device = {
471	.name = "smc91x",
472	.id = 0,
473	.num_resources = ARRAY_SIZE(smc91x_resources),
474	.resource = smc91x_resources,
475	};
476
477	static int __init platform_init(void)
478	{
479	platform_device_register(&smc91x_device);
480	return 0;
481	}
482	arch_initcall(platform_init);