[linux-block.git] / arch / m32r / kernel / setup_mappi.c

/*
 *  linux/arch/m32r/kernel/setup_mappi.c
 *
 *  Setup routines for Renesas MAPPI Board
 *
 *  Copyright (c) 2001-2005  Hiroyuki Kondo, Hirokazu Takata,
 *                           Hitoshi Yamamoto
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>

#include <asm/system.h>
#include <asm/m32r.h>
#include <asm/io.h>

#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))

icu_data_t icu_data[NR_IRQS];

static void disable_mappi_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
	outl(data, port);
}

static void enable_mappi_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
	outl(data, port);
}

static void mask_and_ack_mappi(unsigned int irq)
{
	disable_mappi_irq(irq);
}

static void end_mappi_irq(unsigned int irq)
{
	enable_mappi_irq(irq);
}

static unsigned int startup_mappi_irq(unsigned int irq)
{
	enable_mappi_irq(irq);
	return (0);
}

static void shutdown_mappi_irq(unsigned int irq)
{
	unsigned long port;

	port = irq2port(irq);
	outl(M32R_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type mappi_irq_type =
{
	.typename = "MAPPI-IRQ",
	.startup = startup_mappi_irq,
	.shutdown = shutdown_mappi_irq,
	.enable = enable_mappi_irq,
	.disable = disable_mappi_irq,
	.ack = mask_and_ack_mappi,
	.end = end_mappi_irq
};

void __init init_IRQ(void)
{
	static int once = 0;

	if (once)
		return;
	else
		once++;

#ifdef CONFIG_NE2000
	/* INT0 : LAN controller (RTL8019AS) */
	irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type;
	irq_desc[M32R_IRQ_INT0].action = 0;
	irq_desc[M32R_IRQ_INT0].depth = 1;
	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_mappi_irq(M32R_IRQ_INT0);
#endif /* CONFIG_M32R_NE2000 */

	/* MFT2 : system timer */
	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
	irq_desc[M32R_IRQ_MFT2].action = 0;
	irq_desc[M32R_IRQ_MFT2].depth = 1;
	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	disable_mappi_irq(M32R_IRQ_MFT2);

#ifdef CONFIG_SERIAL_M32R_SIO
	/* SIO0_R : uart receive data */
	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
	irq_desc[M32R_IRQ_SIO0_R].action = 0;
	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	disable_mappi_irq(M32R_IRQ_SIO0_R);

	/* SIO0_S : uart send data */
	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
	irq_desc[M32R_IRQ_SIO0_S].action = 0;
	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	disable_mappi_irq(M32R_IRQ_SIO0_S);

	/* SIO1_R : uart receive data */
	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
	irq_desc[M32R_IRQ_SIO1_R].action = 0;
	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	disable_mappi_irq(M32R_IRQ_SIO1_R);

	/* SIO1_S : uart send data */
	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
	irq_desc[M32R_IRQ_SIO1_S].action = 0;
	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	disable_mappi_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_SERIAL_M32R_SIO */

#if defined(CONFIG_M32R_PCC)
	/* INT1 : pccard0 interrupt */
	irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type;
	irq_desc[M32R_IRQ_INT1].action = 0;
	irq_desc[M32R_IRQ_INT1].depth = 1;
	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
	disable_mappi_irq(M32R_IRQ_INT1);

	/* INT2 : pccard1 interrupt */
	irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type;
	irq_desc[M32R_IRQ_INT2].action = 0;
	irq_desc[M32R_IRQ_INT2].depth = 1;
	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
	disable_mappi_irq(M32R_IRQ_INT2);
#endif /* CONFIG_M32RPCC */
}

#if defined(CONFIG_FB_S1D13XXX)

#include <video/s1d13xxxfb.h>
#include <asm/s1d13806.h>

static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
	.initregs		= s1d13xxxfb_initregs,
	.initregssize		= ARRAY_SIZE(s1d13xxxfb_initregs),
	.platform_init_video	= NULL,
#ifdef CONFIG_PM
	.platform_suspend_video	= NULL,
	.platform_resume_video	= NULL,
#endif
};

static struct resource s1d13xxxfb_resources[] = {
	[0] = {
		.start  = 0x10200000UL,
		.end    = 0x1033FFFFUL,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 0x10000000UL,
		.end    = 0x100001FFUL,
		.flags  = IORESOURCE_MEM,
	}
};

static struct platform_device s1d13xxxfb_device = {
	.name		= S1D_DEVICENAME,
	.id		= 0,
	.dev            = {
		.platform_data  = &s1d13xxxfb_data,
	},
	.num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
	.resource       = s1d13xxxfb_resources,
};

static int __init platform_init(void)
{
	platform_device_register(&s1d13xxxfb_device);
	return 0;
}
arch_initcall(platform_init);
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/m32r/kernel/setup_mappi.c
	3	*
	4	* Setup routines for Renesas MAPPI Board
	5	*
316240f6 HT	6	* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
316240f6 HT	7	* Hitoshi Yamamoto
1da177e4 LT	8	*/
1da177e4 LT	9
1da177e4 LT	10	#include <linux/irq.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
d052d1be	13	#include <linux/platform_device.h>
1da177e4 LT	14
	15	#include <asm/system.h>
	16	#include <asm/m32r.h>
	17	#include <asm/io.h>
	18
	19	#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
	20
1da177e4 LT	21	icu_data_t icu_data[NR_IRQS];
	22
	23	static void disable_mappi_irq(unsigned int irq)
	24	{
	25	unsigned long port, data;
	26
	27	port = irq2port(irq);
	28	data = icu_data[irq].icucr\|M32R_ICUCR_ILEVEL7;
	29	outl(data, port);
	30	}
	31
	32	static void enable_mappi_irq(unsigned int irq)
	33	{
	34	unsigned long port, data;
	35
	36	port = irq2port(irq);
	37	data = icu_data[irq].icucr\|M32R_ICUCR_IEN\|M32R_ICUCR_ILEVEL6;
	38	outl(data, port);
	39	}
	40
	41	static void mask_and_ack_mappi(unsigned int irq)
	42	{
	43	disable_mappi_irq(irq);
	44	}
	45
	46	static void end_mappi_irq(unsigned int irq)
	47	{
	48	enable_mappi_irq(irq);
	49	}
	50
	51	static unsigned int startup_mappi_irq(unsigned int irq)
	52	{
	53	enable_mappi_irq(irq);
	54	return (0);
	55	}
	56
	57	static void shutdown_mappi_irq(unsigned int irq)
	58	{
	59	unsigned long port;
	60
	61	port = irq2port(irq);
	62	outl(M32R_ICUCR_ILEVEL7, port);
	63	}
	64
	65	static struct hw_interrupt_type mappi_irq_type =
	66	{
6f973b00 HT	67	.typename = "MAPPI-IRQ",
	68	.startup = startup_mappi_irq,
	69	.shutdown = shutdown_mappi_irq,
	70	.enable = enable_mappi_irq,
	71	.disable = disable_mappi_irq,
	72	.ack = mask_and_ack_mappi,
	73	.end = end_mappi_irq
1da177e4 LT	74	};
	75
	76	void __init init_IRQ(void)
	77	{
	78	static int once = 0;
	79
	80	if (once)
	81	return;
	82	else
	83	once++;
	84
	85	#ifdef CONFIG_NE2000
	86	/* INT0 : LAN controller (RTL8019AS) */
	87	irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
d1bef4ed	88	irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type;
1da177e4 LT	89	irq_desc[M32R_IRQ_INT0].action = 0;
	90	irq_desc[M32R_IRQ_INT0].depth = 1;
	91	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
	92	disable_mappi_irq(M32R_IRQ_INT0);
	93	#endif /* CONFIG_M32R_NE2000 */
	94
	95	/* MFT2 : system timer */
	96	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
d1bef4ed	97	irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
1da177e4 LT	98	irq_desc[M32R_IRQ_MFT2].action = 0;
	99	irq_desc[M32R_IRQ_MFT2].depth = 1;
	100	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	101	disable_mappi_irq(M32R_IRQ_MFT2);
	102
	103	#ifdef CONFIG_SERIAL_M32R_SIO
	104	/* SIO0_R : uart receive data */
	105	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
d1bef4ed	106	irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
1da177e4 LT	107	irq_desc[M32R_IRQ_SIO0_R].action = 0;
	108	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
	109	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	110	disable_mappi_irq(M32R_IRQ_SIO0_R);
	111
	112	/* SIO0_S : uart send data */
	113	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
d1bef4ed	114	irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
1da177e4 LT	115	irq_desc[M32R_IRQ_SIO0_S].action = 0;
	116	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
	117	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	118	disable_mappi_irq(M32R_IRQ_SIO0_S);
	119
	120	/* SIO1_R : uart receive data */
	121	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
d1bef4ed	122	irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
1da177e4 LT	123	irq_desc[M32R_IRQ_SIO1_R].action = 0;
	124	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
	125	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	126	disable_mappi_irq(M32R_IRQ_SIO1_R);
	127
	128	/* SIO1_S : uart send data */
	129	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
d1bef4ed	130	irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
1da177e4 LT	131	irq_desc[M32R_IRQ_SIO1_S].action = 0;
	132	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
	133	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	134	disable_mappi_irq(M32R_IRQ_SIO1_S);
	135	#endif /* CONFIG_SERIAL_M32R_SIO */
	136
	137	#if defined(CONFIG_M32R_PCC)
	138	/* INT1 : pccard0 interrupt */
	139	irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
d1bef4ed	140	irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type;
1da177e4 LT	141	irq_desc[M32R_IRQ_INT1].action = 0;
	142	irq_desc[M32R_IRQ_INT1].depth = 1;
	143	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN \| M32R_ICUCR_ISMOD00;
	144	disable_mappi_irq(M32R_IRQ_INT1);
	145
	146	/* INT2 : pccard1 interrupt */
	147	irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED;
d1bef4ed	148	irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type;
1da177e4 LT	149	irq_desc[M32R_IRQ_INT2].action = 0;
	150	irq_desc[M32R_IRQ_INT2].depth = 1;
	151	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN \| M32R_ICUCR_ISMOD00;
	152	disable_mappi_irq(M32R_IRQ_INT2);
	153	#endif /* CONFIG_M32RPCC */
	154	}
316240f6 HT	155
	156	#if defined(CONFIG_FB_S1D13XXX)
	157
	158	#include <video/s1d13xxxfb.h>
	159	#include <asm/s1d13806.h>
	160
	161	static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
	162	.initregs = s1d13xxxfb_initregs,
	163	.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
	164	.platform_init_video = NULL,
	165	#ifdef CONFIG_PM
	166	.platform_suspend_video = NULL,
	167	.platform_resume_video = NULL,
	168	#endif
	169	};
	170
	171	static struct resource s1d13xxxfb_resources[] = {
	172	[0] = {
	173	.start = 0x10200000UL,
	174	.end = 0x1033FFFFUL,
	175	.flags = IORESOURCE_MEM,
	176	},
	177	[1] = {
	178	.start = 0x10000000UL,
	179	.end = 0x100001FFUL,
	180	.flags = IORESOURCE_MEM,
	181	}
	182	};
	183
	184	static struct platform_device s1d13xxxfb_device = {
	185	.name = S1D_DEVICENAME,
	186	.id = 0,
	187	.dev = {
	188	.platform_data = &s1d13xxxfb_data,
	189	},
	190	.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
	191	.resource = s1d13xxxfb_resources,
	192	};
	193
	194	static int __init platform_init(void)
	195	{
	196	platform_device_register(&s1d13xxxfb_device);
	197	return 0;
	198	}
	199	arch_initcall(platform_init);
	200	#endif