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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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2 | /* |
3 | * linux/arch/m32r/boot/setup.S -- A setup code. | |
4 | * | |
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5 | * Copyright (C) 2001-2005 Hiroyuki Kondo, Hirokazu Takata, |
6 | * Hitoshi Yamamoto, Hayato Fujiwara | |
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7 | * |
8 | */ | |
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9 | |
10 | #include <linux/linkage.h> | |
11 | #include <asm/segment.h> | |
12 | #include <asm/page.h> | |
13 | #include <asm/pgtable.h> | |
14 | ||
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15 | #include <asm/assembler.h> |
16 | #include <asm/mmu_context.h> | |
17 | #include <asm/m32r.h> | |
18 | ||
19 | /* | |
20 | * References to members of the boot_cpu_data structure. | |
21 | */ | |
22 | ||
23 | #define CPU_PARAMS boot_cpu_data | |
24 | #define M32R_MCICAR 0xfffffff0 | |
25 | #define M32R_MCDCAR 0xfffffff4 | |
26 | #define M32R_MCCR 0xfffffffc | |
27 | #define M32R_BSCR0 0xffffffd2 | |
28 | ||
29 | ;BSEL | |
30 | #define BSEL0CR0 0x00ef5000 | |
31 | #define BSEL0CR1 0x00ef5004 | |
32 | #define BSEL1CR0 0x00ef5100 | |
33 | #define BSEL1CR1 0x00ef5104 | |
34 | #define BSEL0CR0_VAL 0x00000000 | |
35 | #define BSEL0CR1_VAL 0x01200100 | |
36 | #define BSEL1CR0_VAL 0x01018000 | |
37 | #define BSEL1CR1_VAL 0x00200001 | |
38 | ||
39 | ;SDRAMC | |
40 | #define SDRAMC_SDRF0 0x00ef6000 | |
41 | #define SDRAMC_SDRF1 0x00ef6004 | |
42 | #define SDRAMC_SDIR0 0x00ef6008 | |
43 | #define SDRAMC_SDIR1 0x00ef600c | |
44 | #define SDRAMC_SD0ADR 0x00ef6020 | |
45 | #define SDRAMC_SD0ER 0x00ef6024 | |
46 | #define SDRAMC_SD0TR 0x00ef6028 | |
47 | #define SDRAMC_SD0MOD 0x00ef602c | |
48 | #define SDRAMC_SD1ADR 0x00ef6040 | |
49 | #define SDRAMC_SD1ER 0x00ef6044 | |
50 | #define SDRAMC_SD1TR 0x00ef6048 | |
51 | #define SDRAMC_SD1MOD 0x00ef604c | |
52 | #define SDRAM0 0x18000000 | |
53 | #define SDRAM1 0x1c000000 | |
54 | ||
55 | /*------------------------------------------------------------------------ | |
56 | * start up | |
57 | */ | |
58 | ||
59 | /*------------------------------------------------------------------------ | |
60 | * Kernel entry | |
61 | */ | |
62 | .section .boot, "ax" | |
63 | ENTRY(boot) | |
64 | ||
65 | /* Set cache mode */ | |
66 | #if defined(CONFIG_CHIP_XNUX2) | |
67 | ldi r0, #-2 ;LDIMM (r0, M32R_MCCR) | |
68 | ldi r1, #0x0101 ; cache on (with invalidation) | |
69 | ; ldi r1, #0x00 ; cache off | |
70 | sth r1, @r0 | |
71 | #elif defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) \ | |
72 | || defined(CONFIG_CHIP_OPSP) | |
73 | ldi r0, #-4 ;LDIMM (r0, M32R_MCCR) | |
74 | ldi r1, #0x73 ; cache on (with invalidation) | |
75 | ; ldi r1, #0x00 ; cache off | |
76 | st r1, @r0 | |
77 | #elif defined(CONFIG_CHIP_M32102) | |
78 | ldi r0, #-4 ;LDIMM (r0, M32R_MCCR) | |
79 | ldi r1, #0x101 ; cache on (with invalidation) | |
80 | ; ldi r1, #0x00 ; cache off | |
81 | st r1, @r0 | |
9287d95e | 82 | #elif defined(CONFIG_CHIP_M32104) |
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83 | ldi r0, #-96 ; DNCR0 |
84 | seth r1, #0x0060 ; from 0x00600000 | |
85 | or3 r1, r1, #0x0005 ; size 2MB | |
86 | st r1, @r0 | |
87 | seth r1, #0x0100 ; from 0x01000000 | |
88 | or3 r1, r1, #0x0003 ; size 16MB | |
89 | st r1, @+r0 | |
90 | seth r1, #0x0200 ; from 0x02000000 | |
91 | or3 r1, r1, #0x0002 ; size 32MB | |
92 | st r1, @+r0 | |
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93 | ldi r0, #-4 ;LDIMM (r0, M32R_MCCR) |
94 | ldi r1, #0x703 ; cache on (with invalidation) | |
95 | st r1, @r0 | |
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96 | #else |
97 | #error unknown chip configuration | |
98 | #endif | |
99 | ||
100 | #ifdef CONFIG_SMP | |
101 | ;; if not BSP (CPU#0) goto AP_loop | |
102 | seth r5, #shigh(M32R_CPUID_PORTL) | |
103 | ld r5, @(low(M32R_CPUID_PORTL), r5) | |
104 | bnez r5, AP_loop | |
105 | #if !defined(CONFIG_PLAT_USRV) | |
106 | ;; boot AP | |
107 | ld24 r5, #0xeff2f8 ; IPICR7 | |
108 | ldi r6, #0x2 ; IPI to CPU1 | |
109 | st r6, @r5 | |
110 | #endif | |
111 | #endif | |
112 | ||
113 | /* | |
114 | * Now, Jump to stext | |
115 | * if with MMU, TLB on. | |
116 | * if with no MMU, only jump. | |
117 | */ | |
118 | .global eit_vector | |
119 | mmu_on: | |
120 | LDIMM (r13, stext) | |
121 | #ifdef CONFIG_MMU | |
122 | bl init_tlb | |
123 | LDIMM (r2, eit_vector) ; set EVB(cr5) | |
124 | mvtc r2, cr5 | |
125 | seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher | |
126 | or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower | |
127 | ldi r1, #0x01 | |
128 | st r1, @(MATM_offset,r0) ; Set MATM (T bit ON) | |
129 | ld r0, @(MATM_offset,r0) ; Check | |
130 | #else | |
9287d95e | 131 | #if defined(CONFIG_CHIP_M32700) |
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132 | seth r0,#high(M32R_MCDCAR) |
133 | or3 r0,r0,#low(M32R_MCDCAR) | |
134 | ld24 r1,#0x8080 | |
135 | st r1,@r0 | |
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136 | #elif defined(CONFIG_CHIP_M32104) |
137 | LDIMM (r2, eit_vector) ; set EVB(cr5) | |
138 | mvtc r2, cr5 | |
139 | #endif | |
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140 | #endif /* CONFIG_MMU */ |
141 | jmp r13 | |
142 | nop | |
143 | nop | |
144 | ||
145 | #ifdef CONFIG_SMP | |
146 | /* | |
147 | * AP wait loop | |
148 | */ | |
149 | ENTRY(AP_loop) | |
150 | ;; disable interrupt | |
151 | clrpsw #0x40 | |
152 | ;; reset EVB | |
153 | LDIMM (r4, _AP_RE) | |
154 | seth r5, #high(__PAGE_OFFSET) | |
155 | or3 r5, r5, #low(__PAGE_OFFSET) | |
156 | not r5, r5 | |
157 | and r4, r5 | |
158 | mvtc r4, cr5 | |
159 | ;; disable maskable interrupt | |
160 | seth r4, #high(M32R_ICU_IMASK_PORTL) | |
161 | or3 r4, r4, #low(M32R_ICU_IMASK_PORTL) | |
162 | ldi r5, #0 | |
163 | st r5, @r4 | |
164 | ld r5, @r4 | |
165 | ;; enable only IPI | |
166 | setpsw #0x40 | |
167 | ;; LOOOOOOOOOOOOOOP!!! | |
168 | .fillinsn | |
169 | 2: | |
170 | nop | |
171 | nop | |
172 | bra 2b | |
173 | nop | |
174 | nop | |
175 | ||
176 | #ifdef CONFIG_CHIP_M32700_TS1 | |
177 | .global dcache_dummy | |
178 | .balign 16, 0 | |
179 | dcache_dummy: | |
180 | .byte 16 | |
181 | #endif /* CONFIG_CHIP_M32700_TS1 */ | |
182 | #endif /* CONFIG_SMP */ | |
183 | ||
184 | .end | |
185 |