[linux-block.git] / arch / loongarch / kernel / time.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Common time service routines for LoongArch machines.
 *
 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
 */
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/sched_clock.h>
#include <linux/spinlock.h>

#include <asm/cpu-features.h>
#include <asm/loongarch.h>
#include <asm/time.h>

u64 cpu_clock_freq;
EXPORT_SYMBOL(cpu_clock_freq);
u64 const_clock_freq;
EXPORT_SYMBOL(const_clock_freq);

static DEFINE_RAW_SPINLOCK(state_lock);
static DEFINE_PER_CPU(struct clock_event_device, constant_clockevent_device);

static void constant_event_handler(struct clock_event_device *dev)
{
}

static irqreturn_t constant_timer_interrupt(int irq, void *data)
{
	int cpu = smp_processor_id();
	struct clock_event_device *cd;

	/* Clear Timer Interrupt */
	write_csr_tintclear(CSR_TINTCLR_TI);
	cd = &per_cpu(constant_clockevent_device, cpu);
	cd->event_handler(cd);

	return IRQ_HANDLED;
}

static int constant_set_state_oneshot(struct clock_event_device *evt)
{
	unsigned long timer_config;

	raw_spin_lock(&state_lock);

	timer_config = csr_read64(LOONGARCH_CSR_TCFG);
	timer_config |= CSR_TCFG_EN;
	timer_config &= ~CSR_TCFG_PERIOD;
	csr_write64(timer_config, LOONGARCH_CSR_TCFG);

	raw_spin_unlock(&state_lock);

	return 0;
}

static int constant_set_state_oneshot_stopped(struct clock_event_device *evt)
{
	unsigned long timer_config;

	raw_spin_lock(&state_lock);

	timer_config = csr_read64(LOONGARCH_CSR_TCFG);
	timer_config &= ~CSR_TCFG_EN;
	csr_write64(timer_config, LOONGARCH_CSR_TCFG);

	raw_spin_unlock(&state_lock);

	return 0;
}

static int constant_set_state_periodic(struct clock_event_device *evt)
{
	unsigned long period;
	unsigned long timer_config;

	raw_spin_lock(&state_lock);

	period = const_clock_freq / HZ;
	timer_config = period & CSR_TCFG_VAL;
	timer_config |= (CSR_TCFG_PERIOD | CSR_TCFG_EN);
	csr_write64(timer_config, LOONGARCH_CSR_TCFG);

	raw_spin_unlock(&state_lock);

	return 0;
}

static int constant_set_state_shutdown(struct clock_event_device *evt)
{
	return 0;
}

static int constant_timer_next_event(unsigned long delta, struct clock_event_device *evt)
{
	unsigned long timer_config;

	delta &= CSR_TCFG_VAL;
	timer_config = delta | CSR_TCFG_EN;
	csr_write64(timer_config, LOONGARCH_CSR_TCFG);

	return 0;
}

static unsigned long __init get_loops_per_jiffy(void)
{
	unsigned long lpj = (unsigned long)const_clock_freq;

	do_div(lpj, HZ);

	return lpj;
}

static long init_offset __nosavedata;

void save_counter(void)
{
	init_offset = drdtime();
}

void sync_counter(void)
{
	/* Ensure counter begin at 0 */
	csr_write64(init_offset, LOONGARCH_CSR_CNTC);
}

static int get_timer_irq(void)
{
	struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);

	if (d)
		return irq_create_mapping(d, INT_TI);

	return -EINVAL;
}

int constant_clockevent_init(void)
{
	unsigned int cpu = smp_processor_id();
	unsigned long min_delta = 0x600;
	unsigned long max_delta = (1UL << 48) - 1;
	struct clock_event_device *cd;
	static int irq = 0, timer_irq_installed = 0;

	if (!timer_irq_installed) {
		irq = get_timer_irq();
		if (irq < 0)
			pr_err("Failed to map irq %d (timer)\n", irq);
	}

	cd = &per_cpu(constant_clockevent_device, cpu);

	cd->name = "Constant";
	cd->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_PERCPU;

	cd->irq = irq;
	cd->rating = 320;
	cd->cpumask = cpumask_of(cpu);
	cd->set_state_oneshot = constant_set_state_oneshot;
	cd->set_state_oneshot_stopped = constant_set_state_oneshot_stopped;
	cd->set_state_periodic = constant_set_state_periodic;
	cd->set_state_shutdown = constant_set_state_shutdown;
	cd->set_next_event = constant_timer_next_event;
	cd->event_handler = constant_event_handler;

	clockevents_config_and_register(cd, const_clock_freq, min_delta, max_delta);

	if (timer_irq_installed)
		return 0;

	timer_irq_installed = 1;

	sync_counter();

	if (request_irq(irq, constant_timer_interrupt, IRQF_PERCPU | IRQF_TIMER, "timer", NULL))
		pr_err("Failed to request irq %d (timer)\n", irq);

	lpj_fine = get_loops_per_jiffy();
	pr_info("Constant clock event device register\n");

	return 0;
}

static u64 read_const_counter(struct clocksource *clk)
{
	return drdtime();
}

static noinstr u64 sched_clock_read(void)
{
	return drdtime();
}

static struct clocksource clocksource_const = {
	.name = "Constant",
	.rating = 400,
	.read = read_const_counter,
	.mask = CLOCKSOURCE_MASK(64),
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	.vdso_clock_mode = VDSO_CLOCKMODE_CPU,
};

int __init constant_clocksource_init(void)
{
	int res;
	unsigned long freq = const_clock_freq;

	res = clocksource_register_hz(&clocksource_const, freq);

	sched_clock_register(sched_clock_read, 64, freq);

	pr_info("Constant clock source device register\n");

	return res;
}

void __init time_init(void)
{
	if (!cpu_has_cpucfg)
		const_clock_freq = cpu_clock_freq;
	else
		const_clock_freq = calc_const_freq();

	init_offset = -(drdtime() - csr_read64(LOONGARCH_CSR_CNTC));

	constant_clockevent_init();
	constant_clocksource_init();
}
Commit	Line	Data
628c3bb4 HC	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Common time service routines for LoongArch machines.
	4	*
	5	* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
	6	*/
	7	#include <linux/clockchips.h>
	8	#include <linux/delay.h>
	9	#include <linux/export.h>
	10	#include <linux/init.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched_clock.h>
	14	#include <linux/spinlock.h>
	15
	16	#include <asm/cpu-features.h>
	17	#include <asm/loongarch.h>
	18	#include <asm/time.h>
	19
	20	u64 cpu_clock_freq;
	21	EXPORT_SYMBOL(cpu_clock_freq);
	22	u64 const_clock_freq;
	23	EXPORT_SYMBOL(const_clock_freq);
	24
	25	static DEFINE_RAW_SPINLOCK(state_lock);
	26	static DEFINE_PER_CPU(struct clock_event_device, constant_clockevent_device);
	27
	28	static void constant_event_handler(struct clock_event_device *dev)
	29	{
	30	}
	31
c718a0ba	32	static irqreturn_t constant_timer_interrupt(int irq, void *data)
628c3bb4 HC	33	{
	34	int cpu = smp_processor_id();
	35	struct clock_event_device *cd;
	36
	37	/* Clear Timer Interrupt */
	38	write_csr_tintclear(CSR_TINTCLR_TI);
	39	cd = &per_cpu(constant_clockevent_device, cpu);
	40	cd->event_handler(cd);
	41
	42	return IRQ_HANDLED;
	43	}
	44
	45	static int constant_set_state_oneshot(struct clock_event_device *evt)
	46	{
	47	unsigned long timer_config;
	48
	49	raw_spin_lock(&state_lock);
	50
	51	timer_config = csr_read64(LOONGARCH_CSR_TCFG);
	52	timer_config \|= CSR_TCFG_EN;
	53	timer_config &= ~CSR_TCFG_PERIOD;
	54	csr_write64(timer_config, LOONGARCH_CSR_TCFG);
	55
	56	raw_spin_unlock(&state_lock);
	57
	58	return 0;
	59	}
	60
	61	static int constant_set_state_oneshot_stopped(struct clock_event_device *evt)
	62	{
	63	unsigned long timer_config;
	64
	65	raw_spin_lock(&state_lock);
	66
	67	timer_config = csr_read64(LOONGARCH_CSR_TCFG);
	68	timer_config &= ~CSR_TCFG_EN;
	69	csr_write64(timer_config, LOONGARCH_CSR_TCFG);
	70
	71	raw_spin_unlock(&state_lock);
	72
	73	return 0;
	74	}
	75
	76	static int constant_set_state_periodic(struct clock_event_device *evt)
	77	{
	78	unsigned long period;
	79	unsigned long timer_config;
	80
	81	raw_spin_lock(&state_lock);
	82
	83	period = const_clock_freq / HZ;
	84	timer_config = period & CSR_TCFG_VAL;
	85	timer_config \|= (CSR_TCFG_PERIOD \| CSR_TCFG_EN);
	86	csr_write64(timer_config, LOONGARCH_CSR_TCFG);
	87
	88	raw_spin_unlock(&state_lock);
	89
	90	return 0;
	91	}
	92
	93	static int constant_set_state_shutdown(struct clock_event_device *evt)
	94	{
	95	return 0;
	96	}
97
98	static int constant_timer_next_event(unsigned long delta, struct clock_event_device *evt)
99	{
100	unsigned long timer_config;
101
102	delta &= CSR_TCFG_VAL;
103	timer_config = delta \| CSR_TCFG_EN;
104	csr_write64(timer_config, LOONGARCH_CSR_TCFG);
105
106	return 0;
107	}
108
109	static unsigned long __init get_loops_per_jiffy(void)
110	{
111	unsigned long lpj = (unsigned long)const_clock_freq;
112
113	do_div(lpj, HZ);
114
115	return lpj;
116	}
117
366bb35a HC	118	static long init_offset __nosavedata;
	119
	120	void save_counter(void)
	121	{
	122	init_offset = drdtime();
	123	}
628c3bb4 HC	124
	125	void sync_counter(void)
	126	{
	127	/* Ensure counter begin at 0 */
366bb35a	128	csr_write64(init_offset, LOONGARCH_CSR_CNTC);
628c3bb4 HC	129	}
628c3bb4 HC	130
b2d3e335 HC	131	static int get_timer_irq(void)
	132	{
	133	struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
	134
	135	if (d)
9e36fa42	136	return irq_create_mapping(d, INT_TI);
b2d3e335 HC	137
	138	return -EINVAL;
	139	}
	140
628c3bb4 HC	141	int constant_clockevent_init(void)
628c3bb4 HC	142	{
628c3bb4 HC	143	unsigned int cpu = smp_processor_id();
	144	unsigned long min_delta = 0x600;
	145	unsigned long max_delta = (1UL << 48) - 1;
	146	struct clock_event_device *cd;
bb7a78e3	147	static int irq = 0, timer_irq_installed = 0;
628c3bb4	148
bb7a78e3 TY	149	if (!timer_irq_installed) {
	150	irq = get_timer_irq();
	151	if (irq < 0)
	152	pr_err("Failed to map irq %d (timer)\n", irq);
	153	}
628c3bb4 HC	154
	155	cd = &per_cpu(constant_clockevent_device, cpu);
	156
	157	cd->name = "Constant";
	158	cd->features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_PERCPU;
	159
	160	cd->irq = irq;
	161	cd->rating = 320;
	162	cd->cpumask = cpumask_of(cpu);
	163	cd->set_state_oneshot = constant_set_state_oneshot;
	164	cd->set_state_oneshot_stopped = constant_set_state_oneshot_stopped;
	165	cd->set_state_periodic = constant_set_state_periodic;
	166	cd->set_state_shutdown = constant_set_state_shutdown;
	167	cd->set_next_event = constant_timer_next_event;
	168	cd->event_handler = constant_event_handler;
	169
	170	clockevents_config_and_register(cd, const_clock_freq, min_delta, max_delta);
	171
	172	if (timer_irq_installed)
	173	return 0;
	174
	175	timer_irq_installed = 1;
	176
	177	sync_counter();
	178
	179	if (request_irq(irq, constant_timer_interrupt, IRQF_PERCPU \| IRQF_TIMER, "timer", NULL))
	180	pr_err("Failed to request irq %d (timer)\n", irq);
	181
	182	lpj_fine = get_loops_per_jiffy();
	183	pr_info("Constant clock event device register\n");
	184
	185	return 0;
	186	}
	187
	188	static u64 read_const_counter(struct clocksource *clk)
	189	{
	190	return drdtime();
	191	}
	192
6b10fef0	193	static noinstr u64 sched_clock_read(void)
628c3bb4	194	{
6b10fef0	195	return drdtime();
628c3bb4 HC	196	}
	197
	198	static struct clocksource clocksource_const = {
	199	.name = "Constant",
	200	.rating = 400,
	201	.read = read_const_counter,
	202	.mask = CLOCKSOURCE_MASK(64),
	203	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
c6b99bed	204	.vdso_clock_mode = VDSO_CLOCKMODE_CPU,
628c3bb4 HC	205	};
	206
	207	int __init constant_clocksource_init(void)
	208	{
	209	int res;
	210	unsigned long freq = const_clock_freq;
	211
	212	res = clocksource_register_hz(&clocksource_const, freq);
	213
6b10fef0	214	sched_clock_register(sched_clock_read, 64, freq);
628c3bb4 HC	215
	216	pr_info("Constant clock source device register\n");
	217
	218	return res;
	219	}
	220
	221	void __init time_init(void)
	222	{
	223	if (!cpu_has_cpucfg)
	224	const_clock_freq = cpu_clock_freq;
	225	else
	226	const_clock_freq = calc_const_freq();
	227
366bb35a	228	init_offset = -(drdtime() - csr_read64(LOONGARCH_CSR_CNTC));
628c3bb4 HC	229
	230	constant_clockevent_init();
	231	constant_clocksource_init();
	232	}