projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| f2ac457a HC |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* | |
| 3 | * Copyright (C) 2020-2022 Loongson Technology Corporation Limited | |
| 4 | * | |
| 5 | * Derived from MIPS: | |
| 6 | * Copyright (C) 1996, 99 Ralf Baechle | |
| 7 | * Copyright (C) 2000, 2002 Maciej W. Rozycki | |
| 8 | * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. | |
| 9 | */ | |
| 10 | #ifndef _ASM_ADDRSPACE_H | |
| 11 | #define _ASM_ADDRSPACE_H | |
| 12 | ||
| 13 | #include <linux/const.h> | |
| a07c772f | 14 | #include <linux/sizes.h> |
| f2ac457a HC |
15 | |
| 16 | #include <asm/loongarch.h> | |
| 17 | ||
| 18 | /* | |
| 19 | * This gives the physical RAM offset. | |
| 20 | */ | |
| f0ef0b02 | 21 | #ifndef __ASSEMBLER__ |
| f2ac457a | 22 | #ifndef PHYS_OFFSET |
| 3563b477 | 23 | #define PHYS_OFFSET _UL(0) |
| f2ac457a HC |
24 | #endif |
| 25 | extern unsigned long vm_map_base; | |
| f0ef0b02 | 26 | #endif /* __ASSEMBLER__ */ |
| f2ac457a HC |
27 | |
| 28 | #ifndef IO_BASE | |
| 29 | #define IO_BASE CSR_DMW0_BASE | |
| 30 | #endif | |
| 31 | ||
| 32 | #ifndef CACHE_BASE | |
| 33 | #define CACHE_BASE CSR_DMW1_BASE | |
| 34 | #endif | |
| 35 | ||
| 36 | #ifndef UNCACHE_BASE | |
| 37 | #define UNCACHE_BASE CSR_DMW0_BASE | |
| 38 | #endif | |
| 39 | ||
| 8e02c3b7 HC |
40 | #ifndef WRITECOMBINE_BASE |
| 41 | #define WRITECOMBINE_BASE CSR_DMW2_BASE | |
| 42 | #endif | |
| 43 | ||
| f2ac457a HC |
44 | #define DMW_PABITS 48 |
| 45 | #define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1) | |
| 46 | ||
| 47 | /* | |
| 48 | * Memory above this physical address will be considered highmem. | |
| 49 | */ | |
| 50 | #ifndef HIGHMEM_START | |
| 3563b477 | 51 | #define HIGHMEM_START (_UL(1) << _UL(DMW_PABITS)) |
| f2ac457a HC |
52 | #endif |
| 53 | ||
| 54 | #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) | |
| 55 | #define TO_CACHE(x) (CACHE_BASE | ((x) & TO_PHYS_MASK)) | |
| 56 | #define TO_UNCACHE(x) (UNCACHE_BASE | ((x) & TO_PHYS_MASK)) | |
| 57 | ||
| 58 | /* | |
| 59 | * This handles the memory map. | |
| 60 | */ | |
| 61 | #ifndef PAGE_OFFSET | |
| 62 | #define PAGE_OFFSET (CACHE_BASE + PHYS_OFFSET) | |
| 63 | #endif | |
| 64 | ||
| 65 | #ifndef FIXADDR_TOP | |
| 66 | #define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) | |
| 67 | #endif | |
| 68 | ||
| f0ef0b02 | 69 | #ifdef __ASSEMBLER__ |
| f2ac457a HC |
70 | #define _ATYPE_ |
| 71 | #define _ATYPE32_ | |
| 72 | #define _ATYPE64_ | |
| f2ac457a HC |
73 | #else |
| 74 | #define _ATYPE_ __PTRDIFF_TYPE__ | |
| 75 | #define _ATYPE32_ int | |
| 76 | #define _ATYPE64_ __s64 | |
| 3563b477 AS |
77 | #endif |
| 78 | ||
| f2ac457a | 79 | #ifdef CONFIG_64BIT |
| 3563b477 | 80 | #define _CONST64_(x) _UL(x) |
| f2ac457a | 81 | #else |
| 3563b477 | 82 | #define _CONST64_(x) _ULL(x) |
| f2ac457a HC |
83 | #endif |
| 84 | ||
| 85 | /* | |
| 86 | * 32/64-bit LoongArch address spaces | |
| 87 | */ | |
| f0ef0b02 | 88 | #ifdef __ASSEMBLER__ |
| f2ac457a HC |
89 | #define _ACAST32_ |
| 90 | #define _ACAST64_ | |
| 91 | #else | |
| 92 | #define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ | |
| 93 | #define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ | |
| 94 | #endif | |
| 95 | ||
| 96 | #ifdef CONFIG_32BIT | |
| 97 | ||
| 98 | #define UVRANGE 0x00000000 | |
| 99 | #define KPRANGE0 0x80000000 | |
| 100 | #define KPRANGE1 0xa0000000 | |
| 101 | #define KVRANGE 0xc0000000 | |
| 102 | ||
| 103 | #else | |
| 104 | ||
| 105 | #define XUVRANGE _CONST64_(0x0000000000000000) | |
| 106 | #define XSPRANGE _CONST64_(0x4000000000000000) | |
| 107 | #define XKPRANGE _CONST64_(0x8000000000000000) | |
| 108 | #define XKVRANGE _CONST64_(0xc000000000000000) | |
| 109 | ||
| 110 | #endif | |
| 111 | ||
| 112 | /* | |
| 113 | * Returns the physical address of a KPRANGEx / XKPRANGE address | |
| 114 | */ | |
| 115 | #define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK) | |
| 116 | ||
| 092e9ebe HC |
117 | /* |
| 118 | * On LoongArch, I/O ports mappring is following: | |
| 119 | * | |
| 120 | * | .... | | |
| 121 | * |-----------------------| | |
| 122 | * | pci io ports(16K~32M) | | |
| 123 | * |-----------------------| | |
| 124 | * | isa io ports(0 ~16K) | | |
| 125 | * PCI_IOBASE ->|-----------------------| | |
| 126 | * | .... | | |
| 127 | */ | |
| 128 | #define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE))) | |
| 129 | #define PCI_IOSIZE SZ_32M | |
| 130 | #define ISA_IOSIZE SZ_16K | |
| 131 | #define IO_SPACE_LIMIT (PCI_IOSIZE - 1) | |
| 132 | ||
| 3f89765d YT |
133 | #define PHYS_LINK_KADDR PHYSADDR(VMLINUX_LOAD_ADDRESS) |
| 134 | ||
| f2ac457a | 135 | #endif /* _ASM_ADDRSPACE_H */ |