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1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (C) 2020-2022 Loongson Technology Corporation Limited | |
4 | * | |
5 | * Derived from MIPS: | |
6 | * Copyright (C) 1996, 99 Ralf Baechle | |
7 | * Copyright (C) 2000, 2002 Maciej W. Rozycki | |
8 | * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. | |
9 | */ | |
10 | #ifndef _ASM_ADDRSPACE_H | |
11 | #define _ASM_ADDRSPACE_H | |
12 | ||
13 | #include <linux/const.h> | |
a07c772f | 14 | #include <linux/sizes.h> |
f2ac457a HC |
15 | |
16 | #include <asm/loongarch.h> | |
17 | ||
18 | /* | |
19 | * This gives the physical RAM offset. | |
20 | */ | |
21 | #ifndef __ASSEMBLY__ | |
22 | #ifndef PHYS_OFFSET | |
3563b477 | 23 | #define PHYS_OFFSET _UL(0) |
f2ac457a HC |
24 | #endif |
25 | extern unsigned long vm_map_base; | |
26 | #endif /* __ASSEMBLY__ */ | |
27 | ||
28 | #ifndef IO_BASE | |
29 | #define IO_BASE CSR_DMW0_BASE | |
30 | #endif | |
31 | ||
32 | #ifndef CACHE_BASE | |
33 | #define CACHE_BASE CSR_DMW1_BASE | |
34 | #endif | |
35 | ||
36 | #ifndef UNCACHE_BASE | |
37 | #define UNCACHE_BASE CSR_DMW0_BASE | |
38 | #endif | |
39 | ||
40 | #define DMW_PABITS 48 | |
41 | #define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1) | |
42 | ||
43 | /* | |
44 | * Memory above this physical address will be considered highmem. | |
45 | */ | |
46 | #ifndef HIGHMEM_START | |
3563b477 | 47 | #define HIGHMEM_START (_UL(1) << _UL(DMW_PABITS)) |
f2ac457a HC |
48 | #endif |
49 | ||
50 | #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) | |
51 | #define TO_CACHE(x) (CACHE_BASE | ((x) & TO_PHYS_MASK)) | |
52 | #define TO_UNCACHE(x) (UNCACHE_BASE | ((x) & TO_PHYS_MASK)) | |
53 | ||
54 | /* | |
55 | * This handles the memory map. | |
56 | */ | |
57 | #ifndef PAGE_OFFSET | |
58 | #define PAGE_OFFSET (CACHE_BASE + PHYS_OFFSET) | |
59 | #endif | |
60 | ||
61 | #ifndef FIXADDR_TOP | |
62 | #define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) | |
63 | #endif | |
64 | ||
65 | #ifdef __ASSEMBLY__ | |
66 | #define _ATYPE_ | |
67 | #define _ATYPE32_ | |
68 | #define _ATYPE64_ | |
f2ac457a HC |
69 | #else |
70 | #define _ATYPE_ __PTRDIFF_TYPE__ | |
71 | #define _ATYPE32_ int | |
72 | #define _ATYPE64_ __s64 | |
3563b477 AS |
73 | #endif |
74 | ||
f2ac457a | 75 | #ifdef CONFIG_64BIT |
3563b477 | 76 | #define _CONST64_(x) _UL(x) |
f2ac457a | 77 | #else |
3563b477 | 78 | #define _CONST64_(x) _ULL(x) |
f2ac457a HC |
79 | #endif |
80 | ||
81 | /* | |
82 | * 32/64-bit LoongArch address spaces | |
83 | */ | |
84 | #ifdef __ASSEMBLY__ | |
85 | #define _ACAST32_ | |
86 | #define _ACAST64_ | |
87 | #else | |
88 | #define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ | |
89 | #define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ | |
90 | #endif | |
91 | ||
92 | #ifdef CONFIG_32BIT | |
93 | ||
94 | #define UVRANGE 0x00000000 | |
95 | #define KPRANGE0 0x80000000 | |
96 | #define KPRANGE1 0xa0000000 | |
97 | #define KVRANGE 0xc0000000 | |
98 | ||
99 | #else | |
100 | ||
101 | #define XUVRANGE _CONST64_(0x0000000000000000) | |
102 | #define XSPRANGE _CONST64_(0x4000000000000000) | |
103 | #define XKPRANGE _CONST64_(0x8000000000000000) | |
104 | #define XKVRANGE _CONST64_(0xc000000000000000) | |
105 | ||
106 | #endif | |
107 | ||
108 | /* | |
109 | * Returns the physical address of a KPRANGEx / XKPRANGE address | |
110 | */ | |
111 | #define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK) | |
112 | ||
092e9ebe HC |
113 | /* |
114 | * On LoongArch, I/O ports mappring is following: | |
115 | * | |
116 | * | .... | | |
117 | * |-----------------------| | |
118 | * | pci io ports(16K~32M) | | |
119 | * |-----------------------| | |
120 | * | isa io ports(0 ~16K) | | |
121 | * PCI_IOBASE ->|-----------------------| | |
122 | * | .... | | |
123 | */ | |
124 | #define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE))) | |
125 | #define PCI_IOSIZE SZ_32M | |
126 | #define ISA_IOSIZE SZ_16K | |
127 | #define IO_SPACE_LIMIT (PCI_IOSIZE - 1) | |
128 | ||
3f89765d YT |
129 | #define PHYS_LINK_KADDR PHYSADDR(VMLINUX_LOAD_ADDRESS) |
130 | ||
f2ac457a | 131 | #endif /* _ASM_ADDRSPACE_H */ |