Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Platform dependent support for SGI SN | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
ff740fb0 | 8 | * Copyright (c) 2000-2008 Silicon Graphics, Inc. All Rights Reserved. |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/irq.h> | |
cb4cb2cb | 12 | #include <linux/spinlock.h> |
2fcc3db0 | 13 | #include <linux/init.h> |
82524746 | 14 | #include <linux/rculist.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1da177e4 LT |
16 | #include <asm/sn/addrs.h> |
17 | #include <asm/sn/arch.h> | |
c13cf371 PB |
18 | #include <asm/sn/intr.h> |
19 | #include <asm/sn/pcibr_provider.h> | |
9b08ebd1 MM |
20 | #include <asm/sn/pcibus_provider_defs.h> |
21 | #include <asm/sn/pcidev.h> | |
1da177e4 LT |
22 | #include <asm/sn/shub_mmr.h> |
23 | #include <asm/sn/sn_sal.h> | |
6e9de181 | 24 | #include <asm/sn/sn_feature_sets.h> |
1da177e4 LT |
25 | |
26 | static void force_interrupt(int irq); | |
27 | static void register_intr_pda(struct sn_irq_info *sn_irq_info); | |
28 | static void unregister_intr_pda(struct sn_irq_info *sn_irq_info); | |
29 | ||
d0d59b98 | 30 | int sn_force_interrupt_flag = 1; |
1da177e4 | 31 | extern int sn_ioif_inited; |
83821d3f | 32 | struct list_head **sn_irq_lh; |
34af946a | 33 | static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */ |
1da177e4 | 34 | |
83821d3f MM |
35 | u64 sn_intr_alloc(nasid_t local_nasid, int local_widget, |
36 | struct sn_irq_info *sn_irq_info, | |
1da177e4 LT |
37 | int req_irq, nasid_t req_nasid, |
38 | int req_slice) | |
39 | { | |
40 | struct ia64_sal_retval ret_stuff; | |
41 | ret_stuff.status = 0; | |
42 | ret_stuff.v0 = 0; | |
43 | ||
44 | SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT, | |
45 | (u64) SAL_INTR_ALLOC, (u64) local_nasid, | |
83821d3f | 46 | (u64) local_widget, __pa(sn_irq_info), (u64) req_irq, |
1da177e4 | 47 | (u64) req_nasid, (u64) req_slice); |
83821d3f | 48 | |
1da177e4 LT |
49 | return ret_stuff.status; |
50 | } | |
51 | ||
83821d3f | 52 | void sn_intr_free(nasid_t local_nasid, int local_widget, |
1da177e4 LT |
53 | struct sn_irq_info *sn_irq_info) |
54 | { | |
55 | struct ia64_sal_retval ret_stuff; | |
56 | ret_stuff.status = 0; | |
57 | ret_stuff.v0 = 0; | |
58 | ||
59 | SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT, | |
60 | (u64) SAL_INTR_FREE, (u64) local_nasid, | |
61 | (u64) local_widget, (u64) sn_irq_info->irq_irq, | |
62 | (u64) sn_irq_info->irq_cookie, 0, 0); | |
63 | } | |
64 | ||
0e17b560 JK |
65 | u64 sn_intr_redirect(nasid_t local_nasid, int local_widget, |
66 | struct sn_irq_info *sn_irq_info, | |
67 | nasid_t req_nasid, int req_slice) | |
68 | { | |
69 | struct ia64_sal_retval ret_stuff; | |
70 | ret_stuff.status = 0; | |
71 | ret_stuff.v0 = 0; | |
72 | ||
73 | SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT, | |
74 | (u64) SAL_INTR_REDIRECT, (u64) local_nasid, | |
75 | (u64) local_widget, __pa(sn_irq_info), | |
76 | (u64) req_nasid, (u64) req_slice, 0); | |
77 | ||
78 | return ret_stuff.status; | |
79 | } | |
80 | ||
1da177e4 LT |
81 | static unsigned int sn_startup_irq(unsigned int irq) |
82 | { | |
83 | return 0; | |
84 | } | |
85 | ||
86 | static void sn_shutdown_irq(unsigned int irq) | |
87 | { | |
88 | } | |
89 | ||
1f3b6045 RA |
90 | extern void ia64_mca_register_cpev(int); |
91 | ||
1da177e4 LT |
92 | static void sn_disable_irq(unsigned int irq) |
93 | { | |
1f3b6045 RA |
94 | if (irq == local_vector_to_irq(IA64_CPE_VECTOR)) |
95 | ia64_mca_register_cpev(0); | |
1da177e4 LT |
96 | } |
97 | ||
98 | static void sn_enable_irq(unsigned int irq) | |
99 | { | |
1f3b6045 RA |
100 | if (irq == local_vector_to_irq(IA64_CPE_VECTOR)) |
101 | ia64_mca_register_cpev(irq); | |
1da177e4 LT |
102 | } |
103 | ||
104 | static void sn_ack_irq(unsigned int irq) | |
105 | { | |
2fcc3db0 | 106 | u64 event_occurred, mask; |
1da177e4 LT |
107 | |
108 | irq = irq & 0xff; | |
2fcc3db0 | 109 | event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED)); |
be539c73 | 110 | mask = event_occurred & SH_ALL_INT_MASK; |
2fcc3db0 | 111 | HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask); |
1da177e4 LT |
112 | __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs); |
113 | ||
689388bb | 114 | move_native_irq(irq); |
1da177e4 LT |
115 | } |
116 | ||
117 | static void sn_end_irq(unsigned int irq) | |
118 | { | |
1da177e4 | 119 | int ivec; |
0aa2c72e | 120 | u64 event_occurred; |
1da177e4 LT |
121 | |
122 | ivec = irq & 0xff; | |
123 | if (ivec == SGI_UART_VECTOR) { | |
0aa2c72e | 124 | event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED)); |
cb4cb2cb | 125 | /* If the UART bit is set here, we may have received an |
1da177e4 LT |
126 | * interrupt from the UART that the driver missed. To |
127 | * make sure, we IPI ourselves to force us to look again. | |
128 | */ | |
129 | if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) { | |
130 | platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR, | |
131 | IA64_IPI_DM_INT, 0); | |
132 | } | |
133 | } | |
134 | __clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs); | |
135 | if (sn_force_interrupt_flag) | |
136 | force_interrupt(irq); | |
137 | } | |
138 | ||
cb4cb2cb PB |
139 | static void sn_irq_info_free(struct rcu_head *head); |
140 | ||
83821d3f MM |
141 | struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info, |
142 | nasid_t nasid, int slice) | |
1da177e4 | 143 | { |
83821d3f | 144 | int vector; |
c6957771 JK |
145 | int cpuid; |
146 | #ifdef CONFIG_SMP | |
83821d3f | 147 | int cpuphys; |
c6957771 | 148 | #endif |
83821d3f MM |
149 | int64_t bridge; |
150 | int local_widget, status; | |
151 | nasid_t local_nasid; | |
152 | struct sn_irq_info *new_irq_info; | |
153 | struct sn_pcibus_provider *pci_provider; | |
154 | ||
0e17b560 | 155 | bridge = (u64) sn_irq_info->irq_bridge; |
83821d3f | 156 | if (!bridge) { |
83821d3f MM |
157 | return NULL; /* irq is not a device interrupt */ |
158 | } | |
1da177e4 | 159 | |
83821d3f | 160 | local_nasid = NASID_GET(bridge); |
1da177e4 | 161 | |
83821d3f MM |
162 | if (local_nasid & 1) |
163 | local_widget = TIO_SWIN_WIDGETNUM(bridge); | |
164 | else | |
165 | local_widget = SWIN_WIDGETNUM(bridge); | |
83821d3f | 166 | vector = sn_irq_info->irq_irq; |
0e17b560 JK |
167 | |
168 | /* Make use of SAL_INTR_REDIRECT if PROM supports it */ | |
169 | status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice); | |
170 | if (!status) { | |
171 | new_irq_info = sn_irq_info; | |
172 | goto finish_up; | |
173 | } | |
174 | ||
175 | /* | |
176 | * PROM does not support SAL_INTR_REDIRECT, or it failed. | |
177 | * Revert to old method. | |
178 | */ | |
179 | new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC); | |
180 | if (new_irq_info == NULL) | |
181 | return NULL; | |
182 | ||
183 | memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info)); | |
184 | ||
83821d3f MM |
185 | /* Free the old PROM new_irq_info structure */ |
186 | sn_intr_free(local_nasid, local_widget, new_irq_info); | |
83821d3f | 187 | unregister_intr_pda(new_irq_info); |
1da177e4 | 188 | |
83821d3f MM |
189 | /* allocate a new PROM new_irq_info struct */ |
190 | status = sn_intr_alloc(local_nasid, local_widget, | |
191 | new_irq_info, vector, | |
192 | nasid, slice); | |
1da177e4 | 193 | |
83821d3f MM |
194 | /* SAL call failed */ |
195 | if (status) { | |
196 | kfree(new_irq_info); | |
197 | return NULL; | |
198 | } | |
cb4cb2cb | 199 | |
0e17b560 JK |
200 | register_intr_pda(new_irq_info); |
201 | spin_lock(&sn_irq_info_lock); | |
202 | list_replace_rcu(&sn_irq_info->list, &new_irq_info->list); | |
203 | spin_unlock(&sn_irq_info_lock); | |
204 | call_rcu(&sn_irq_info->rcu, sn_irq_info_free); | |
205 | ||
206 | ||
207 | finish_up: | |
c6957771 JK |
208 | /* Update kernels new_irq_info with new target info */ |
209 | cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid, | |
210 | new_irq_info->irq_slice); | |
211 | new_irq_info->irq_cpuid = cpuid; | |
1da177e4 | 212 | |
83821d3f | 213 | pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type]; |
cb4cb2cb | 214 | |
83821d3f MM |
215 | /* |
216 | * If this represents a line interrupt, target it. If it's | |
217 | * an msi (irq_int_bit < 0), it's already targeted. | |
218 | */ | |
219 | if (new_irq_info->irq_int_bit >= 0 && | |
220 | pci_provider && pci_provider->target_interrupt) | |
221 | (pci_provider->target_interrupt)(new_irq_info); | |
cb4cb2cb | 222 | |
1da177e4 | 223 | #ifdef CONFIG_SMP |
c6957771 | 224 | cpuphys = cpu_physical_id(cpuid); |
83821d3f | 225 | set_irq_affinity_info((vector & 0xff), cpuphys, 0); |
1da177e4 | 226 | #endif |
83821d3f MM |
227 | |
228 | return new_irq_info; | |
229 | } | |
230 | ||
d5dedd45 | 231 | static int sn_set_affinity_irq(unsigned int irq, const struct cpumask *mask) |
83821d3f MM |
232 | { |
233 | struct sn_irq_info *sn_irq_info, *sn_irq_info_safe; | |
234 | nasid_t nasid; | |
235 | int slice; | |
236 | ||
0de26520 RR |
237 | nasid = cpuid_to_nasid(cpumask_first(mask)); |
238 | slice = cpuid_to_slice(cpumask_first(mask)); | |
83821d3f MM |
239 | |
240 | list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe, | |
241 | sn_irq_lh[irq], list) | |
242 | (void)sn_retarget_vector(sn_irq_info, nasid, slice); | |
d5dedd45 YL |
243 | |
244 | return 0; | |
1da177e4 LT |
245 | } |
246 | ||
6e9de181 JK |
247 | #ifdef CONFIG_SMP |
248 | void sn_set_err_irq_affinity(unsigned int irq) | |
249 | { | |
250 | /* | |
251 | * On systems which support CPU disabling (SHub2), all error interrupts | |
252 | * are targetted at the boot CPU. | |
253 | */ | |
254 | if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT)) | |
255 | set_irq_affinity_info(irq, cpu_physical_id(0), 0); | |
256 | } | |
257 | #else | |
258 | void sn_set_err_irq_affinity(unsigned int irq) { } | |
259 | #endif | |
260 | ||
e253eb0c KH |
261 | static void |
262 | sn_mask_irq(unsigned int irq) | |
263 | { | |
264 | } | |
265 | ||
266 | static void | |
267 | sn_unmask_irq(unsigned int irq) | |
268 | { | |
269 | } | |
270 | ||
271 | struct irq_chip irq_type_sn = { | |
06344db3 | 272 | .name = "SN hub", |
cb4cb2cb PB |
273 | .startup = sn_startup_irq, |
274 | .shutdown = sn_shutdown_irq, | |
275 | .enable = sn_enable_irq, | |
276 | .disable = sn_disable_irq, | |
277 | .ack = sn_ack_irq, | |
278 | .end = sn_end_irq, | |
e253eb0c KH |
279 | .mask = sn_mask_irq, |
280 | .unmask = sn_unmask_irq, | |
cb4cb2cb | 281 | .set_affinity = sn_set_affinity_irq |
1da177e4 LT |
282 | }; |
283 | ||
1115200a KK |
284 | ia64_vector sn_irq_to_vector(int irq) |
285 | { | |
286 | if (irq >= IA64_NUM_VECTORS) | |
287 | return 0; | |
288 | return (ia64_vector)irq; | |
289 | } | |
290 | ||
1da177e4 LT |
291 | unsigned int sn_local_vector_to_irq(u8 vector) |
292 | { | |
293 | return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector)); | |
294 | } | |
295 | ||
296 | void sn_irq_init(void) | |
297 | { | |
298 | int i; | |
86bc3dfe | 299 | struct irq_desc *base_desc = irq_desc; |
1da177e4 | 300 | |
10083072 MM |
301 | ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR; |
302 | ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR; | |
303 | ||
1da177e4 | 304 | for (i = 0; i < NR_IRQS; i++) { |
8a7c3cd3 | 305 | if (base_desc[i].chip == &no_irq_chip) { |
d1bef4ed | 306 | base_desc[i].chip = &irq_type_sn; |
1da177e4 LT |
307 | } |
308 | } | |
309 | } | |
310 | ||
311 | static void register_intr_pda(struct sn_irq_info *sn_irq_info) | |
312 | { | |
313 | int irq = sn_irq_info->irq_irq; | |
314 | int cpu = sn_irq_info->irq_cpuid; | |
315 | ||
316 | if (pdacpu(cpu)->sn_last_irq < irq) { | |
317 | pdacpu(cpu)->sn_last_irq = irq; | |
318 | } | |
319 | ||
2fcc3db0 | 320 | if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq) |
1da177e4 | 321 | pdacpu(cpu)->sn_first_irq = irq; |
1da177e4 LT |
322 | } |
323 | ||
324 | static void unregister_intr_pda(struct sn_irq_info *sn_irq_info) | |
325 | { | |
326 | int irq = sn_irq_info->irq_irq; | |
327 | int cpu = sn_irq_info->irq_cpuid; | |
328 | struct sn_irq_info *tmp_irq_info; | |
329 | int i, foundmatch; | |
330 | ||
cb4cb2cb | 331 | rcu_read_lock(); |
1da177e4 LT |
332 | if (pdacpu(cpu)->sn_last_irq == irq) { |
333 | foundmatch = 0; | |
cb4cb2cb PB |
334 | for (i = pdacpu(cpu)->sn_last_irq - 1; |
335 | i && !foundmatch; i--) { | |
336 | list_for_each_entry_rcu(tmp_irq_info, | |
337 | sn_irq_lh[i], | |
338 | list) { | |
1da177e4 | 339 | if (tmp_irq_info->irq_cpuid == cpu) { |
cb4cb2cb | 340 | foundmatch = 1; |
1da177e4 LT |
341 | break; |
342 | } | |
1da177e4 LT |
343 | } |
344 | } | |
345 | pdacpu(cpu)->sn_last_irq = i; | |
346 | } | |
347 | ||
348 | if (pdacpu(cpu)->sn_first_irq == irq) { | |
349 | foundmatch = 0; | |
cb4cb2cb PB |
350 | for (i = pdacpu(cpu)->sn_first_irq + 1; |
351 | i < NR_IRQS && !foundmatch; i++) { | |
352 | list_for_each_entry_rcu(tmp_irq_info, | |
353 | sn_irq_lh[i], | |
354 | list) { | |
1da177e4 | 355 | if (tmp_irq_info->irq_cpuid == cpu) { |
cb4cb2cb | 356 | foundmatch = 1; |
1da177e4 LT |
357 | break; |
358 | } | |
1da177e4 LT |
359 | } |
360 | } | |
361 | pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i); | |
362 | } | |
cb4cb2cb | 363 | rcu_read_unlock(); |
1da177e4 LT |
364 | } |
365 | ||
cb4cb2cb | 366 | static void sn_irq_info_free(struct rcu_head *head) |
1da177e4 LT |
367 | { |
368 | struct sn_irq_info *sn_irq_info; | |
1da177e4 | 369 | |
cb4cb2cb | 370 | sn_irq_info = container_of(head, struct sn_irq_info, rcu); |
1da177e4 LT |
371 | kfree(sn_irq_info); |
372 | } | |
373 | ||
374 | void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info) | |
375 | { | |
376 | nasid_t nasid = sn_irq_info->irq_nasid; | |
377 | int slice = sn_irq_info->irq_slice; | |
378 | int cpu = nasid_slice_to_cpuid(nasid, slice); | |
c6957771 JK |
379 | #ifdef CONFIG_SMP |
380 | int cpuphys; | |
86bc3dfe | 381 | struct irq_desc *desc; |
c6957771 | 382 | #endif |
1da177e4 | 383 | |
cb4cb2cb | 384 | pci_dev_get(pci_dev); |
1da177e4 LT |
385 | sn_irq_info->irq_cpuid = cpu; |
386 | sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev); | |
387 | ||
388 | /* link it into the sn_irq[irq] list */ | |
cb4cb2cb PB |
389 | spin_lock(&sn_irq_info_lock); |
390 | list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]); | |
10083072 | 391 | reserve_irq_vector(sn_irq_info->irq_irq); |
cb4cb2cb | 392 | spin_unlock(&sn_irq_info_lock); |
1da177e4 | 393 | |
2fcc3db0 | 394 | register_intr_pda(sn_irq_info); |
c6957771 JK |
395 | #ifdef CONFIG_SMP |
396 | cpuphys = cpu_physical_id(cpu); | |
397 | set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0); | |
ff740fb0 JK |
398 | desc = irq_to_desc(sn_irq_info->irq_irq); |
399 | /* | |
400 | * Affinity was set by the PROM, prevent it from | |
401 | * being reset by the request_irq() path. | |
402 | */ | |
403 | desc->status |= IRQ_AFFINITY_SET; | |
c6957771 | 404 | #endif |
1da177e4 LT |
405 | } |
406 | ||
cb4cb2cb PB |
407 | void sn_irq_unfixup(struct pci_dev *pci_dev) |
408 | { | |
409 | struct sn_irq_info *sn_irq_info; | |
410 | ||
411 | /* Only cleanup IRQ stuff if this device has a host bus context */ | |
412 | if (!SN_PCIDEV_BUSSOFT(pci_dev)) | |
413 | return; | |
414 | ||
415 | sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info; | |
8b34ff42 PB |
416 | if (!sn_irq_info) |
417 | return; | |
418 | if (!sn_irq_info->irq_irq) { | |
6f354b01 | 419 | kfree(sn_irq_info); |
cb4cb2cb | 420 | return; |
6f354b01 | 421 | } |
cb4cb2cb PB |
422 | |
423 | unregister_intr_pda(sn_irq_info); | |
424 | spin_lock(&sn_irq_info_lock); | |
425 | list_del_rcu(&sn_irq_info->list); | |
426 | spin_unlock(&sn_irq_info_lock); | |
10083072 MM |
427 | if (list_empty(sn_irq_lh[sn_irq_info->irq_irq])) |
428 | free_irq_vector(sn_irq_info->irq_irq); | |
cb4cb2cb | 429 | call_rcu(&sn_irq_info->rcu, sn_irq_info_free); |
cb4cb2cb | 430 | pci_dev_put(pci_dev); |
10083072 | 431 | |
cb4cb2cb PB |
432 | } |
433 | ||
735e60f4 MM |
434 | static inline void |
435 | sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info) | |
436 | { | |
437 | struct sn_pcibus_provider *pci_provider; | |
438 | ||
439 | pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type]; | |
352b0ef5 MH |
440 | |
441 | /* Don't force an interrupt if the irq has been disabled */ | |
442 | if (!(irq_desc[sn_irq_info->irq_irq].status & IRQ_DISABLED) && | |
443 | pci_provider && pci_provider->force_interrupt) | |
735e60f4 MM |
444 | (*pci_provider->force_interrupt)(sn_irq_info); |
445 | } | |
446 | ||
1da177e4 LT |
447 | static void force_interrupt(int irq) |
448 | { | |
449 | struct sn_irq_info *sn_irq_info; | |
450 | ||
451 | if (!sn_ioif_inited) | |
452 | return; | |
cb4cb2cb PB |
453 | |
454 | rcu_read_lock(); | |
735e60f4 MM |
455 | list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list) |
456 | sn_call_force_intr_provider(sn_irq_info); | |
457 | ||
cb4cb2cb | 458 | rcu_read_unlock(); |
1da177e4 LT |
459 | } |
460 | ||
461 | /* | |
462 | * Check for lost interrupts. If the PIC int_status reg. says that | |
463 | * an interrupt has been sent, but not handled, and the interrupt | |
464 | * is not pending in either the cpu irr regs or in the soft irr regs, | |
465 | * and the interrupt is not in service, then the interrupt may have | |
466 | * been lost. Force an interrupt on that pin. It is possible that | |
467 | * the interrupt is in flight, so we may generate a spurious interrupt, | |
468 | * but we should never miss a real lost interrupt. | |
469 | */ | |
470 | static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info) | |
471 | { | |
53493dcf | 472 | u64 regval; |
1da177e4 LT |
473 | struct pcidev_info *pcidev_info; |
474 | struct pcibus_info *pcibus_info; | |
475 | ||
735e60f4 MM |
476 | /* |
477 | * Bridge types attached to TIO (anything but PIC) do not need this WAR | |
478 | * since they do not target Shub II interrupt registers. If that | |
479 | * ever changes, this check needs to accomodate. | |
480 | */ | |
481 | if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC) | |
482 | return; | |
483 | ||
1da177e4 LT |
484 | pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; |
485 | if (!pcidev_info) | |
486 | return; | |
487 | ||
488 | pcibus_info = | |
489 | (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info-> | |
490 | pdi_pcibus_info; | |
491 | regval = pcireg_intr_status_get(pcibus_info); | |
492 | ||
9a4e5549 | 493 | if (!ia64_get_irr(irq_to_vector(irq))) { |
735e60f4 MM |
494 | if (!test_bit(irq, pda->sn_in_service_ivecs)) { |
495 | regval &= 0xff; | |
496 | if (sn_irq_info->irq_int_bit & regval & | |
497 | sn_irq_info->irq_last_intr) { | |
498 | regval &= ~(sn_irq_info->irq_int_bit & regval); | |
499 | sn_call_force_intr_provider(sn_irq_info); | |
1da177e4 LT |
500 | } |
501 | } | |
502 | } | |
503 | sn_irq_info->irq_last_intr = regval; | |
504 | } | |
505 | ||
506 | void sn_lb_int_war_check(void) | |
507 | { | |
cb4cb2cb | 508 | struct sn_irq_info *sn_irq_info; |
1da177e4 LT |
509 | int i; |
510 | ||
511 | if (!sn_ioif_inited || pda->sn_first_irq == 0) | |
512 | return; | |
cb4cb2cb PB |
513 | |
514 | rcu_read_lock(); | |
1da177e4 | 515 | for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) { |
cb4cb2cb | 516 | list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) { |
735e60f4 | 517 | sn_check_intr(i, sn_irq_info); |
1da177e4 LT |
518 | } |
519 | } | |
cb4cb2cb PB |
520 | rcu_read_unlock(); |
521 | } | |
522 | ||
2fcc3db0 | 523 | void __init sn_irq_lh_init(void) |
cb4cb2cb PB |
524 | { |
525 | int i; | |
526 | ||
527 | sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL); | |
528 | if (!sn_irq_lh) | |
529 | panic("SN PCI INIT: Failed to allocate memory for PCI init\n"); | |
530 | ||
531 | for (i = 0; i < NR_IRQS; i++) { | |
532 | sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL); | |
533 | if (!sn_irq_lh[i]) | |
534 | panic("SN PCI INIT: Failed IRQ memory allocation\n"); | |
535 | ||
536 | INIT_LIST_HEAD(sn_irq_lh[i]); | |
537 | } | |
1da177e4 | 538 | } |