[linux-2.6-block.git] / arch / ia64 / sn / kernel / bte.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 2000-2006 Silicon Graphics, Inc.  All Rights Reserved.
 */

#include <linux/module.h>
#include <asm/sn/nodepda.h>
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#include <asm/sn/sn_cpuid.h>
#include <asm/sn/pda.h>
#include <asm/sn/shubio.h>
#include <asm/nodedata.h>
#include <asm/delay.h>

#include <linux/bootmem.h>
#include <linux/string.h>
#include <linux/sched.h>

#include <asm/sn/bte.h>

#ifndef L1_CACHE_MASK
#define L1_CACHE_MASK (L1_CACHE_BYTES - 1)
#endif

/* two interfaces on two btes */
#define MAX_INTERFACES_TO_TRY		4
#define MAX_NODES_TO_TRY		2

static struct bteinfo_s *bte_if_on_node(nasid_t nasid, int interface)
{
	nodepda_t *tmp_nodepda;

	if (nasid_to_cnodeid(nasid) == -1)
		return (struct bteinfo_s *)NULL;

	tmp_nodepda = NODEPDA(nasid_to_cnodeid(nasid));
	return &tmp_nodepda->bte_if[interface];

}

static inline void bte_start_transfer(struct bteinfo_s *bte, u64 len, u64 mode)
{
	if (is_shub2()) {
		BTE_CTRL_STORE(bte, (IBLS_BUSY | ((len) | (mode) << 24)));
	} else {
		BTE_LNSTAT_STORE(bte, len);
		BTE_CTRL_STORE(bte, mode);
	}
}

/************************************************************************
 * Block Transfer Engine copy related functions.
 *
 ***********************************************************************/

/*
 * bte_copy(src, dest, len, mode, notification)
 *
 * Use the block transfer engine to move kernel memory from src to dest
 * using the assigned mode.
 *
 * Parameters:
 *   src - physical address of the transfer source.
 *   dest - physical address of the transfer destination.
 *   len - number of bytes to transfer from source to dest.
 *   mode - hardware defined.  See reference information
 *          for IBCT0/1 in the SHUB Programmers Reference
 *   notification - kernel virtual address of the notification cache
 *                  line.  If NULL, the default is used and
 *                  the bte_copy is synchronous.
 *
 * NOTE:  This function requires src, dest, and len to
 * be cacheline aligned.
 */
bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
{
	u64 transfer_size;
	u64 transfer_stat;
	u64 notif_phys_addr;
	struct bteinfo_s *bte;
	bte_result_t bte_status;
	unsigned long irq_flags;
	unsigned long itc_end = 0;
	int nasid_to_try[MAX_NODES_TO_TRY];
	int my_nasid = cpuid_to_nasid(raw_smp_processor_id());
	int bte_if_index, nasid_index;
	int bte_first, btes_per_node = BTES_PER_NODE;

	BTE_PRINTK(("bte_copy(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%p)\n",
		    src, dest, len, mode, notification));

	if (len == 0) {
		return BTE_SUCCESS;
	}

	BUG_ON((len & L1_CACHE_MASK) ||
		 (src & L1_CACHE_MASK) || (dest & L1_CACHE_MASK));
	BUG_ON(!(len < ((BTE_LEN_MASK + 1) << L1_CACHE_SHIFT)));

	/*
	 * Start with interface corresponding to cpu number
	 */
	bte_first = raw_smp_processor_id() % btes_per_node;

	if (mode & BTE_USE_DEST) {
		/* try remote then local */
		nasid_to_try[0] = NASID_GET(dest);
		if (mode & BTE_USE_ANY) {
			nasid_to_try[1] = my_nasid;
		} else {
			nasid_to_try[1] = (int)NULL;
		}
	} else {
		/* try local then remote */
		nasid_to_try[0] = my_nasid;
		if (mode & BTE_USE_ANY) {
			nasid_to_try[1] = NASID_GET(dest);
		} else {
			nasid_to_try[1] = (int)NULL;
		}
	}

retry_bteop:
	do {
		local_irq_save(irq_flags);

		bte_if_index = bte_first;
		nasid_index = 0;

		/* Attempt to lock one of the BTE interfaces. */
		while (nasid_index < MAX_NODES_TO_TRY) {
			bte = bte_if_on_node(nasid_to_try[nasid_index],bte_if_index);

			if (bte == NULL) {
				nasid_index++;
				continue;
			}

			if (spin_trylock(&bte->spinlock)) {
				if (!(*bte->most_rcnt_na & BTE_WORD_AVAILABLE) ||
				    (BTE_LNSTAT_LOAD(bte) & BTE_ACTIVE)) {
					/* Got the lock but BTE still busy */
					spin_unlock(&bte->spinlock);
				} else {
					/* we got the lock and it's not busy */
					break;
				}
			}

			bte_if_index = (bte_if_index + 1) % btes_per_node; /* Next interface */
			if (bte_if_index == bte_first) {
				/*
				 * We've tried all interfaces on this node
				 */
				nasid_index++;
			}

			bte = NULL;
		}

		if (bte != NULL) {
			break;
		}

		local_irq_restore(irq_flags);

		if (!(mode & BTE_WACQUIRE)) {
			return BTEFAIL_NOTAVAIL;
		}
	} while (1);

	if (notification == NULL) {
		/* User does not want to be notified. */
		bte->most_rcnt_na = &bte->notify;
	} else {
		bte->most_rcnt_na = notification;
	}

	/* Calculate the number of cache lines to transfer. */
	transfer_size = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK);

	/* Initialize the notification to a known value. */
	*bte->most_rcnt_na = BTE_WORD_BUSY;
	notif_phys_addr = (u64)bte->most_rcnt_na;

	/* Set the source and destination registers */
	BTE_PRINTKV(("IBSA = 0x%lx)\n", src));
	BTE_SRC_STORE(bte, src);
	BTE_PRINTKV(("IBDA = 0x%lx)\n", dest));
	BTE_DEST_STORE(bte, dest);

	/* Set the notification register */
	BTE_PRINTKV(("IBNA = 0x%lx)\n", notif_phys_addr));
	BTE_NOTIF_STORE(bte, notif_phys_addr);

	/* Initiate the transfer */
	BTE_PRINTK(("IBCT = 0x%lx)\n", BTE_VALID_MODE(mode)));
	bte_start_transfer(bte, transfer_size, BTE_VALID_MODE(mode));

	itc_end = ia64_get_itc() + (40000000 * local_cpu_data->cyc_per_usec);

	spin_unlock_irqrestore(&bte->spinlock, irq_flags);

	if (notification != NULL) {
		return BTE_SUCCESS;
	}

	while ((transfer_stat = *bte->most_rcnt_na) == BTE_WORD_BUSY) {
		cpu_relax();
		if (ia64_get_itc() > itc_end) {
			BTE_PRINTK(("BTE timeout nasid 0x%x bte%d IBLS = 0x%lx na 0x%lx\n",
				NASID_GET(bte->bte_base_addr), bte->bte_num,
				BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na) );
			bte->bte_error_count++;
			bte->bh_error = IBLS_ERROR;
			bte_error_handler((unsigned long)NODEPDA(bte->bte_cnode));
			*bte->most_rcnt_na = BTE_WORD_AVAILABLE;
			goto retry_bteop;
		}
	}

	BTE_PRINTKV((" Delay Done.  IBLS = 0x%lx, most_rcnt_na = 0x%lx\n",
		     BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));

	if (transfer_stat & IBLS_ERROR) {
		bte_status = transfer_stat & ~IBLS_ERROR;
	} else {
		bte_status = BTE_SUCCESS;
	}
	*bte->most_rcnt_na = BTE_WORD_AVAILABLE;

	BTE_PRINTK(("Returning status is 0x%lx and most_rcnt_na is 0x%lx\n",
		    BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));

	return bte_status;
}

EXPORT_SYMBOL(bte_copy);

/*
 * bte_unaligned_copy(src, dest, len, mode)
 *
 * use the block transfer engine to move kernel
 * memory from src to dest using the assigned mode.
 *
 * Parameters:
 *   src - physical address of the transfer source.
 *   dest - physical address of the transfer destination.
 *   len - number of bytes to transfer from source to dest.
 *   mode - hardware defined.  See reference information
 *          for IBCT0/1 in the SGI documentation.
 *
 * NOTE: If the source, dest, and len are all cache line aligned,
 * then it would be _FAR_ preferable to use bte_copy instead.
 */
bte_result_t bte_unaligned_copy(u64 src, u64 dest, u64 len, u64 mode)
{
	int destFirstCacheOffset;
	u64 headBteSource;
	u64 headBteLen;
	u64 headBcopySrcOffset;
	u64 headBcopyDest;
	u64 headBcopyLen;
	u64 footBteSource;
	u64 footBteLen;
	u64 footBcopyDest;
	u64 footBcopyLen;
	bte_result_t rv;
	char *bteBlock, *bteBlock_unaligned;

	if (len == 0) {
		return BTE_SUCCESS;
	}

	/* temporary buffer used during unaligned transfers */
	bteBlock_unaligned = kmalloc(len + 3 * L1_CACHE_BYTES, GFP_KERNEL);
	if (bteBlock_unaligned == NULL) {
		return BTEFAIL_NOTAVAIL;
	}
	bteBlock = (char *)L1_CACHE_ALIGN((u64) bteBlock_unaligned);

	headBcopySrcOffset = src & L1_CACHE_MASK;
	destFirstCacheOffset = dest & L1_CACHE_MASK;

	/*
	 * At this point, the transfer is broken into
	 * (up to) three sections.  The first section is
	 * from the start address to the first physical
	 * cache line, the second is from the first physical
	 * cache line to the last complete cache line,
	 * and the third is from the last cache line to the
	 * end of the buffer.  The first and third sections
	 * are handled by bte copying into a temporary buffer
	 * and then bcopy'ing the necessary section into the
	 * final location.  The middle section is handled with
	 * a standard bte copy.
	 *
	 * One nasty exception to the above rule is when the
	 * source and destination are not symmetrically
	 * mis-aligned.  If the source offset from the first
	 * cache line is different from the destination offset,
	 * we make the first section be the entire transfer
	 * and the bcopy the entire block into place.
	 */
	if (headBcopySrcOffset == destFirstCacheOffset) {

		/*
		 * Both the source and destination are the same
		 * distance from a cache line boundary so we can
		 * use the bte to transfer the bulk of the
		 * data.
		 */
		headBteSource = src & ~L1_CACHE_MASK;
		headBcopyDest = dest;
		if (headBcopySrcOffset) {
			headBcopyLen =
			    (len >
			     (L1_CACHE_BYTES -
			      headBcopySrcOffset) ? L1_CACHE_BYTES
			     - headBcopySrcOffset : len);
			headBteLen = L1_CACHE_BYTES;
		} else {
			headBcopyLen = 0;
			headBteLen = 0;
		}

		if (len > headBcopyLen) {
			footBcopyLen = (len - headBcopyLen) & L1_CACHE_MASK;
			footBteLen = L1_CACHE_BYTES;

			footBteSource = src + len - footBcopyLen;
			footBcopyDest = dest + len - footBcopyLen;

			if (footBcopyDest == (headBcopyDest + headBcopyLen)) {
				/*
				 * We have two contiguous bcopy
				 * blocks.  Merge them.
				 */
				headBcopyLen += footBcopyLen;
				headBteLen += footBteLen;
			} else if (footBcopyLen > 0) {
				rv = bte_copy(footBteSource,
					      ia64_tpa((unsigned long)bteBlock),
					      footBteLen, mode, NULL);
				if (rv != BTE_SUCCESS) {
					kfree(bteBlock_unaligned);
					return rv;
				}

				memcpy(__va(footBcopyDest),
				       (char *)bteBlock, footBcopyLen);
			}
		} else {
			footBcopyLen = 0;
			footBteLen = 0;
		}

		if (len > (headBcopyLen + footBcopyLen)) {
			/* now transfer the middle. */
			rv = bte_copy((src + headBcopyLen),
				      (dest +
				       headBcopyLen),
				      (len - headBcopyLen -
				       footBcopyLen), mode, NULL);
			if (rv != BTE_SUCCESS) {
				kfree(bteBlock_unaligned);
				return rv;
			}

		}
	} else {

		/*
		 * The transfer is not symmetric, we will
		 * allocate a buffer large enough for all the
		 * data, bte_copy into that buffer and then
		 * bcopy to the destination.
		 */

		headBcopySrcOffset = src & L1_CACHE_MASK;
		headBcopyDest = dest;
		headBcopyLen = len;

		headBteSource = src - headBcopySrcOffset;
		/* Add the leading and trailing bytes from source */
		headBteLen = L1_CACHE_ALIGN(len + headBcopySrcOffset);
	}

	if (headBcopyLen > 0) {
		rv = bte_copy(headBteSource,
			      ia64_tpa((unsigned long)bteBlock), headBteLen,
			      mode, NULL);
		if (rv != BTE_SUCCESS) {
			kfree(bteBlock_unaligned);
			return rv;
		}

		memcpy(__va(headBcopyDest), ((char *)bteBlock +
					     headBcopySrcOffset), headBcopyLen);
	}
	kfree(bteBlock_unaligned);
	return BTE_SUCCESS;
}

EXPORT_SYMBOL(bte_unaligned_copy);

/************************************************************************
 * Block Transfer Engine initialization functions.
 *
 ***********************************************************************/

/*
 * bte_init_node(nodepda, cnode)
 *
 * Initialize the nodepda structure with BTE base addresses and
 * spinlocks.
 */
void bte_init_node(nodepda_t * mynodepda, cnodeid_t cnode)
{
	int i;

	/*
	 * Indicate that all the block transfer engines on this node
	 * are available.
	 */

	/*
	 * Allocate one bte_recover_t structure per node.  It holds
	 * the recovery lock for node.  All the bte interface structures
	 * will point at this one bte_recover structure to get the lock.
	 */
	spin_lock_init(&mynodepda->bte_recovery_lock);
	init_timer(&mynodepda->bte_recovery_timer);
	mynodepda->bte_recovery_timer.function = bte_error_handler;
	mynodepda->bte_recovery_timer.data = (unsigned long)mynodepda;

	for (i = 0; i < BTES_PER_NODE; i++) {
		u64 *base_addr;

		/* Which link status register should we use? */
		base_addr = (u64 *)
		    REMOTE_HUB_ADDR(cnodeid_to_nasid(cnode), BTE_BASE_ADDR(i));
		mynodepda->bte_if[i].bte_base_addr = base_addr;
		mynodepda->bte_if[i].bte_source_addr = BTE_SOURCE_ADDR(base_addr);
		mynodepda->bte_if[i].bte_destination_addr = BTE_DEST_ADDR(base_addr);
		mynodepda->bte_if[i].bte_control_addr = BTE_CTRL_ADDR(base_addr);
		mynodepda->bte_if[i].bte_notify_addr = BTE_NOTIF_ADDR(base_addr);

		/*
		 * Initialize the notification and spinlock
		 * so the first transfer can occur.
		 */
		mynodepda->bte_if[i].most_rcnt_na =
		    &(mynodepda->bte_if[i].notify);
		mynodepda->bte_if[i].notify = BTE_WORD_AVAILABLE;
		spin_lock_init(&mynodepda->bte_if[i].spinlock);

		mynodepda->bte_if[i].bte_cnode = cnode;
		mynodepda->bte_if[i].bte_error_count = 0;
		mynodepda->bte_if[i].bte_num = i;
		mynodepda->bte_if[i].cleanup_active = 0;
		mynodepda->bte_if[i].bh_error = 0;
	}

}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
913e4a75	6	* Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved.
1da177e4 LT	7	*/
1da177e4 LT	8
1da177e4 LT	9	#include <linux/module.h>
	10	#include <asm/sn/nodepda.h>
	11	#include <asm/sn/addrs.h>
	12	#include <asm/sn/arch.h>
	13	#include <asm/sn/sn_cpuid.h>
	14	#include <asm/sn/pda.h>
	15	#include <asm/sn/shubio.h>
	16	#include <asm/nodedata.h>
	17	#include <asm/delay.h>
	18
	19	#include <linux/bootmem.h>
	20	#include <linux/string.h>
	21	#include <linux/sched.h>
	22
	23	#include <asm/sn/bte.h>
	24
	25	#ifndef L1_CACHE_MASK
	26	#define L1_CACHE_MASK (L1_CACHE_BYTES - 1)
	27	#endif
	28
	29	/* two interfaces on two btes */
	30	#define MAX_INTERFACES_TO_TRY 4
7e95b9d6	31	#define MAX_NODES_TO_TRY 2
1da177e4 LT	32
	33	static struct bteinfo_s *bte_if_on_node(nasid_t nasid, int interface)
	34	{
	35	nodepda_t *tmp_nodepda;
	36
7e95b9d6	37	if (nasid_to_cnodeid(nasid) == -1)
53b3531b	38	return (struct bteinfo_s *)NULL;
7e95b9d6	39
1da177e4 LT	40	tmp_nodepda = NODEPDA(nasid_to_cnodeid(nasid));
	41	return &tmp_nodepda->bte_if[interface];
	42
	43	}
	44
7e95b9d6 JS	45	static inline void bte_start_transfer(struct bteinfo_s *bte, u64 len, u64 mode)
	46	{
	47	if (is_shub2()) {
	48	BTE_CTRL_STORE(bte, (IBLS_BUSY \| ((len) \| (mode) << 24)));
	49	} else {
	50	BTE_LNSTAT_STORE(bte, len);
	51	BTE_CTRL_STORE(bte, mode);
	52	}
	53	}
	54
1da177e4 LT	55	/************************************************************************
	56	* Block Transfer Engine copy related functions.
	57	*
	58	***********************************************************************/
	59
	60	/*
	61	* bte_copy(src, dest, len, mode, notification)
	62	*
	63	* Use the block transfer engine to move kernel memory from src to dest
	64	* using the assigned mode.
	65	*
72fdbdce	66	* Parameters:
1da177e4 LT	67	* src - physical address of the transfer source.
	68	* dest - physical address of the transfer destination.
	69	* len - number of bytes to transfer from source to dest.
	70	* mode - hardware defined. See reference information
	71	* for IBCT0/1 in the SHUB Programmers Reference
	72	* notification - kernel virtual address of the notification cache
	73	* line. If NULL, the default is used and
	74	* the bte_copy is synchronous.
	75	*
	76	* NOTE: This function requires src, dest, and len to
	77	* be cacheline aligned.
	78	*/
	79	bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
	80	{
	81	u64 transfer_size;
	82	u64 transfer_stat;
7e95b9d6	83	u64 notif_phys_addr;
1da177e4 LT	84	struct bteinfo_s *bte;
	85	bte_result_t bte_status;
	86	unsigned long irq_flags;
	87	unsigned long itc_end = 0;
7e95b9d6	88	int nasid_to_try[MAX_NODES_TO_TRY];
e7f98dbb	89	int my_nasid = cpuid_to_nasid(raw_smp_processor_id());
7e95b9d6 JS	90	int bte_if_index, nasid_index;
7e95b9d6 JS	91	int bte_first, btes_per_node = BTES_PER_NODE;
1da177e4 LT	92
	93	BTE_PRINTK(("bte_copy(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%p)\n",
	94	src, dest, len, mode, notification));
	95
	96	if (len == 0) {
	97	return BTE_SUCCESS;
	98	}
	99
	100	BUG_ON((len & L1_CACHE_MASK) \|\|
	101	(src & L1_CACHE_MASK) \|\| (dest & L1_CACHE_MASK));
	102	BUG_ON(!(len < ((BTE_LEN_MASK + 1) << L1_CACHE_SHIFT)));
	103
7e95b9d6 JS	104	/*
	105	* Start with interface corresponding to cpu number
	106	*/
d1e079b3	107	bte_first = raw_smp_processor_id() % btes_per_node;
1da177e4 LT	108
	109	if (mode & BTE_USE_DEST) {
	110	/* try remote then local */
7e95b9d6	111	nasid_to_try[0] = NASID_GET(dest);
1da177e4	112	if (mode & BTE_USE_ANY) {
7e95b9d6	113	nasid_to_try[1] = my_nasid;
1da177e4	114	} else {
7e95b9d6	115	nasid_to_try[1] = (int)NULL;
1da177e4 LT	116	}
	117	} else {
	118	/* try local then remote */
7e95b9d6	119	nasid_to_try[0] = my_nasid;
1da177e4	120	if (mode & BTE_USE_ANY) {
7e95b9d6	121	nasid_to_try[1] = NASID_GET(dest);
1da177e4	122	} else {
7e95b9d6	123	nasid_to_try[1] = (int)NULL;
1da177e4 LT	124	}
	125	}
	126
	127	retry_bteop:
	128	do {
	129	local_irq_save(irq_flags);
	130
7e95b9d6 JS	131	bte_if_index = bte_first;
7e95b9d6 JS	132	nasid_index = 0;
1da177e4 LT	133
1da177e4 LT	134	/* Attempt to lock one of the BTE interfaces. */
7e95b9d6 JS	135	while (nasid_index < MAX_NODES_TO_TRY) {
7e95b9d6 JS	136	bte = bte_if_on_node(nasid_to_try[nasid_index],bte_if_index);
1da177e4 LT	137
1da177e4 LT	138	if (bte == NULL) {
ab2ff46a	139	nasid_index++;
1da177e4 LT	140	continue;
	141	}
	142
	143	if (spin_trylock(&bte->spinlock)) {
	144	if (!(*bte->most_rcnt_na & BTE_WORD_AVAILABLE) \|\|
	145	(BTE_LNSTAT_LOAD(bte) & BTE_ACTIVE)) {
	146	/* Got the lock but BTE still busy */
	147	spin_unlock(&bte->spinlock);
	148	} else {
	149	/* we got the lock and it's not busy */
	150	break;
	151	}
	152	}
7e95b9d6 JS	153
	154	bte_if_index = (bte_if_index + 1) % btes_per_node; /* Next interface */
	155	if (bte_if_index == bte_first) {
	156	/*
	157	* We've tried all interfaces on this node
	158	*/
	159	nasid_index++;
	160	}
	161
1da177e4 LT	162	bte = NULL;
	163	}
	164
	165	if (bte != NULL) {
	166	break;
	167	}
	168
	169	local_irq_restore(irq_flags);
	170
	171	if (!(mode & BTE_WACQUIRE)) {
	172	return BTEFAIL_NOTAVAIL;
	173	}
	174	} while (1);
	175
	176	if (notification == NULL) {
	177	/* User does not want to be notified. */
	178	bte->most_rcnt_na = &bte->notify;
	179	} else {
	180	bte->most_rcnt_na = notification;
	181	}
	182
	183	/* Calculate the number of cache lines to transfer. */
	184	transfer_size = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK);
	185
	186	/* Initialize the notification to a known value. */
	187	*bte->most_rcnt_na = BTE_WORD_BUSY;
913e4a75	188	notif_phys_addr = (u64)bte->most_rcnt_na;
1da177e4	189
1da177e4	190	/* Set the source and destination registers */
913e4a75 RA	191	BTE_PRINTKV(("IBSA = 0x%lx)\n", src));
	192	BTE_SRC_STORE(bte, src);
	193	BTE_PRINTKV(("IBDA = 0x%lx)\n", dest));
	194	BTE_DEST_STORE(bte, dest);
1da177e4 LT	195
1da177e4 LT	196	/* Set the notification register */
7e95b9d6 JS	197	BTE_PRINTKV(("IBNA = 0x%lx)\n", notif_phys_addr));
7e95b9d6 JS	198	BTE_NOTIF_STORE(bte, notif_phys_addr);
1da177e4 LT	199
	200	/* Initiate the transfer */
	201	BTE_PRINTK(("IBCT = 0x%lx)\n", BTE_VALID_MODE(mode)));
7e95b9d6	202	bte_start_transfer(bte, transfer_size, BTE_VALID_MODE(mode));
1da177e4 LT	203
	204	itc_end = ia64_get_itc() + (40000000 * local_cpu_data->cyc_per_usec);
	205
	206	spin_unlock_irqrestore(&bte->spinlock, irq_flags);
	207
	208	if (notification != NULL) {
	209	return BTE_SUCCESS;
	210	}
	211
	212	while ((transfer_stat = *bte->most_rcnt_na) == BTE_WORD_BUSY) {
68b9753f	213	cpu_relax();
1da177e4 LT	214	if (ia64_get_itc() > itc_end) {
	215	BTE_PRINTK(("BTE timeout nasid 0x%x bte%d IBLS = 0x%lx na 0x%lx\n",
	216	NASID_GET(bte->bte_base_addr), bte->bte_num,
	217	BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na) );
	218	bte->bte_error_count++;
	219	bte->bh_error = IBLS_ERROR;
	220	bte_error_handler((unsigned long)NODEPDA(bte->bte_cnode));
	221	*bte->most_rcnt_na = BTE_WORD_AVAILABLE;
	222	goto retry_bteop;
	223	}
	224	}
	225
	226	BTE_PRINTKV((" Delay Done. IBLS = 0x%lx, most_rcnt_na = 0x%lx\n",
	227	BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
	228
	229	if (transfer_stat & IBLS_ERROR) {
	230	bte_status = transfer_stat & ~IBLS_ERROR;
	231	} else {
	232	bte_status = BTE_SUCCESS;
	233	}
	234	*bte->most_rcnt_na = BTE_WORD_AVAILABLE;
	235
	236	BTE_PRINTK(("Returning status is 0x%lx and most_rcnt_na is 0x%lx\n",
	237	BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
	238
	239	return bte_status;
	240	}
	241
	242	EXPORT_SYMBOL(bte_copy);
	243
	244	/*
	245	* bte_unaligned_copy(src, dest, len, mode)
	246	*
	247	* use the block transfer engine to move kernel
	248	* memory from src to dest using the assigned mode.
	249	*
72fdbdce	250	* Parameters:
1da177e4 LT	251	* src - physical address of the transfer source.
	252	* dest - physical address of the transfer destination.
	253	* len - number of bytes to transfer from source to dest.
	254	* mode - hardware defined. See reference information
	255	* for IBCT0/1 in the SGI documentation.
	256	*
	257	* NOTE: If the source, dest, and len are all cache line aligned,
72fdbdce	258	* then it would be _FAR_ preferable to use bte_copy instead.
1da177e4 LT	259	*/
	260	bte_result_t bte_unaligned_copy(u64 src, u64 dest, u64 len, u64 mode)
	261	{
	262	int destFirstCacheOffset;
	263	u64 headBteSource;
	264	u64 headBteLen;
	265	u64 headBcopySrcOffset;
	266	u64 headBcopyDest;
	267	u64 headBcopyLen;
	268	u64 footBteSource;
	269	u64 footBteLen;
	270	u64 footBcopyDest;
	271	u64 footBcopyLen;
	272	bte_result_t rv;
	273	char bteBlock, bteBlock_unaligned;
	274
	275	if (len == 0) {
	276	return BTE_SUCCESS;
	277	}
	278
	279	/* temporary buffer used during unaligned transfers */
fd1dfc6f	280	bteBlock_unaligned = kmalloc(len + 3 * L1_CACHE_BYTES, GFP_KERNEL);
1da177e4 LT	281	if (bteBlock_unaligned == NULL) {
	282	return BTEFAIL_NOTAVAIL;
	283	}
	284	bteBlock = (char *)L1_CACHE_ALIGN((u64) bteBlock_unaligned);
	285
	286	headBcopySrcOffset = src & L1_CACHE_MASK;
	287	destFirstCacheOffset = dest & L1_CACHE_MASK;
	288
	289	/*
	290	* At this point, the transfer is broken into
	291	* (up to) three sections. The first section is
	292	* from the start address to the first physical
	293	* cache line, the second is from the first physical
	294	* cache line to the last complete cache line,
	295	* and the third is from the last cache line to the
	296	* end of the buffer. The first and third sections
	297	* are handled by bte copying into a temporary buffer
	298	* and then bcopy'ing the necessary section into the
	299	* final location. The middle section is handled with
	300	* a standard bte copy.
	301	*
	302	* One nasty exception to the above rule is when the
72fdbdce	303	* source and destination are not symmetrically
1da177e4 LT	304	* mis-aligned. If the source offset from the first
	305	* cache line is different from the destination offset,
	306	* we make the first section be the entire transfer
	307	* and the bcopy the entire block into place.
	308	*/
	309	if (headBcopySrcOffset == destFirstCacheOffset) {
	310
	311	/*
	312	* Both the source and destination are the same
	313	* distance from a cache line boundary so we can
	314	* use the bte to transfer the bulk of the
	315	* data.
	316	*/
	317	headBteSource = src & ~L1_CACHE_MASK;
	318	headBcopyDest = dest;
	319	if (headBcopySrcOffset) {
	320	headBcopyLen =
	321	(len >
	322	(L1_CACHE_BYTES -
	323	headBcopySrcOffset) ? L1_CACHE_BYTES
	324	- headBcopySrcOffset : len);
	325	headBteLen = L1_CACHE_BYTES;
	326	} else {
	327	headBcopyLen = 0;
	328	headBteLen = 0;
	329	}
	330
	331	if (len > headBcopyLen) {
	332	footBcopyLen = (len - headBcopyLen) & L1_CACHE_MASK;
	333	footBteLen = L1_CACHE_BYTES;
	334
	335	footBteSource = src + len - footBcopyLen;
	336	footBcopyDest = dest + len - footBcopyLen;
	337
	338	if (footBcopyDest == (headBcopyDest + headBcopyLen)) {
	339	/*
72fdbdce	340	* We have two contiguous bcopy
1da177e4 LT	341	* blocks. Merge them.
	342	*/
	343	headBcopyLen += footBcopyLen;
	344	headBteLen += footBteLen;
	345	} else if (footBcopyLen > 0) {
	346	rv = bte_copy(footBteSource,
	347	ia64_tpa((unsigned long)bteBlock),
	348	footBteLen, mode, NULL);
	349	if (rv != BTE_SUCCESS) {
	350	kfree(bteBlock_unaligned);
	351	return rv;
	352	}
	353
	354	memcpy(__va(footBcopyDest),
	355	(char *)bteBlock, footBcopyLen);
	356	}
	357	} else {
	358	footBcopyLen = 0;
	359	footBteLen = 0;
	360	}
	361
	362	if (len > (headBcopyLen + footBcopyLen)) {
	363	/* now transfer the middle. */
	364	rv = bte_copy((src + headBcopyLen),
	365	(dest +
	366	headBcopyLen),
	367	(len - headBcopyLen -
	368	footBcopyLen), mode, NULL);
	369	if (rv != BTE_SUCCESS) {
	370	kfree(bteBlock_unaligned);
	371	return rv;
	372	}
	373
	374	}
	375	} else {
	376
	377	/*
72fdbdce	378	* The transfer is not symmetric, we will
1da177e4 LT	379	* allocate a buffer large enough for all the
	380	* data, bte_copy into that buffer and then
	381	* bcopy to the destination.
	382	*/
	383
1da177e4 LT	384	headBcopySrcOffset = src & L1_CACHE_MASK;
	385	headBcopyDest = dest;
	386	headBcopyLen = len;
cbf093e8 RH	387
	388	headBteSource = src - headBcopySrcOffset;
	389	/* Add the leading and trailing bytes from source */
	390	headBteLen = L1_CACHE_ALIGN(len + headBcopySrcOffset);
1da177e4 LT	391	}
	392
	393	if (headBcopyLen > 0) {
	394	rv = bte_copy(headBteSource,
	395	ia64_tpa((unsigned long)bteBlock), headBteLen,
	396	mode, NULL);
	397	if (rv != BTE_SUCCESS) {
	398	kfree(bteBlock_unaligned);
	399	return rv;
	400	}
	401
	402	memcpy(__va(headBcopyDest), ((char *)bteBlock +
	403	headBcopySrcOffset), headBcopyLen);
	404	}
	405	kfree(bteBlock_unaligned);
	406	return BTE_SUCCESS;
	407	}
	408
	409	EXPORT_SYMBOL(bte_unaligned_copy);
	410
	411	/************************************************************************
	412	* Block Transfer Engine initialization functions.
	413	*
	414	***********************************************************************/
	415
	416	/*
	417	* bte_init_node(nodepda, cnode)
	418	*
	419	* Initialize the nodepda structure with BTE base addresses and
	420	* spinlocks.
	421	*/
	422	void bte_init_node(nodepda_t * mynodepda, cnodeid_t cnode)
	423	{
	424	int i;
	425
	426	/*
	427	* Indicate that all the block transfer engines on this node
	428	* are available.
	429	*/
	430
	431	/*
	432	* Allocate one bte_recover_t structure per node. It holds
	433	* the recovery lock for node. All the bte interface structures
	434	* will point at this one bte_recover structure to get the lock.
	435	*/
	436	spin_lock_init(&mynodepda->bte_recovery_lock);
	437	init_timer(&mynodepda->bte_recovery_timer);
	438	mynodepda->bte_recovery_timer.function = bte_error_handler;
	439	mynodepda->bte_recovery_timer.data = (unsigned long)mynodepda;
	440
	441	for (i = 0; i < BTES_PER_NODE; i++) {
95ff439a RA	442	u64 *base_addr;
95ff439a RA	443
1da177e4	444	/* Which link status register should we use? */
95ff439a RA	445	base_addr = (u64 *)
	446	REMOTE_HUB_ADDR(cnodeid_to_nasid(cnode), BTE_BASE_ADDR(i));
	447	mynodepda->bte_if[i].bte_base_addr = base_addr;
	448	mynodepda->bte_if[i].bte_source_addr = BTE_SOURCE_ADDR(base_addr);
	449	mynodepda->bte_if[i].bte_destination_addr = BTE_DEST_ADDR(base_addr);
	450	mynodepda->bte_if[i].bte_control_addr = BTE_CTRL_ADDR(base_addr);
	451	mynodepda->bte_if[i].bte_notify_addr = BTE_NOTIF_ADDR(base_addr);
1da177e4 LT	452
	453	/*
	454	* Initialize the notification and spinlock
	455	* so the first transfer can occur.
	456	*/
	457	mynodepda->bte_if[i].most_rcnt_na =
	458	&(mynodepda->bte_if[i].notify);
	459	mynodepda->bte_if[i].notify = BTE_WORD_AVAILABLE;
	460	spin_lock_init(&mynodepda->bte_if[i].spinlock);
	461
	462	mynodepda->bte_if[i].bte_cnode = cnode;
	463	mynodepda->bte_if[i].bte_error_count = 0;
	464	mynodepda->bte_if[i].bte_num = i;
	465	mynodepda->bte_if[i].cleanup_active = 0;
	466	mynodepda->bte_if[i].bh_error = 0;
	467	}
	468
	469	}