Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.c - Low-Level PCI Access in IA-64 | |
3 | * | |
4 | * Derived from bios32.c of i386 tree. | |
5 | * | |
6 | * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
9 | * Copyright (C) 2004 Silicon Graphics, Inc. | |
10 | * | |
11 | * Note: Above list of copyright holders is incomplete... | |
12 | */ | |
1da177e4 LT |
13 | |
14 | #include <linux/acpi.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/slab.h> | |
1da177e4 | 21 | #include <linux/spinlock.h> |
175add19 | 22 | #include <linux/bootmem.h> |
1da177e4 LT |
23 | |
24 | #include <asm/machvec.h> | |
25 | #include <asm/page.h> | |
1da177e4 LT |
26 | #include <asm/system.h> |
27 | #include <asm/io.h> | |
28 | #include <asm/sal.h> | |
29 | #include <asm/smp.h> | |
30 | #include <asm/irq.h> | |
31 | #include <asm/hw_irq.h> | |
32 | ||
1da177e4 LT |
33 | /* |
34 | * Low-level SAL-based PCI configuration access functions. Note that SAL | |
35 | * calls are already serialized (via sal_lock), so we don't need another | |
36 | * synchronization mechanism here. | |
37 | */ | |
38 | ||
39 | #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ | |
40 | (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) | |
41 | ||
42 | /* SAL 3.2 adds support for extended config space. */ | |
43 | ||
44 | #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ | |
45 | (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) | |
46 | ||
b6ce068a | 47 | int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
48 | int reg, int len, u32 *value) |
49 | { | |
50 | u64 addr, data = 0; | |
51 | int mode, result; | |
52 | ||
53 | if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
54 | return -EINVAL; | |
55 | ||
56 | if ((seg | reg) <= 255) { | |
57 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
58 | mode = 0; | |
59 | } else { | |
60 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); | |
61 | mode = 1; | |
62 | } | |
63 | result = ia64_sal_pci_config_read(addr, mode, len, &data); | |
64 | if (result != 0) | |
65 | return -EINVAL; | |
66 | ||
67 | *value = (u32) data; | |
68 | return 0; | |
69 | } | |
70 | ||
b6ce068a | 71 | int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
72 | int reg, int len, u32 value) |
73 | { | |
74 | u64 addr; | |
75 | int mode, result; | |
76 | ||
77 | if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
78 | return -EINVAL; | |
79 | ||
80 | if ((seg | reg) <= 255) { | |
81 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
82 | mode = 0; | |
83 | } else { | |
84 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); | |
85 | mode = 1; | |
86 | } | |
87 | result = ia64_sal_pci_config_write(addr, mode, len, value); | |
88 | if (result != 0) | |
89 | return -EINVAL; | |
90 | return 0; | |
91 | } | |
92 | ||
b6ce068a MW |
93 | static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, |
94 | int size, u32 *value) | |
1da177e4 | 95 | { |
b6ce068a | 96 | return raw_pci_read(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
97 | devfn, where, size, value); |
98 | } | |
99 | ||
b6ce068a MW |
100 | static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, |
101 | int size, u32 value) | |
1da177e4 | 102 | { |
b6ce068a | 103 | return raw_pci_write(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
104 | devfn, where, size, value); |
105 | } | |
106 | ||
107 | struct pci_ops pci_root_ops = { | |
108 | .read = pci_read, | |
109 | .write = pci_write, | |
110 | }; | |
111 | ||
1da177e4 LT |
112 | /* Called by ACPI when it finds a new root bus. */ |
113 | ||
114 | static struct pci_controller * __devinit | |
115 | alloc_pci_controller (int seg) | |
116 | { | |
117 | struct pci_controller *controller; | |
118 | ||
52fd9108 | 119 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); |
1da177e4 LT |
120 | if (!controller) |
121 | return NULL; | |
122 | ||
1da177e4 | 123 | controller->segment = seg; |
514604c6 | 124 | controller->node = -1; |
1da177e4 LT |
125 | return controller; |
126 | } | |
127 | ||
4f41d5a4 BH |
128 | struct pci_root_info { |
129 | struct pci_controller *controller; | |
130 | char *name; | |
131 | }; | |
132 | ||
133 | static unsigned int | |
134 | new_space (u64 phys_base, int sparse) | |
1da177e4 | 135 | { |
4f41d5a4 | 136 | u64 mmio_base; |
1da177e4 LT |
137 | int i; |
138 | ||
4f41d5a4 BH |
139 | if (phys_base == 0) |
140 | return 0; /* legacy I/O port space */ | |
1da177e4 | 141 | |
4f41d5a4 | 142 | mmio_base = (u64) ioremap(phys_base, 0); |
1da177e4 | 143 | for (i = 0; i < num_io_spaces; i++) |
4f41d5a4 | 144 | if (io_space[i].mmio_base == mmio_base && |
1da177e4 | 145 | io_space[i].sparse == sparse) |
4f41d5a4 | 146 | return i; |
1da177e4 LT |
147 | |
148 | if (num_io_spaces == MAX_IO_SPACES) { | |
4f41d5a4 BH |
149 | printk(KERN_ERR "PCI: Too many IO port spaces " |
150 | "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES); | |
1da177e4 LT |
151 | return ~0; |
152 | } | |
153 | ||
154 | i = num_io_spaces++; | |
4f41d5a4 | 155 | io_space[i].mmio_base = mmio_base; |
1da177e4 LT |
156 | io_space[i].sparse = sparse; |
157 | ||
4f41d5a4 BH |
158 | return i; |
159 | } | |
160 | ||
161 | static u64 __devinit | |
162 | add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr) | |
163 | { | |
164 | struct resource *resource; | |
165 | char *name; | |
e088a4ad | 166 | unsigned long base, min, max, base_port; |
4f41d5a4 BH |
167 | unsigned int sparse = 0, space_nr, len; |
168 | ||
169 | resource = kzalloc(sizeof(*resource), GFP_KERNEL); | |
170 | if (!resource) { | |
171 | printk(KERN_ERR "PCI: No memory for %s I/O port space\n", | |
172 | info->name); | |
173 | goto out; | |
174 | } | |
175 | ||
176 | len = strlen(info->name) + 32; | |
177 | name = kzalloc(len, GFP_KERNEL); | |
178 | if (!name) { | |
179 | printk(KERN_ERR "PCI: No memory for %s I/O port space name\n", | |
180 | info->name); | |
181 | goto free_resource; | |
182 | } | |
183 | ||
50eca3eb | 184 | min = addr->minimum; |
4f41d5a4 | 185 | max = min + addr->address_length - 1; |
0897831b | 186 | if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) |
4f41d5a4 BH |
187 | sparse = 1; |
188 | ||
50eca3eb | 189 | space_nr = new_space(addr->translation_offset, sparse); |
4f41d5a4 BH |
190 | if (space_nr == ~0) |
191 | goto free_name; | |
192 | ||
193 | base = __pa(io_space[space_nr].mmio_base); | |
194 | base_port = IO_SPACE_BASE(space_nr); | |
195 | snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name, | |
196 | base_port + min, base_port + max); | |
197 | ||
198 | /* | |
199 | * The SDM guarantees the legacy 0-64K space is sparse, but if the | |
200 | * mapping is done by the processor (not the bridge), ACPI may not | |
201 | * mark it as sparse. | |
202 | */ | |
203 | if (space_nr == 0) | |
204 | sparse = 1; | |
205 | ||
206 | resource->name = name; | |
207 | resource->flags = IORESOURCE_MEM; | |
208 | resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); | |
209 | resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); | |
210 | insert_resource(&iomem_resource, resource); | |
211 | ||
212 | return base_port; | |
213 | ||
214 | free_name: | |
215 | kfree(name); | |
216 | free_resource: | |
217 | kfree(resource); | |
218 | out: | |
219 | return ~0; | |
1da177e4 LT |
220 | } |
221 | ||
463eb297 BH |
222 | static acpi_status __devinit resource_to_window(struct acpi_resource *resource, |
223 | struct acpi_resource_address64 *addr) | |
224 | { | |
225 | acpi_status status; | |
226 | ||
227 | /* | |
228 | * We're only interested in _CRS descriptors that are | |
229 | * - address space descriptors for memory or I/O space | |
230 | * - non-zero size | |
231 | * - producers, i.e., the address space is routed downstream, | |
232 | * not consumed by the bridge itself | |
233 | */ | |
234 | status = acpi_resource_to_address64(resource, addr); | |
235 | if (ACPI_SUCCESS(status) && | |
236 | (addr->resource_type == ACPI_MEMORY_RANGE || | |
237 | addr->resource_type == ACPI_IO_RANGE) && | |
238 | addr->address_length && | |
239 | addr->producer_consumer == ACPI_PRODUCER) | |
240 | return AE_OK; | |
241 | ||
242 | return AE_ERROR; | |
243 | } | |
244 | ||
1da177e4 LT |
245 | static acpi_status __devinit |
246 | count_window (struct acpi_resource *resource, void *data) | |
247 | { | |
248 | unsigned int *windows = (unsigned int *) data; | |
249 | struct acpi_resource_address64 addr; | |
250 | acpi_status status; | |
251 | ||
463eb297 | 252 | status = resource_to_window(resource, &addr); |
1da177e4 | 253 | if (ACPI_SUCCESS(status)) |
463eb297 | 254 | (*windows)++; |
1da177e4 LT |
255 | |
256 | return AE_OK; | |
257 | } | |
258 | ||
1da177e4 LT |
259 | static __devinit acpi_status add_window(struct acpi_resource *res, void *data) |
260 | { | |
261 | struct pci_root_info *info = data; | |
262 | struct pci_window *window; | |
263 | struct acpi_resource_address64 addr; | |
264 | acpi_status status; | |
265 | unsigned long flags, offset = 0; | |
266 | struct resource *root; | |
267 | ||
463eb297 BH |
268 | /* Return AE_OK for non-window resources to keep scanning for more */ |
269 | status = resource_to_window(res, &addr); | |
1da177e4 LT |
270 | if (!ACPI_SUCCESS(status)) |
271 | return AE_OK; | |
272 | ||
1da177e4 LT |
273 | if (addr.resource_type == ACPI_MEMORY_RANGE) { |
274 | flags = IORESOURCE_MEM; | |
275 | root = &iomem_resource; | |
50eca3eb | 276 | offset = addr.translation_offset; |
1da177e4 LT |
277 | } else if (addr.resource_type == ACPI_IO_RANGE) { |
278 | flags = IORESOURCE_IO; | |
279 | root = &ioport_resource; | |
4f41d5a4 | 280 | offset = add_io_space(info, &addr); |
1da177e4 LT |
281 | if (offset == ~0) |
282 | return AE_OK; | |
283 | } else | |
284 | return AE_OK; | |
285 | ||
286 | window = &info->controller->window[info->controller->windows++]; | |
287 | window->resource.name = info->name; | |
288 | window->resource.flags = flags; | |
50eca3eb | 289 | window->resource.start = addr.minimum + offset; |
4f41d5a4 | 290 | window->resource.end = window->resource.start + addr.address_length - 1; |
1da177e4 LT |
291 | window->resource.child = NULL; |
292 | window->offset = offset; | |
293 | ||
294 | if (insert_resource(root, &window->resource)) { | |
e088a4ad | 295 | printk(KERN_ERR "alloc 0x%llx-0x%llx from %s for %s failed\n", |
1da177e4 LT |
296 | window->resource.start, window->resource.end, |
297 | root->name, info->name); | |
298 | } | |
299 | ||
300 | return AE_OK; | |
301 | } | |
302 | ||
303 | static void __devinit | |
304 | pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) | |
305 | { | |
306 | int i, j; | |
307 | ||
308 | j = 0; | |
309 | for (i = 0; i < ctrl->windows; i++) { | |
310 | struct resource *res = &ctrl->window[i].resource; | |
311 | /* HP's firmware has a hack to work around a Windows bug. | |
312 | * Ignore these tiny memory ranges */ | |
313 | if ((res->flags & IORESOURCE_MEM) && | |
314 | (res->end - res->start < 16)) | |
315 | continue; | |
316 | if (j >= PCI_BUS_NUM_RESOURCES) { | |
e088a4ad MW |
317 | printk("Ignoring range [%#llx-%#llx] (%lx)\n", |
318 | res->start, res->end, res->flags); | |
1da177e4 LT |
319 | continue; |
320 | } | |
321 | bus->resource[j++] = res; | |
322 | } | |
323 | } | |
324 | ||
325 | struct pci_bus * __devinit | |
326 | pci_acpi_scan_root(struct acpi_device *device, int domain, int bus) | |
327 | { | |
1da177e4 LT |
328 | struct pci_controller *controller; |
329 | unsigned int windows = 0; | |
330 | struct pci_bus *pbus; | |
331 | char *name; | |
514604c6 | 332 | int pxm; |
1da177e4 LT |
333 | |
334 | controller = alloc_pci_controller(domain); | |
335 | if (!controller) | |
336 | goto out1; | |
337 | ||
338 | controller->acpi_handle = device->handle; | |
339 | ||
514604c6 CL |
340 | pxm = acpi_get_pxm(controller->acpi_handle); |
341 | #ifdef CONFIG_NUMA | |
342 | if (pxm >= 0) | |
762834e8 | 343 | controller->node = pxm_to_node(pxm); |
514604c6 CL |
344 | #endif |
345 | ||
1da177e4 LT |
346 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, |
347 | &windows); | |
a66aa704 | 348 | if (windows) { |
8a20fd52 LT |
349 | struct pci_root_info info; |
350 | ||
a66aa704 KK |
351 | controller->window = |
352 | kmalloc_node(sizeof(*controller->window) * windows, | |
353 | GFP_KERNEL, controller->node); | |
354 | if (!controller->window) | |
355 | goto out2; | |
1da177e4 | 356 | |
8a20fd52 LT |
357 | name = kmalloc(16, GFP_KERNEL); |
358 | if (!name) | |
359 | goto out3; | |
1da177e4 | 360 | |
8a20fd52 LT |
361 | sprintf(name, "PCI Bus %04x:%02x", domain, bus); |
362 | info.controller = controller; | |
363 | info.name = name; | |
364 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, | |
365 | add_window, &info); | |
366 | } | |
b87e81e5 | 367 | /* |
368 | * See arch/x86/pci/acpi.c. | |
369 | * The desired pci bus might already be scanned in a quirk. We | |
370 | * should handle the case here, but it appears that IA64 hasn't | |
371 | * such quirk. So we just ignore the case now. | |
372 | */ | |
c431ada4 | 373 | pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller); |
1da177e4 LT |
374 | |
375 | return pbus; | |
376 | ||
377 | out3: | |
378 | kfree(controller->window); | |
379 | out2: | |
380 | kfree(controller); | |
381 | out1: | |
382 | return NULL; | |
383 | } | |
384 | ||
385 | void pcibios_resource_to_bus(struct pci_dev *dev, | |
386 | struct pci_bus_region *region, struct resource *res) | |
387 | { | |
388 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
389 | unsigned long offset = 0; | |
390 | int i; | |
391 | ||
392 | for (i = 0; i < controller->windows; i++) { | |
393 | struct pci_window *window = &controller->window[i]; | |
394 | if (!(window->resource.flags & res->flags)) | |
395 | continue; | |
396 | if (window->resource.start > res->start) | |
397 | continue; | |
398 | if (window->resource.end < res->end) | |
399 | continue; | |
400 | offset = window->offset; | |
401 | break; | |
402 | } | |
403 | ||
404 | region->start = res->start - offset; | |
405 | region->end = res->end - offset; | |
406 | } | |
407 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
408 | ||
409 | void pcibios_bus_to_resource(struct pci_dev *dev, | |
410 | struct resource *res, struct pci_bus_region *region) | |
411 | { | |
412 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
413 | unsigned long offset = 0; | |
414 | int i; | |
415 | ||
416 | for (i = 0; i < controller->windows; i++) { | |
417 | struct pci_window *window = &controller->window[i]; | |
418 | if (!(window->resource.flags & res->flags)) | |
419 | continue; | |
420 | if (window->resource.start - window->offset > region->start) | |
421 | continue; | |
422 | if (window->resource.end - window->offset < region->end) | |
423 | continue; | |
424 | offset = window->offset; | |
425 | break; | |
426 | } | |
427 | ||
428 | res->start = region->start + offset; | |
429 | res->end = region->end + offset; | |
430 | } | |
41290c14 | 431 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 432 | |
71c3511c RS |
433 | static int __devinit is_valid_resource(struct pci_dev *dev, int idx) |
434 | { | |
435 | unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; | |
436 | struct resource *devr = &dev->resource[idx]; | |
437 | ||
438 | if (!dev->bus) | |
439 | return 0; | |
440 | for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) { | |
441 | struct resource *busr = dev->bus->resource[i]; | |
442 | ||
443 | if (!busr || ((busr->flags ^ devr->flags) & type_mask)) | |
444 | continue; | |
445 | if ((devr->start) && (devr->start >= busr->start) && | |
446 | (devr->end <= busr->end)) | |
447 | return 1; | |
448 | } | |
449 | return 0; | |
450 | } | |
451 | ||
7b9c8ba2 KK |
452 | static void __devinit |
453 | pcibios_fixup_resources(struct pci_dev *dev, int start, int limit) | |
1da177e4 LT |
454 | { |
455 | struct pci_bus_region region; | |
456 | int i; | |
1da177e4 | 457 | |
7b9c8ba2 | 458 | for (i = start; i < limit; i++) { |
1da177e4 LT |
459 | if (!dev->resource[i].flags) |
460 | continue; | |
461 | region.start = dev->resource[i].start; | |
462 | region.end = dev->resource[i].end; | |
463 | pcibios_bus_to_resource(dev, &dev->resource[i], ®ion); | |
71c3511c RS |
464 | if ((is_valid_resource(dev, i))) |
465 | pci_claim_resource(dev, i); | |
1da177e4 LT |
466 | } |
467 | } | |
468 | ||
8ea6091f | 469 | void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) |
7b9c8ba2 KK |
470 | { |
471 | pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES); | |
472 | } | |
8ea6091f | 473 | EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources); |
7b9c8ba2 KK |
474 | |
475 | static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev) | |
476 | { | |
477 | pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES); | |
478 | } | |
479 | ||
1da177e4 LT |
480 | /* |
481 | * Called after each bus is probed, but before its children are examined. | |
482 | */ | |
483 | void __devinit | |
484 | pcibios_fixup_bus (struct pci_bus *b) | |
485 | { | |
486 | struct pci_dev *dev; | |
487 | ||
f7d473d9 RS |
488 | if (b->self) { |
489 | pci_read_bridge_bases(b); | |
7b9c8ba2 | 490 | pcibios_fixup_bridge_resources(b->self); |
1d89b30c MW |
491 | } else { |
492 | pcibios_setup_root_windows(b, b->sysdata); | |
f7d473d9 | 493 | } |
1da177e4 LT |
494 | list_for_each_entry(dev, &b->devices, bus_list) |
495 | pcibios_fixup_device_resources(dev); | |
8ea6091f | 496 | platform_pci_fixup_bus(b); |
1da177e4 LT |
497 | |
498 | return; | |
499 | } | |
500 | ||
501 | void __devinit | |
502 | pcibios_update_irq (struct pci_dev *dev, int irq) | |
503 | { | |
504 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
505 | ||
506 | /* ??? FIXME -- record old value for shutdown. */ | |
507 | } | |
508 | ||
1da177e4 LT |
509 | int |
510 | pcibios_enable_device (struct pci_dev *dev, int mask) | |
511 | { | |
512 | int ret; | |
513 | ||
d981f163 | 514 | ret = pci_enable_resources(dev, mask); |
1da177e4 LT |
515 | if (ret < 0) |
516 | return ret; | |
517 | ||
bba6f6fc EB |
518 | if (!dev->msi_enabled) |
519 | return acpi_pci_irq_enable(dev); | |
520 | return 0; | |
1da177e4 LT |
521 | } |
522 | ||
1da177e4 LT |
523 | void |
524 | pcibios_disable_device (struct pci_dev *dev) | |
525 | { | |
c7f570a5 | 526 | BUG_ON(atomic_read(&dev->enable_cnt)); |
bba6f6fc EB |
527 | if (!dev->msi_enabled) |
528 | acpi_pci_irq_disable(dev); | |
1da177e4 | 529 | } |
1da177e4 LT |
530 | |
531 | void | |
532 | pcibios_align_resource (void *data, struct resource *res, | |
e31dd6e4 | 533 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
534 | { |
535 | } | |
536 | ||
537 | /* | |
538 | * PCI BIOS setup, always defaults to SAL interface | |
539 | */ | |
944c54e7 | 540 | char * __init |
1da177e4 LT |
541 | pcibios_setup (char *str) |
542 | { | |
ac311ac2 | 543 | return str; |
1da177e4 LT |
544 | } |
545 | ||
546 | int | |
547 | pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
548 | enum pci_mmap_state mmap_state, int write_combine) | |
549 | { | |
012b7105 AC |
550 | unsigned long size = vma->vm_end - vma->vm_start; |
551 | pgprot_t prot; | |
552 | ||
1da177e4 LT |
553 | /* |
554 | * I/O space cannot be accessed via normal processor loads and | |
555 | * stores on this platform. | |
556 | */ | |
557 | if (mmap_state == pci_mmap_io) | |
558 | /* | |
559 | * XXX we could relax this for I/O spaces for which ACPI | |
560 | * indicates that the space is 1-to-1 mapped. But at the | |
561 | * moment, we don't support multiple PCI address spaces and | |
562 | * the legacy I/O space is not 1-to-1 mapped, so this is moot. | |
563 | */ | |
564 | return -EINVAL; | |
565 | ||
012b7105 AC |
566 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
567 | return -EINVAL; | |
568 | ||
569 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
570 | vma->vm_page_prot); | |
571 | ||
1da177e4 | 572 | /* |
012b7105 AC |
573 | * If the user requested WC, the kernel uses UC or WC for this region, |
574 | * and the chipset supports WC, we can use WC. Otherwise, we have to | |
575 | * use the same attribute the kernel uses. | |
1da177e4 | 576 | */ |
012b7105 AC |
577 | if (write_combine && |
578 | ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC || | |
579 | (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) && | |
580 | efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) | |
1da177e4 LT |
581 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); |
582 | else | |
012b7105 | 583 | vma->vm_page_prot = prot; |
1da177e4 LT |
584 | |
585 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
586 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
587 | return -EAGAIN; | |
588 | ||
589 | return 0; | |
590 | } | |
591 | ||
592 | /** | |
593 | * ia64_pci_get_legacy_mem - generic legacy mem routine | |
594 | * @bus: bus to get legacy memory base address for | |
595 | * | |
596 | * Find the base of legacy memory for @bus. This is typically the first | |
597 | * megabyte of bus address space for @bus or is simply 0 on platforms whose | |
598 | * chipsets support legacy I/O and memory routing. Returns the base address | |
599 | * or an error pointer if an error occurred. | |
600 | * | |
601 | * This is the ia64 generic version of this routine. Other platforms | |
602 | * are free to override it with a machine vector. | |
603 | */ | |
604 | char *ia64_pci_get_legacy_mem(struct pci_bus *bus) | |
605 | { | |
606 | return (char *)__IA64_UNCACHED_OFFSET; | |
607 | } | |
608 | ||
609 | /** | |
610 | * pci_mmap_legacy_page_range - map legacy memory space to userland | |
611 | * @bus: bus whose legacy space we're mapping | |
612 | * @vma: vma passed in by mmap | |
613 | * | |
614 | * Map legacy memory space for this device back to userspace using a machine | |
615 | * vector to get the base address. | |
616 | */ | |
617 | int | |
f19aeb1f BH |
618 | pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma, |
619 | enum pci_mmap_state mmap_state) | |
1da177e4 | 620 | { |
32e62c63 BH |
621 | unsigned long size = vma->vm_end - vma->vm_start; |
622 | pgprot_t prot; | |
1da177e4 LT |
623 | char *addr; |
624 | ||
f19aeb1f BH |
625 | /* We only support mmap'ing of legacy memory space */ |
626 | if (mmap_state != pci_mmap_mem) | |
627 | return -ENOSYS; | |
628 | ||
32e62c63 BH |
629 | /* |
630 | * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt | |
631 | * for more details. | |
632 | */ | |
06c67bef | 633 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
32e62c63 BH |
634 | return -EINVAL; |
635 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
636 | vma->vm_page_prot); | |
32e62c63 | 637 | |
1da177e4 LT |
638 | addr = pci_get_legacy_mem(bus); |
639 | if (IS_ERR(addr)) | |
640 | return PTR_ERR(addr); | |
641 | ||
642 | vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; | |
32e62c63 | 643 | vma->vm_page_prot = prot; |
1da177e4 LT |
644 | |
645 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
32e62c63 | 646 | size, vma->vm_page_prot)) |
1da177e4 LT |
647 | return -EAGAIN; |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
652 | /** | |
653 | * ia64_pci_legacy_read - read from legacy I/O space | |
654 | * @bus: bus to read | |
655 | * @port: legacy port value | |
656 | * @val: caller allocated storage for returned value | |
657 | * @size: number of bytes to read | |
658 | * | |
659 | * Simply reads @size bytes from @port and puts the result in @val. | |
660 | * | |
661 | * Again, this (and the write routine) are generic versions that can be | |
662 | * overridden by the platform. This is necessary on platforms that don't | |
663 | * support legacy I/O routing or that hard fail on legacy I/O timeouts. | |
664 | */ | |
665 | int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
666 | { | |
667 | int ret = size; | |
668 | ||
669 | switch (size) { | |
670 | case 1: | |
671 | *val = inb(port); | |
672 | break; | |
673 | case 2: | |
674 | *val = inw(port); | |
675 | break; | |
676 | case 4: | |
677 | *val = inl(port); | |
678 | break; | |
679 | default: | |
680 | ret = -EINVAL; | |
681 | break; | |
682 | } | |
683 | ||
684 | return ret; | |
685 | } | |
686 | ||
687 | /** | |
688 | * ia64_pci_legacy_write - perform a legacy I/O write | |
689 | * @bus: bus pointer | |
690 | * @port: port to write | |
691 | * @val: value to write | |
692 | * @size: number of bytes to write from @val | |
693 | * | |
694 | * Simply writes @size bytes of @val to @port. | |
695 | */ | |
a72391e4 | 696 | int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) |
1da177e4 | 697 | { |
408045af | 698 | int ret = size; |
1da177e4 LT |
699 | |
700 | switch (size) { | |
701 | case 1: | |
702 | outb(val, port); | |
703 | break; | |
704 | case 2: | |
705 | outw(val, port); | |
706 | break; | |
707 | case 4: | |
708 | outl(val, port); | |
709 | break; | |
710 | default: | |
711 | ret = -EINVAL; | |
712 | break; | |
713 | } | |
714 | ||
715 | return ret; | |
716 | } | |
717 | ||
3efe2d84 MW |
718 | /* It's defined in drivers/pci/pci.c */ |
719 | extern u8 pci_cache_line_size; | |
720 | ||
1da177e4 | 721 | /** |
3efe2d84 | 722 | * set_pci_cacheline_size - determine cacheline size for PCI devices |
1da177e4 LT |
723 | * |
724 | * We want to use the line-size of the outer-most cache. We assume | |
725 | * that this line-size is the same for all CPUs. | |
726 | * | |
727 | * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). | |
1da177e4 | 728 | */ |
3efe2d84 | 729 | static void __init set_pci_cacheline_size(void) |
1da177e4 | 730 | { |
e088a4ad MW |
731 | unsigned long levels, unique_caches; |
732 | long status; | |
1da177e4 | 733 | pal_cache_config_info_t cci; |
1da177e4 LT |
734 | |
735 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
736 | if (status != 0) { | |
3efe2d84 | 737 | printk(KERN_ERR "%s: ia64_pal_cache_summary() failed " |
d4ed8084 | 738 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 739 | return; |
1da177e4 LT |
740 | } |
741 | ||
3efe2d84 MW |
742 | status = ia64_pal_cache_config_info(levels - 1, |
743 | /* cache_type (data_or_unified)= */ 2, &cci); | |
1da177e4 | 744 | if (status != 0) { |
3efe2d84 | 745 | printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed " |
d4ed8084 | 746 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 747 | return; |
1da177e4 | 748 | } |
3efe2d84 | 749 | pci_cache_line_size = (1 << cci.pcci_line_size) / 4; |
1da177e4 LT |
750 | } |
751 | ||
175add19 JK |
752 | u64 ia64_dma_get_required_mask(struct device *dev) |
753 | { | |
754 | u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT); | |
755 | u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT)); | |
756 | u64 mask; | |
757 | ||
758 | if (!high_totalram) { | |
759 | /* convert to mask just covering totalram */ | |
760 | low_totalram = (1 << (fls(low_totalram) - 1)); | |
761 | low_totalram += low_totalram - 1; | |
762 | mask = low_totalram; | |
763 | } else { | |
764 | high_totalram = (1 << (fls(high_totalram) - 1)); | |
765 | high_totalram += high_totalram - 1; | |
766 | mask = (((u64)high_totalram) << 32) + 0xffffffff; | |
767 | } | |
768 | return mask; | |
769 | } | |
770 | EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask); | |
771 | ||
772 | u64 dma_get_required_mask(struct device *dev) | |
773 | { | |
774 | return platform_dma_get_required_mask(dev); | |
775 | } | |
776 | EXPORT_SYMBOL_GPL(dma_get_required_mask); | |
777 | ||
3efe2d84 MW |
778 | static int __init pcibios_init(void) |
779 | { | |
780 | set_pci_cacheline_size(); | |
781 | return 0; | |
1da177e4 | 782 | } |
3efe2d84 MW |
783 | |
784 | subsys_initcall(pcibios_init); |