Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * pci.c - Low-Level PCI Access in IA-64 | |
3 | * | |
4 | * Derived from bios32.c of i386 tree. | |
5 | * | |
6 | * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
9 | * Copyright (C) 2004 Silicon Graphics, Inc. | |
10 | * | |
11 | * Note: Above list of copyright holders is incomplete... | |
12 | */ | |
1da177e4 LT |
13 | |
14 | #include <linux/acpi.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/smp_lock.h> | |
22 | #include <linux/spinlock.h> | |
23 | ||
24 | #include <asm/machvec.h> | |
25 | #include <asm/page.h> | |
1da177e4 LT |
26 | #include <asm/system.h> |
27 | #include <asm/io.h> | |
28 | #include <asm/sal.h> | |
29 | #include <asm/smp.h> | |
30 | #include <asm/irq.h> | |
31 | #include <asm/hw_irq.h> | |
32 | ||
1da177e4 LT |
33 | /* |
34 | * Low-level SAL-based PCI configuration access functions. Note that SAL | |
35 | * calls are already serialized (via sal_lock), so we don't need another | |
36 | * synchronization mechanism here. | |
37 | */ | |
38 | ||
39 | #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ | |
40 | (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) | |
41 | ||
42 | /* SAL 3.2 adds support for extended config space. */ | |
43 | ||
44 | #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ | |
45 | (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) | |
46 | ||
47 | static int | |
48 | pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn, | |
49 | int reg, int len, u32 *value) | |
50 | { | |
51 | u64 addr, data = 0; | |
52 | int mode, result; | |
53 | ||
54 | if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
55 | return -EINVAL; | |
56 | ||
57 | if ((seg | reg) <= 255) { | |
58 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
59 | mode = 0; | |
60 | } else { | |
61 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); | |
62 | mode = 1; | |
63 | } | |
64 | result = ia64_sal_pci_config_read(addr, mode, len, &data); | |
65 | if (result != 0) | |
66 | return -EINVAL; | |
67 | ||
68 | *value = (u32) data; | |
69 | return 0; | |
70 | } | |
71 | ||
72 | static int | |
73 | pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn, | |
74 | int reg, int len, u32 value) | |
75 | { | |
76 | u64 addr; | |
77 | int mode, result; | |
78 | ||
79 | if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
80 | return -EINVAL; | |
81 | ||
82 | if ((seg | reg) <= 255) { | |
83 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
84 | mode = 0; | |
85 | } else { | |
86 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); | |
87 | mode = 1; | |
88 | } | |
89 | result = ia64_sal_pci_config_write(addr, mode, len, value); | |
90 | if (result != 0) | |
91 | return -EINVAL; | |
92 | return 0; | |
93 | } | |
94 | ||
95 | static struct pci_raw_ops pci_sal_ops = { | |
4f41d5a4 | 96 | .read = pci_sal_read, |
1da177e4 LT |
97 | .write = pci_sal_write |
98 | }; | |
99 | ||
100 | struct pci_raw_ops *raw_pci_ops = &pci_sal_ops; | |
101 | ||
102 | static int | |
103 | pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) | |
104 | { | |
105 | return raw_pci_ops->read(pci_domain_nr(bus), bus->number, | |
106 | devfn, where, size, value); | |
107 | } | |
108 | ||
109 | static int | |
110 | pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) | |
111 | { | |
112 | return raw_pci_ops->write(pci_domain_nr(bus), bus->number, | |
113 | devfn, where, size, value); | |
114 | } | |
115 | ||
116 | struct pci_ops pci_root_ops = { | |
117 | .read = pci_read, | |
118 | .write = pci_write, | |
119 | }; | |
120 | ||
1da177e4 LT |
121 | /* Called by ACPI when it finds a new root bus. */ |
122 | ||
123 | static struct pci_controller * __devinit | |
124 | alloc_pci_controller (int seg) | |
125 | { | |
126 | struct pci_controller *controller; | |
127 | ||
128 | controller = kmalloc(sizeof(*controller), GFP_KERNEL); | |
129 | if (!controller) | |
130 | return NULL; | |
131 | ||
132 | memset(controller, 0, sizeof(*controller)); | |
133 | controller->segment = seg; | |
514604c6 | 134 | controller->node = -1; |
1da177e4 LT |
135 | return controller; |
136 | } | |
137 | ||
4f41d5a4 BH |
138 | struct pci_root_info { |
139 | struct pci_controller *controller; | |
140 | char *name; | |
141 | }; | |
142 | ||
143 | static unsigned int | |
144 | new_space (u64 phys_base, int sparse) | |
1da177e4 | 145 | { |
4f41d5a4 | 146 | u64 mmio_base; |
1da177e4 LT |
147 | int i; |
148 | ||
4f41d5a4 BH |
149 | if (phys_base == 0) |
150 | return 0; /* legacy I/O port space */ | |
1da177e4 | 151 | |
4f41d5a4 | 152 | mmio_base = (u64) ioremap(phys_base, 0); |
1da177e4 | 153 | for (i = 0; i < num_io_spaces; i++) |
4f41d5a4 | 154 | if (io_space[i].mmio_base == mmio_base && |
1da177e4 | 155 | io_space[i].sparse == sparse) |
4f41d5a4 | 156 | return i; |
1da177e4 LT |
157 | |
158 | if (num_io_spaces == MAX_IO_SPACES) { | |
4f41d5a4 BH |
159 | printk(KERN_ERR "PCI: Too many IO port spaces " |
160 | "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES); | |
1da177e4 LT |
161 | return ~0; |
162 | } | |
163 | ||
164 | i = num_io_spaces++; | |
4f41d5a4 | 165 | io_space[i].mmio_base = mmio_base; |
1da177e4 LT |
166 | io_space[i].sparse = sparse; |
167 | ||
4f41d5a4 BH |
168 | return i; |
169 | } | |
170 | ||
171 | static u64 __devinit | |
172 | add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr) | |
173 | { | |
174 | struct resource *resource; | |
175 | char *name; | |
176 | u64 base, min, max, base_port; | |
177 | unsigned int sparse = 0, space_nr, len; | |
178 | ||
179 | resource = kzalloc(sizeof(*resource), GFP_KERNEL); | |
180 | if (!resource) { | |
181 | printk(KERN_ERR "PCI: No memory for %s I/O port space\n", | |
182 | info->name); | |
183 | goto out; | |
184 | } | |
185 | ||
186 | len = strlen(info->name) + 32; | |
187 | name = kzalloc(len, GFP_KERNEL); | |
188 | if (!name) { | |
189 | printk(KERN_ERR "PCI: No memory for %s I/O port space name\n", | |
190 | info->name); | |
191 | goto free_resource; | |
192 | } | |
193 | ||
50eca3eb | 194 | min = addr->minimum; |
4f41d5a4 | 195 | max = min + addr->address_length - 1; |
0897831b | 196 | if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) |
4f41d5a4 BH |
197 | sparse = 1; |
198 | ||
50eca3eb | 199 | space_nr = new_space(addr->translation_offset, sparse); |
4f41d5a4 BH |
200 | if (space_nr == ~0) |
201 | goto free_name; | |
202 | ||
203 | base = __pa(io_space[space_nr].mmio_base); | |
204 | base_port = IO_SPACE_BASE(space_nr); | |
205 | snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name, | |
206 | base_port + min, base_port + max); | |
207 | ||
208 | /* | |
209 | * The SDM guarantees the legacy 0-64K space is sparse, but if the | |
210 | * mapping is done by the processor (not the bridge), ACPI may not | |
211 | * mark it as sparse. | |
212 | */ | |
213 | if (space_nr == 0) | |
214 | sparse = 1; | |
215 | ||
216 | resource->name = name; | |
217 | resource->flags = IORESOURCE_MEM; | |
218 | resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); | |
219 | resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); | |
220 | insert_resource(&iomem_resource, resource); | |
221 | ||
222 | return base_port; | |
223 | ||
224 | free_name: | |
225 | kfree(name); | |
226 | free_resource: | |
227 | kfree(resource); | |
228 | out: | |
229 | return ~0; | |
1da177e4 LT |
230 | } |
231 | ||
463eb297 BH |
232 | static acpi_status __devinit resource_to_window(struct acpi_resource *resource, |
233 | struct acpi_resource_address64 *addr) | |
234 | { | |
235 | acpi_status status; | |
236 | ||
237 | /* | |
238 | * We're only interested in _CRS descriptors that are | |
239 | * - address space descriptors for memory or I/O space | |
240 | * - non-zero size | |
241 | * - producers, i.e., the address space is routed downstream, | |
242 | * not consumed by the bridge itself | |
243 | */ | |
244 | status = acpi_resource_to_address64(resource, addr); | |
245 | if (ACPI_SUCCESS(status) && | |
246 | (addr->resource_type == ACPI_MEMORY_RANGE || | |
247 | addr->resource_type == ACPI_IO_RANGE) && | |
248 | addr->address_length && | |
249 | addr->producer_consumer == ACPI_PRODUCER) | |
250 | return AE_OK; | |
251 | ||
252 | return AE_ERROR; | |
253 | } | |
254 | ||
1da177e4 LT |
255 | static acpi_status __devinit |
256 | count_window (struct acpi_resource *resource, void *data) | |
257 | { | |
258 | unsigned int *windows = (unsigned int *) data; | |
259 | struct acpi_resource_address64 addr; | |
260 | acpi_status status; | |
261 | ||
463eb297 | 262 | status = resource_to_window(resource, &addr); |
1da177e4 | 263 | if (ACPI_SUCCESS(status)) |
463eb297 | 264 | (*windows)++; |
1da177e4 LT |
265 | |
266 | return AE_OK; | |
267 | } | |
268 | ||
1da177e4 LT |
269 | static __devinit acpi_status add_window(struct acpi_resource *res, void *data) |
270 | { | |
271 | struct pci_root_info *info = data; | |
272 | struct pci_window *window; | |
273 | struct acpi_resource_address64 addr; | |
274 | acpi_status status; | |
275 | unsigned long flags, offset = 0; | |
276 | struct resource *root; | |
277 | ||
463eb297 BH |
278 | /* Return AE_OK for non-window resources to keep scanning for more */ |
279 | status = resource_to_window(res, &addr); | |
1da177e4 LT |
280 | if (!ACPI_SUCCESS(status)) |
281 | return AE_OK; | |
282 | ||
1da177e4 LT |
283 | if (addr.resource_type == ACPI_MEMORY_RANGE) { |
284 | flags = IORESOURCE_MEM; | |
285 | root = &iomem_resource; | |
50eca3eb | 286 | offset = addr.translation_offset; |
1da177e4 LT |
287 | } else if (addr.resource_type == ACPI_IO_RANGE) { |
288 | flags = IORESOURCE_IO; | |
289 | root = &ioport_resource; | |
4f41d5a4 | 290 | offset = add_io_space(info, &addr); |
1da177e4 LT |
291 | if (offset == ~0) |
292 | return AE_OK; | |
293 | } else | |
294 | return AE_OK; | |
295 | ||
296 | window = &info->controller->window[info->controller->windows++]; | |
297 | window->resource.name = info->name; | |
298 | window->resource.flags = flags; | |
50eca3eb | 299 | window->resource.start = addr.minimum + offset; |
4f41d5a4 | 300 | window->resource.end = window->resource.start + addr.address_length - 1; |
1da177e4 LT |
301 | window->resource.child = NULL; |
302 | window->offset = offset; | |
303 | ||
304 | if (insert_resource(root, &window->resource)) { | |
305 | printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n", | |
306 | window->resource.start, window->resource.end, | |
307 | root->name, info->name); | |
308 | } | |
309 | ||
310 | return AE_OK; | |
311 | } | |
312 | ||
313 | static void __devinit | |
314 | pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) | |
315 | { | |
316 | int i, j; | |
317 | ||
318 | j = 0; | |
319 | for (i = 0; i < ctrl->windows; i++) { | |
320 | struct resource *res = &ctrl->window[i].resource; | |
321 | /* HP's firmware has a hack to work around a Windows bug. | |
322 | * Ignore these tiny memory ranges */ | |
323 | if ((res->flags & IORESOURCE_MEM) && | |
324 | (res->end - res->start < 16)) | |
325 | continue; | |
326 | if (j >= PCI_BUS_NUM_RESOURCES) { | |
327 | printk("Ignoring range [%lx-%lx] (%lx)\n", res->start, | |
328 | res->end, res->flags); | |
329 | continue; | |
330 | } | |
331 | bus->resource[j++] = res; | |
332 | } | |
333 | } | |
334 | ||
335 | struct pci_bus * __devinit | |
336 | pci_acpi_scan_root(struct acpi_device *device, int domain, int bus) | |
337 | { | |
338 | struct pci_root_info info; | |
339 | struct pci_controller *controller; | |
340 | unsigned int windows = 0; | |
341 | struct pci_bus *pbus; | |
342 | char *name; | |
514604c6 | 343 | int pxm; |
1da177e4 LT |
344 | |
345 | controller = alloc_pci_controller(domain); | |
346 | if (!controller) | |
347 | goto out1; | |
348 | ||
349 | controller->acpi_handle = device->handle; | |
350 | ||
514604c6 CL |
351 | pxm = acpi_get_pxm(controller->acpi_handle); |
352 | #ifdef CONFIG_NUMA | |
353 | if (pxm >= 0) | |
762834e8 | 354 | controller->node = pxm_to_node(pxm); |
514604c6 CL |
355 | #endif |
356 | ||
1da177e4 LT |
357 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, |
358 | &windows); | |
514604c6 CL |
359 | controller->window = kmalloc_node(sizeof(*controller->window) * windows, |
360 | GFP_KERNEL, controller->node); | |
1da177e4 LT |
361 | if (!controller->window) |
362 | goto out2; | |
363 | ||
364 | name = kmalloc(16, GFP_KERNEL); | |
365 | if (!name) | |
366 | goto out3; | |
367 | ||
368 | sprintf(name, "PCI Bus %04x:%02x", domain, bus); | |
369 | info.controller = controller; | |
370 | info.name = name; | |
371 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window, | |
372 | &info); | |
373 | ||
c431ada4 | 374 | pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller); |
1da177e4 LT |
375 | if (pbus) |
376 | pcibios_setup_root_windows(pbus, controller); | |
377 | ||
378 | return pbus; | |
379 | ||
380 | out3: | |
381 | kfree(controller->window); | |
382 | out2: | |
383 | kfree(controller); | |
384 | out1: | |
385 | return NULL; | |
386 | } | |
387 | ||
388 | void pcibios_resource_to_bus(struct pci_dev *dev, | |
389 | struct pci_bus_region *region, struct resource *res) | |
390 | { | |
391 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
392 | unsigned long offset = 0; | |
393 | int i; | |
394 | ||
395 | for (i = 0; i < controller->windows; i++) { | |
396 | struct pci_window *window = &controller->window[i]; | |
397 | if (!(window->resource.flags & res->flags)) | |
398 | continue; | |
399 | if (window->resource.start > res->start) | |
400 | continue; | |
401 | if (window->resource.end < res->end) | |
402 | continue; | |
403 | offset = window->offset; | |
404 | break; | |
405 | } | |
406 | ||
407 | region->start = res->start - offset; | |
408 | region->end = res->end - offset; | |
409 | } | |
410 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
411 | ||
412 | void pcibios_bus_to_resource(struct pci_dev *dev, | |
413 | struct resource *res, struct pci_bus_region *region) | |
414 | { | |
415 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
416 | unsigned long offset = 0; | |
417 | int i; | |
418 | ||
419 | for (i = 0; i < controller->windows; i++) { | |
420 | struct pci_window *window = &controller->window[i]; | |
421 | if (!(window->resource.flags & res->flags)) | |
422 | continue; | |
423 | if (window->resource.start - window->offset > region->start) | |
424 | continue; | |
425 | if (window->resource.end - window->offset < region->end) | |
426 | continue; | |
427 | offset = window->offset; | |
428 | break; | |
429 | } | |
430 | ||
431 | res->start = region->start + offset; | |
432 | res->end = region->end + offset; | |
433 | } | |
41290c14 | 434 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 435 | |
71c3511c RS |
436 | static int __devinit is_valid_resource(struct pci_dev *dev, int idx) |
437 | { | |
438 | unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; | |
439 | struct resource *devr = &dev->resource[idx]; | |
440 | ||
441 | if (!dev->bus) | |
442 | return 0; | |
443 | for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) { | |
444 | struct resource *busr = dev->bus->resource[i]; | |
445 | ||
446 | if (!busr || ((busr->flags ^ devr->flags) & type_mask)) | |
447 | continue; | |
448 | if ((devr->start) && (devr->start >= busr->start) && | |
449 | (devr->end <= busr->end)) | |
450 | return 1; | |
451 | } | |
452 | return 0; | |
453 | } | |
454 | ||
7b9c8ba2 KK |
455 | static void __devinit |
456 | pcibios_fixup_resources(struct pci_dev *dev, int start, int limit) | |
1da177e4 LT |
457 | { |
458 | struct pci_bus_region region; | |
459 | int i; | |
1da177e4 | 460 | |
7b9c8ba2 | 461 | for (i = start; i < limit; i++) { |
1da177e4 LT |
462 | if (!dev->resource[i].flags) |
463 | continue; | |
464 | region.start = dev->resource[i].start; | |
465 | region.end = dev->resource[i].end; | |
466 | pcibios_bus_to_resource(dev, &dev->resource[i], ®ion); | |
71c3511c RS |
467 | if ((is_valid_resource(dev, i))) |
468 | pci_claim_resource(dev, i); | |
1da177e4 LT |
469 | } |
470 | } | |
471 | ||
7b9c8ba2 KK |
472 | static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) |
473 | { | |
474 | pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES); | |
475 | } | |
476 | ||
477 | static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev) | |
478 | { | |
479 | pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES); | |
480 | } | |
481 | ||
1da177e4 LT |
482 | /* |
483 | * Called after each bus is probed, but before its children are examined. | |
484 | */ | |
485 | void __devinit | |
486 | pcibios_fixup_bus (struct pci_bus *b) | |
487 | { | |
488 | struct pci_dev *dev; | |
489 | ||
f7d473d9 RS |
490 | if (b->self) { |
491 | pci_read_bridge_bases(b); | |
7b9c8ba2 | 492 | pcibios_fixup_bridge_resources(b->self); |
f7d473d9 | 493 | } |
1da177e4 LT |
494 | list_for_each_entry(dev, &b->devices, bus_list) |
495 | pcibios_fixup_device_resources(dev); | |
496 | ||
497 | return; | |
498 | } | |
499 | ||
500 | void __devinit | |
501 | pcibios_update_irq (struct pci_dev *dev, int irq) | |
502 | { | |
503 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
504 | ||
505 | /* ??? FIXME -- record old value for shutdown. */ | |
506 | } | |
507 | ||
508 | static inline int | |
509 | pcibios_enable_resources (struct pci_dev *dev, int mask) | |
510 | { | |
511 | u16 cmd, old_cmd; | |
512 | int idx; | |
513 | struct resource *r; | |
fab3fb0a | 514 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM; |
1da177e4 LT |
515 | |
516 | if (!dev) | |
517 | return -EINVAL; | |
518 | ||
519 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
520 | old_cmd = cmd; | |
fab3fb0a | 521 | for (idx=0; idx<PCI_NUM_RESOURCES; idx++) { |
1da177e4 LT |
522 | /* Only set up the desired resources. */ |
523 | if (!(mask & (1 << idx))) | |
524 | continue; | |
525 | ||
526 | r = &dev->resource[idx]; | |
fab3fb0a RS |
527 | if (!(r->flags & type_mask)) |
528 | continue; | |
529 | if ((idx == PCI_ROM_RESOURCE) && | |
530 | (!(r->flags & IORESOURCE_ROM_ENABLE))) | |
531 | continue; | |
1da177e4 LT |
532 | if (!r->start && r->end) { |
533 | printk(KERN_ERR | |
534 | "PCI: Device %s not available because of resource collisions\n", | |
535 | pci_name(dev)); | |
536 | return -EINVAL; | |
537 | } | |
538 | if (r->flags & IORESOURCE_IO) | |
539 | cmd |= PCI_COMMAND_IO; | |
540 | if (r->flags & IORESOURCE_MEM) | |
541 | cmd |= PCI_COMMAND_MEMORY; | |
542 | } | |
1da177e4 LT |
543 | if (cmd != old_cmd) { |
544 | printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); | |
545 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
546 | } | |
547 | return 0; | |
548 | } | |
549 | ||
550 | int | |
551 | pcibios_enable_device (struct pci_dev *dev, int mask) | |
552 | { | |
553 | int ret; | |
554 | ||
555 | ret = pcibios_enable_resources(dev, mask); | |
556 | if (ret < 0) | |
557 | return ret; | |
558 | ||
559 | return acpi_pci_irq_enable(dev); | |
560 | } | |
561 | ||
1da177e4 LT |
562 | void |
563 | pcibios_disable_device (struct pci_dev *dev) | |
564 | { | |
565 | acpi_pci_irq_disable(dev); | |
566 | } | |
1da177e4 LT |
567 | |
568 | void | |
569 | pcibios_align_resource (void *data, struct resource *res, | |
e31dd6e4 | 570 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
571 | { |
572 | } | |
573 | ||
574 | /* | |
575 | * PCI BIOS setup, always defaults to SAL interface | |
576 | */ | |
577 | char * __init | |
578 | pcibios_setup (char *str) | |
579 | { | |
ac311ac2 | 580 | return str; |
1da177e4 LT |
581 | } |
582 | ||
583 | int | |
584 | pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
585 | enum pci_mmap_state mmap_state, int write_combine) | |
586 | { | |
587 | /* | |
588 | * I/O space cannot be accessed via normal processor loads and | |
589 | * stores on this platform. | |
590 | */ | |
591 | if (mmap_state == pci_mmap_io) | |
592 | /* | |
593 | * XXX we could relax this for I/O spaces for which ACPI | |
594 | * indicates that the space is 1-to-1 mapped. But at the | |
595 | * moment, we don't support multiple PCI address spaces and | |
596 | * the legacy I/O space is not 1-to-1 mapped, so this is moot. | |
597 | */ | |
598 | return -EINVAL; | |
599 | ||
600 | /* | |
601 | * Leave vm_pgoff as-is, the PCI space address is the physical | |
602 | * address on this platform. | |
603 | */ | |
1da177e4 LT |
604 | if (write_combine && efi_range_is_wc(vma->vm_start, |
605 | vma->vm_end - vma->vm_start)) | |
606 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
607 | else | |
608 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
609 | ||
610 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
611 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
612 | return -EAGAIN; | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | /** | |
618 | * ia64_pci_get_legacy_mem - generic legacy mem routine | |
619 | * @bus: bus to get legacy memory base address for | |
620 | * | |
621 | * Find the base of legacy memory for @bus. This is typically the first | |
622 | * megabyte of bus address space for @bus or is simply 0 on platforms whose | |
623 | * chipsets support legacy I/O and memory routing. Returns the base address | |
624 | * or an error pointer if an error occurred. | |
625 | * | |
626 | * This is the ia64 generic version of this routine. Other platforms | |
627 | * are free to override it with a machine vector. | |
628 | */ | |
629 | char *ia64_pci_get_legacy_mem(struct pci_bus *bus) | |
630 | { | |
631 | return (char *)__IA64_UNCACHED_OFFSET; | |
632 | } | |
633 | ||
634 | /** | |
635 | * pci_mmap_legacy_page_range - map legacy memory space to userland | |
636 | * @bus: bus whose legacy space we're mapping | |
637 | * @vma: vma passed in by mmap | |
638 | * | |
639 | * Map legacy memory space for this device back to userspace using a machine | |
640 | * vector to get the base address. | |
641 | */ | |
642 | int | |
643 | pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma) | |
644 | { | |
32e62c63 BH |
645 | unsigned long size = vma->vm_end - vma->vm_start; |
646 | pgprot_t prot; | |
1da177e4 LT |
647 | char *addr; |
648 | ||
32e62c63 BH |
649 | /* |
650 | * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt | |
651 | * for more details. | |
652 | */ | |
653 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff << PAGE_SHIFT, size)) | |
654 | return -EINVAL; | |
655 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
656 | vma->vm_page_prot); | |
657 | if (pgprot_val(prot) != pgprot_val(pgprot_noncached(vma->vm_page_prot))) | |
658 | return -EINVAL; | |
659 | ||
1da177e4 LT |
660 | addr = pci_get_legacy_mem(bus); |
661 | if (IS_ERR(addr)) | |
662 | return PTR_ERR(addr); | |
663 | ||
664 | vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; | |
32e62c63 | 665 | vma->vm_page_prot = prot; |
1da177e4 LT |
666 | |
667 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
32e62c63 | 668 | size, vma->vm_page_prot)) |
1da177e4 LT |
669 | return -EAGAIN; |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
674 | /** | |
675 | * ia64_pci_legacy_read - read from legacy I/O space | |
676 | * @bus: bus to read | |
677 | * @port: legacy port value | |
678 | * @val: caller allocated storage for returned value | |
679 | * @size: number of bytes to read | |
680 | * | |
681 | * Simply reads @size bytes from @port and puts the result in @val. | |
682 | * | |
683 | * Again, this (and the write routine) are generic versions that can be | |
684 | * overridden by the platform. This is necessary on platforms that don't | |
685 | * support legacy I/O routing or that hard fail on legacy I/O timeouts. | |
686 | */ | |
687 | int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
688 | { | |
689 | int ret = size; | |
690 | ||
691 | switch (size) { | |
692 | case 1: | |
693 | *val = inb(port); | |
694 | break; | |
695 | case 2: | |
696 | *val = inw(port); | |
697 | break; | |
698 | case 4: | |
699 | *val = inl(port); | |
700 | break; | |
701 | default: | |
702 | ret = -EINVAL; | |
703 | break; | |
704 | } | |
705 | ||
706 | return ret; | |
707 | } | |
708 | ||
709 | /** | |
710 | * ia64_pci_legacy_write - perform a legacy I/O write | |
711 | * @bus: bus pointer | |
712 | * @port: port to write | |
713 | * @val: value to write | |
714 | * @size: number of bytes to write from @val | |
715 | * | |
716 | * Simply writes @size bytes of @val to @port. | |
717 | */ | |
a72391e4 | 718 | int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) |
1da177e4 | 719 | { |
408045af | 720 | int ret = size; |
1da177e4 LT |
721 | |
722 | switch (size) { | |
723 | case 1: | |
724 | outb(val, port); | |
725 | break; | |
726 | case 2: | |
727 | outw(val, port); | |
728 | break; | |
729 | case 4: | |
730 | outl(val, port); | |
731 | break; | |
732 | default: | |
733 | ret = -EINVAL; | |
734 | break; | |
735 | } | |
736 | ||
737 | return ret; | |
738 | } | |
739 | ||
740 | /** | |
741 | * pci_cacheline_size - determine cacheline size for PCI devices | |
742 | * @dev: void | |
743 | * | |
744 | * We want to use the line-size of the outer-most cache. We assume | |
745 | * that this line-size is the same for all CPUs. | |
746 | * | |
747 | * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). | |
748 | * | |
749 | * RETURNS: An appropriate -ERRNO error value on eror, or zero for success. | |
750 | */ | |
751 | static unsigned long | |
752 | pci_cacheline_size (void) | |
753 | { | |
754 | u64 levels, unique_caches; | |
755 | s64 status; | |
756 | pal_cache_config_info_t cci; | |
757 | static u8 cacheline_size; | |
758 | ||
759 | if (cacheline_size) | |
760 | return cacheline_size; | |
761 | ||
762 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
763 | if (status != 0) { | |
764 | printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", | |
765 | __FUNCTION__, status); | |
766 | return SMP_CACHE_BYTES; | |
767 | } | |
768 | ||
769 | status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2, | |
770 | &cci); | |
771 | if (status != 0) { | |
772 | printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n", | |
773 | __FUNCTION__, status); | |
774 | return SMP_CACHE_BYTES; | |
775 | } | |
776 | cacheline_size = 1 << cci.pcci_line_size; | |
777 | return cacheline_size; | |
778 | } | |
779 | ||
780 | /** | |
781 | * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi() | |
782 | * @dev: the PCI device for which MWI is enabled | |
783 | * | |
784 | * For ia64, we can get the cacheline sizes from PAL. | |
785 | * | |
786 | * RETURNS: An appropriate -ERRNO error value on eror, or zero for success. | |
787 | */ | |
788 | int | |
789 | pcibios_prep_mwi (struct pci_dev *dev) | |
790 | { | |
791 | unsigned long desired_linesize, current_linesize; | |
792 | int rc = 0; | |
793 | u8 pci_linesize; | |
794 | ||
795 | desired_linesize = pci_cacheline_size(); | |
796 | ||
797 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize); | |
798 | current_linesize = 4 * pci_linesize; | |
799 | if (desired_linesize != current_linesize) { | |
800 | printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,", | |
801 | pci_name(dev), current_linesize); | |
802 | if (current_linesize > desired_linesize) { | |
803 | printk(" expected %lu bytes instead\n", desired_linesize); | |
804 | rc = -EINVAL; | |
805 | } else { | |
806 | printk(" correcting to %lu\n", desired_linesize); | |
807 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4); | |
808 | } | |
809 | } | |
810 | return rc; | |
811 | } | |
812 | ||
813 | int pci_vector_resources(int last, int nr_released) | |
814 | { | |
815 | int count = nr_released; | |
816 | ||
4f41d5a4 | 817 | count += (IA64_LAST_DEVICE_VECTOR - last); |
1da177e4 LT |
818 | |
819 | return count; | |
820 | } |