Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.c - Low-Level PCI Access in IA-64 | |
3 | * | |
4 | * Derived from bios32.c of i386 tree. | |
5 | * | |
6 | * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
9 | * Copyright (C) 2004 Silicon Graphics, Inc. | |
10 | * | |
11 | * Note: Above list of copyright holders is incomplete... | |
12 | */ | |
1da177e4 LT |
13 | |
14 | #include <linux/acpi.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/slab.h> | |
1da177e4 LT |
21 | #include <linux/spinlock.h> |
22 | ||
23 | #include <asm/machvec.h> | |
24 | #include <asm/page.h> | |
1da177e4 LT |
25 | #include <asm/system.h> |
26 | #include <asm/io.h> | |
27 | #include <asm/sal.h> | |
28 | #include <asm/smp.h> | |
29 | #include <asm/irq.h> | |
30 | #include <asm/hw_irq.h> | |
31 | ||
1da177e4 LT |
32 | /* |
33 | * Low-level SAL-based PCI configuration access functions. Note that SAL | |
34 | * calls are already serialized (via sal_lock), so we don't need another | |
35 | * synchronization mechanism here. | |
36 | */ | |
37 | ||
38 | #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ | |
39 | (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) | |
40 | ||
41 | /* SAL 3.2 adds support for extended config space. */ | |
42 | ||
43 | #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ | |
44 | (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) | |
45 | ||
b6ce068a | 46 | int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
47 | int reg, int len, u32 *value) |
48 | { | |
49 | u64 addr, data = 0; | |
50 | int mode, result; | |
51 | ||
52 | if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
53 | return -EINVAL; | |
54 | ||
55 | if ((seg | reg) <= 255) { | |
56 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
57 | mode = 0; | |
58 | } else { | |
59 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); | |
60 | mode = 1; | |
61 | } | |
62 | result = ia64_sal_pci_config_read(addr, mode, len, &data); | |
63 | if (result != 0) | |
64 | return -EINVAL; | |
65 | ||
66 | *value = (u32) data; | |
67 | return 0; | |
68 | } | |
69 | ||
b6ce068a | 70 | int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
71 | int reg, int len, u32 value) |
72 | { | |
73 | u64 addr; | |
74 | int mode, result; | |
75 | ||
76 | if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
77 | return -EINVAL; | |
78 | ||
79 | if ((seg | reg) <= 255) { | |
80 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
81 | mode = 0; | |
82 | } else { | |
83 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); | |
84 | mode = 1; | |
85 | } | |
86 | result = ia64_sal_pci_config_write(addr, mode, len, value); | |
87 | if (result != 0) | |
88 | return -EINVAL; | |
89 | return 0; | |
90 | } | |
91 | ||
b6ce068a MW |
92 | static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, |
93 | int size, u32 *value) | |
1da177e4 | 94 | { |
b6ce068a | 95 | return raw_pci_read(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
96 | devfn, where, size, value); |
97 | } | |
98 | ||
b6ce068a MW |
99 | static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, |
100 | int size, u32 value) | |
1da177e4 | 101 | { |
b6ce068a | 102 | return raw_pci_write(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
103 | devfn, where, size, value); |
104 | } | |
105 | ||
106 | struct pci_ops pci_root_ops = { | |
107 | .read = pci_read, | |
108 | .write = pci_write, | |
109 | }; | |
110 | ||
1da177e4 LT |
111 | /* Called by ACPI when it finds a new root bus. */ |
112 | ||
113 | static struct pci_controller * __devinit | |
114 | alloc_pci_controller (int seg) | |
115 | { | |
116 | struct pci_controller *controller; | |
117 | ||
52fd9108 | 118 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); |
1da177e4 LT |
119 | if (!controller) |
120 | return NULL; | |
121 | ||
1da177e4 | 122 | controller->segment = seg; |
514604c6 | 123 | controller->node = -1; |
1da177e4 LT |
124 | return controller; |
125 | } | |
126 | ||
4f41d5a4 BH |
127 | struct pci_root_info { |
128 | struct pci_controller *controller; | |
129 | char *name; | |
130 | }; | |
131 | ||
132 | static unsigned int | |
133 | new_space (u64 phys_base, int sparse) | |
1da177e4 | 134 | { |
4f41d5a4 | 135 | u64 mmio_base; |
1da177e4 LT |
136 | int i; |
137 | ||
4f41d5a4 BH |
138 | if (phys_base == 0) |
139 | return 0; /* legacy I/O port space */ | |
1da177e4 | 140 | |
4f41d5a4 | 141 | mmio_base = (u64) ioremap(phys_base, 0); |
1da177e4 | 142 | for (i = 0; i < num_io_spaces; i++) |
4f41d5a4 | 143 | if (io_space[i].mmio_base == mmio_base && |
1da177e4 | 144 | io_space[i].sparse == sparse) |
4f41d5a4 | 145 | return i; |
1da177e4 LT |
146 | |
147 | if (num_io_spaces == MAX_IO_SPACES) { | |
4f41d5a4 BH |
148 | printk(KERN_ERR "PCI: Too many IO port spaces " |
149 | "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES); | |
1da177e4 LT |
150 | return ~0; |
151 | } | |
152 | ||
153 | i = num_io_spaces++; | |
4f41d5a4 | 154 | io_space[i].mmio_base = mmio_base; |
1da177e4 LT |
155 | io_space[i].sparse = sparse; |
156 | ||
4f41d5a4 BH |
157 | return i; |
158 | } | |
159 | ||
160 | static u64 __devinit | |
161 | add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr) | |
162 | { | |
163 | struct resource *resource; | |
164 | char *name; | |
165 | u64 base, min, max, base_port; | |
166 | unsigned int sparse = 0, space_nr, len; | |
167 | ||
168 | resource = kzalloc(sizeof(*resource), GFP_KERNEL); | |
169 | if (!resource) { | |
170 | printk(KERN_ERR "PCI: No memory for %s I/O port space\n", | |
171 | info->name); | |
172 | goto out; | |
173 | } | |
174 | ||
175 | len = strlen(info->name) + 32; | |
176 | name = kzalloc(len, GFP_KERNEL); | |
177 | if (!name) { | |
178 | printk(KERN_ERR "PCI: No memory for %s I/O port space name\n", | |
179 | info->name); | |
180 | goto free_resource; | |
181 | } | |
182 | ||
50eca3eb | 183 | min = addr->minimum; |
4f41d5a4 | 184 | max = min + addr->address_length - 1; |
0897831b | 185 | if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) |
4f41d5a4 BH |
186 | sparse = 1; |
187 | ||
50eca3eb | 188 | space_nr = new_space(addr->translation_offset, sparse); |
4f41d5a4 BH |
189 | if (space_nr == ~0) |
190 | goto free_name; | |
191 | ||
192 | base = __pa(io_space[space_nr].mmio_base); | |
193 | base_port = IO_SPACE_BASE(space_nr); | |
194 | snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name, | |
195 | base_port + min, base_port + max); | |
196 | ||
197 | /* | |
198 | * The SDM guarantees the legacy 0-64K space is sparse, but if the | |
199 | * mapping is done by the processor (not the bridge), ACPI may not | |
200 | * mark it as sparse. | |
201 | */ | |
202 | if (space_nr == 0) | |
203 | sparse = 1; | |
204 | ||
205 | resource->name = name; | |
206 | resource->flags = IORESOURCE_MEM; | |
207 | resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); | |
208 | resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); | |
209 | insert_resource(&iomem_resource, resource); | |
210 | ||
211 | return base_port; | |
212 | ||
213 | free_name: | |
214 | kfree(name); | |
215 | free_resource: | |
216 | kfree(resource); | |
217 | out: | |
218 | return ~0; | |
1da177e4 LT |
219 | } |
220 | ||
463eb297 BH |
221 | static acpi_status __devinit resource_to_window(struct acpi_resource *resource, |
222 | struct acpi_resource_address64 *addr) | |
223 | { | |
224 | acpi_status status; | |
225 | ||
226 | /* | |
227 | * We're only interested in _CRS descriptors that are | |
228 | * - address space descriptors for memory or I/O space | |
229 | * - non-zero size | |
230 | * - producers, i.e., the address space is routed downstream, | |
231 | * not consumed by the bridge itself | |
232 | */ | |
233 | status = acpi_resource_to_address64(resource, addr); | |
234 | if (ACPI_SUCCESS(status) && | |
235 | (addr->resource_type == ACPI_MEMORY_RANGE || | |
236 | addr->resource_type == ACPI_IO_RANGE) && | |
237 | addr->address_length && | |
238 | addr->producer_consumer == ACPI_PRODUCER) | |
239 | return AE_OK; | |
240 | ||
241 | return AE_ERROR; | |
242 | } | |
243 | ||
1da177e4 LT |
244 | static acpi_status __devinit |
245 | count_window (struct acpi_resource *resource, void *data) | |
246 | { | |
247 | unsigned int *windows = (unsigned int *) data; | |
248 | struct acpi_resource_address64 addr; | |
249 | acpi_status status; | |
250 | ||
463eb297 | 251 | status = resource_to_window(resource, &addr); |
1da177e4 | 252 | if (ACPI_SUCCESS(status)) |
463eb297 | 253 | (*windows)++; |
1da177e4 LT |
254 | |
255 | return AE_OK; | |
256 | } | |
257 | ||
1da177e4 LT |
258 | static __devinit acpi_status add_window(struct acpi_resource *res, void *data) |
259 | { | |
260 | struct pci_root_info *info = data; | |
261 | struct pci_window *window; | |
262 | struct acpi_resource_address64 addr; | |
263 | acpi_status status; | |
264 | unsigned long flags, offset = 0; | |
265 | struct resource *root; | |
266 | ||
463eb297 BH |
267 | /* Return AE_OK for non-window resources to keep scanning for more */ |
268 | status = resource_to_window(res, &addr); | |
1da177e4 LT |
269 | if (!ACPI_SUCCESS(status)) |
270 | return AE_OK; | |
271 | ||
1da177e4 LT |
272 | if (addr.resource_type == ACPI_MEMORY_RANGE) { |
273 | flags = IORESOURCE_MEM; | |
274 | root = &iomem_resource; | |
50eca3eb | 275 | offset = addr.translation_offset; |
1da177e4 LT |
276 | } else if (addr.resource_type == ACPI_IO_RANGE) { |
277 | flags = IORESOURCE_IO; | |
278 | root = &ioport_resource; | |
4f41d5a4 | 279 | offset = add_io_space(info, &addr); |
1da177e4 LT |
280 | if (offset == ~0) |
281 | return AE_OK; | |
282 | } else | |
283 | return AE_OK; | |
284 | ||
285 | window = &info->controller->window[info->controller->windows++]; | |
286 | window->resource.name = info->name; | |
287 | window->resource.flags = flags; | |
50eca3eb | 288 | window->resource.start = addr.minimum + offset; |
4f41d5a4 | 289 | window->resource.end = window->resource.start + addr.address_length - 1; |
1da177e4 LT |
290 | window->resource.child = NULL; |
291 | window->offset = offset; | |
292 | ||
293 | if (insert_resource(root, &window->resource)) { | |
294 | printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n", | |
295 | window->resource.start, window->resource.end, | |
296 | root->name, info->name); | |
297 | } | |
298 | ||
299 | return AE_OK; | |
300 | } | |
301 | ||
302 | static void __devinit | |
303 | pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) | |
304 | { | |
305 | int i, j; | |
306 | ||
307 | j = 0; | |
308 | for (i = 0; i < ctrl->windows; i++) { | |
309 | struct resource *res = &ctrl->window[i].resource; | |
310 | /* HP's firmware has a hack to work around a Windows bug. | |
311 | * Ignore these tiny memory ranges */ | |
312 | if ((res->flags & IORESOURCE_MEM) && | |
313 | (res->end - res->start < 16)) | |
314 | continue; | |
315 | if (j >= PCI_BUS_NUM_RESOURCES) { | |
316 | printk("Ignoring range [%lx-%lx] (%lx)\n", res->start, | |
317 | res->end, res->flags); | |
318 | continue; | |
319 | } | |
320 | bus->resource[j++] = res; | |
321 | } | |
322 | } | |
323 | ||
324 | struct pci_bus * __devinit | |
325 | pci_acpi_scan_root(struct acpi_device *device, int domain, int bus) | |
326 | { | |
1da177e4 LT |
327 | struct pci_controller *controller; |
328 | unsigned int windows = 0; | |
329 | struct pci_bus *pbus; | |
330 | char *name; | |
514604c6 | 331 | int pxm; |
1da177e4 LT |
332 | |
333 | controller = alloc_pci_controller(domain); | |
334 | if (!controller) | |
335 | goto out1; | |
336 | ||
337 | controller->acpi_handle = device->handle; | |
338 | ||
514604c6 CL |
339 | pxm = acpi_get_pxm(controller->acpi_handle); |
340 | #ifdef CONFIG_NUMA | |
341 | if (pxm >= 0) | |
762834e8 | 342 | controller->node = pxm_to_node(pxm); |
514604c6 CL |
343 | #endif |
344 | ||
1da177e4 LT |
345 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, |
346 | &windows); | |
a66aa704 | 347 | if (windows) { |
8a20fd52 LT |
348 | struct pci_root_info info; |
349 | ||
a66aa704 KK |
350 | controller->window = |
351 | kmalloc_node(sizeof(*controller->window) * windows, | |
352 | GFP_KERNEL, controller->node); | |
353 | if (!controller->window) | |
354 | goto out2; | |
1da177e4 | 355 | |
8a20fd52 LT |
356 | name = kmalloc(16, GFP_KERNEL); |
357 | if (!name) | |
358 | goto out3; | |
1da177e4 | 359 | |
8a20fd52 LT |
360 | sprintf(name, "PCI Bus %04x:%02x", domain, bus); |
361 | info.controller = controller; | |
362 | info.name = name; | |
363 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, | |
364 | add_window, &info); | |
365 | } | |
b87e81e5 | 366 | /* |
367 | * See arch/x86/pci/acpi.c. | |
368 | * The desired pci bus might already be scanned in a quirk. We | |
369 | * should handle the case here, but it appears that IA64 hasn't | |
370 | * such quirk. So we just ignore the case now. | |
371 | */ | |
c431ada4 | 372 | pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller); |
1da177e4 LT |
373 | if (pbus) |
374 | pcibios_setup_root_windows(pbus, controller); | |
375 | ||
376 | return pbus; | |
377 | ||
378 | out3: | |
379 | kfree(controller->window); | |
380 | out2: | |
381 | kfree(controller); | |
382 | out1: | |
383 | return NULL; | |
384 | } | |
385 | ||
386 | void pcibios_resource_to_bus(struct pci_dev *dev, | |
387 | struct pci_bus_region *region, struct resource *res) | |
388 | { | |
389 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
390 | unsigned long offset = 0; | |
391 | int i; | |
392 | ||
393 | for (i = 0; i < controller->windows; i++) { | |
394 | struct pci_window *window = &controller->window[i]; | |
395 | if (!(window->resource.flags & res->flags)) | |
396 | continue; | |
397 | if (window->resource.start > res->start) | |
398 | continue; | |
399 | if (window->resource.end < res->end) | |
400 | continue; | |
401 | offset = window->offset; | |
402 | break; | |
403 | } | |
404 | ||
405 | region->start = res->start - offset; | |
406 | region->end = res->end - offset; | |
407 | } | |
408 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
409 | ||
410 | void pcibios_bus_to_resource(struct pci_dev *dev, | |
411 | struct resource *res, struct pci_bus_region *region) | |
412 | { | |
413 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
414 | unsigned long offset = 0; | |
415 | int i; | |
416 | ||
417 | for (i = 0; i < controller->windows; i++) { | |
418 | struct pci_window *window = &controller->window[i]; | |
419 | if (!(window->resource.flags & res->flags)) | |
420 | continue; | |
421 | if (window->resource.start - window->offset > region->start) | |
422 | continue; | |
423 | if (window->resource.end - window->offset < region->end) | |
424 | continue; | |
425 | offset = window->offset; | |
426 | break; | |
427 | } | |
428 | ||
429 | res->start = region->start + offset; | |
430 | res->end = region->end + offset; | |
431 | } | |
41290c14 | 432 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 433 | |
71c3511c RS |
434 | static int __devinit is_valid_resource(struct pci_dev *dev, int idx) |
435 | { | |
436 | unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; | |
437 | struct resource *devr = &dev->resource[idx]; | |
438 | ||
439 | if (!dev->bus) | |
440 | return 0; | |
441 | for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) { | |
442 | struct resource *busr = dev->bus->resource[i]; | |
443 | ||
444 | if (!busr || ((busr->flags ^ devr->flags) & type_mask)) | |
445 | continue; | |
446 | if ((devr->start) && (devr->start >= busr->start) && | |
447 | (devr->end <= busr->end)) | |
448 | return 1; | |
449 | } | |
450 | return 0; | |
451 | } | |
452 | ||
7b9c8ba2 KK |
453 | static void __devinit |
454 | pcibios_fixup_resources(struct pci_dev *dev, int start, int limit) | |
1da177e4 LT |
455 | { |
456 | struct pci_bus_region region; | |
457 | int i; | |
1da177e4 | 458 | |
7b9c8ba2 | 459 | for (i = start; i < limit; i++) { |
1da177e4 LT |
460 | if (!dev->resource[i].flags) |
461 | continue; | |
462 | region.start = dev->resource[i].start; | |
463 | region.end = dev->resource[i].end; | |
464 | pcibios_bus_to_resource(dev, &dev->resource[i], ®ion); | |
71c3511c RS |
465 | if ((is_valid_resource(dev, i))) |
466 | pci_claim_resource(dev, i); | |
1da177e4 LT |
467 | } |
468 | } | |
469 | ||
8ea6091f | 470 | void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) |
7b9c8ba2 KK |
471 | { |
472 | pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES); | |
473 | } | |
8ea6091f | 474 | EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources); |
7b9c8ba2 KK |
475 | |
476 | static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev) | |
477 | { | |
478 | pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES); | |
479 | } | |
480 | ||
1da177e4 LT |
481 | /* |
482 | * Called after each bus is probed, but before its children are examined. | |
483 | */ | |
484 | void __devinit | |
485 | pcibios_fixup_bus (struct pci_bus *b) | |
486 | { | |
487 | struct pci_dev *dev; | |
488 | ||
f7d473d9 RS |
489 | if (b->self) { |
490 | pci_read_bridge_bases(b); | |
7b9c8ba2 | 491 | pcibios_fixup_bridge_resources(b->self); |
f7d473d9 | 492 | } |
1da177e4 LT |
493 | list_for_each_entry(dev, &b->devices, bus_list) |
494 | pcibios_fixup_device_resources(dev); | |
8ea6091f | 495 | platform_pci_fixup_bus(b); |
1da177e4 LT |
496 | |
497 | return; | |
498 | } | |
499 | ||
500 | void __devinit | |
501 | pcibios_update_irq (struct pci_dev *dev, int irq) | |
502 | { | |
503 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
504 | ||
505 | /* ??? FIXME -- record old value for shutdown. */ | |
506 | } | |
507 | ||
1da177e4 LT |
508 | int |
509 | pcibios_enable_device (struct pci_dev *dev, int mask) | |
510 | { | |
511 | int ret; | |
512 | ||
d981f163 | 513 | ret = pci_enable_resources(dev, mask); |
1da177e4 LT |
514 | if (ret < 0) |
515 | return ret; | |
516 | ||
bba6f6fc EB |
517 | if (!dev->msi_enabled) |
518 | return acpi_pci_irq_enable(dev); | |
519 | return 0; | |
1da177e4 LT |
520 | } |
521 | ||
1da177e4 LT |
522 | void |
523 | pcibios_disable_device (struct pci_dev *dev) | |
524 | { | |
c7f570a5 | 525 | BUG_ON(atomic_read(&dev->enable_cnt)); |
bba6f6fc EB |
526 | if (!dev->msi_enabled) |
527 | acpi_pci_irq_disable(dev); | |
1da177e4 | 528 | } |
1da177e4 LT |
529 | |
530 | void | |
531 | pcibios_align_resource (void *data, struct resource *res, | |
e31dd6e4 | 532 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
533 | { |
534 | } | |
535 | ||
536 | /* | |
537 | * PCI BIOS setup, always defaults to SAL interface | |
538 | */ | |
cb2e0912 | 539 | char * __devinit |
1da177e4 LT |
540 | pcibios_setup (char *str) |
541 | { | |
ac311ac2 | 542 | return str; |
1da177e4 LT |
543 | } |
544 | ||
545 | int | |
546 | pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
547 | enum pci_mmap_state mmap_state, int write_combine) | |
548 | { | |
012b7105 AC |
549 | unsigned long size = vma->vm_end - vma->vm_start; |
550 | pgprot_t prot; | |
551 | ||
1da177e4 LT |
552 | /* |
553 | * I/O space cannot be accessed via normal processor loads and | |
554 | * stores on this platform. | |
555 | */ | |
556 | if (mmap_state == pci_mmap_io) | |
557 | /* | |
558 | * XXX we could relax this for I/O spaces for which ACPI | |
559 | * indicates that the space is 1-to-1 mapped. But at the | |
560 | * moment, we don't support multiple PCI address spaces and | |
561 | * the legacy I/O space is not 1-to-1 mapped, so this is moot. | |
562 | */ | |
563 | return -EINVAL; | |
564 | ||
012b7105 AC |
565 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
566 | return -EINVAL; | |
567 | ||
568 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
569 | vma->vm_page_prot); | |
570 | ||
1da177e4 | 571 | /* |
012b7105 AC |
572 | * If the user requested WC, the kernel uses UC or WC for this region, |
573 | * and the chipset supports WC, we can use WC. Otherwise, we have to | |
574 | * use the same attribute the kernel uses. | |
1da177e4 | 575 | */ |
012b7105 AC |
576 | if (write_combine && |
577 | ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC || | |
578 | (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) && | |
579 | efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) | |
1da177e4 LT |
580 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); |
581 | else | |
012b7105 | 582 | vma->vm_page_prot = prot; |
1da177e4 LT |
583 | |
584 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
585 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
586 | return -EAGAIN; | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
591 | /** | |
592 | * ia64_pci_get_legacy_mem - generic legacy mem routine | |
593 | * @bus: bus to get legacy memory base address for | |
594 | * | |
595 | * Find the base of legacy memory for @bus. This is typically the first | |
596 | * megabyte of bus address space for @bus or is simply 0 on platforms whose | |
597 | * chipsets support legacy I/O and memory routing. Returns the base address | |
598 | * or an error pointer if an error occurred. | |
599 | * | |
600 | * This is the ia64 generic version of this routine. Other platforms | |
601 | * are free to override it with a machine vector. | |
602 | */ | |
603 | char *ia64_pci_get_legacy_mem(struct pci_bus *bus) | |
604 | { | |
605 | return (char *)__IA64_UNCACHED_OFFSET; | |
606 | } | |
607 | ||
608 | /** | |
609 | * pci_mmap_legacy_page_range - map legacy memory space to userland | |
610 | * @bus: bus whose legacy space we're mapping | |
611 | * @vma: vma passed in by mmap | |
612 | * | |
613 | * Map legacy memory space for this device back to userspace using a machine | |
614 | * vector to get the base address. | |
615 | */ | |
616 | int | |
f19aeb1f BH |
617 | pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma, |
618 | enum pci_mmap_state mmap_state) | |
1da177e4 | 619 | { |
32e62c63 BH |
620 | unsigned long size = vma->vm_end - vma->vm_start; |
621 | pgprot_t prot; | |
1da177e4 LT |
622 | char *addr; |
623 | ||
f19aeb1f BH |
624 | /* We only support mmap'ing of legacy memory space */ |
625 | if (mmap_state != pci_mmap_mem) | |
626 | return -ENOSYS; | |
627 | ||
32e62c63 BH |
628 | /* |
629 | * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt | |
630 | * for more details. | |
631 | */ | |
06c67bef | 632 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
32e62c63 BH |
633 | return -EINVAL; |
634 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
635 | vma->vm_page_prot); | |
32e62c63 | 636 | |
1da177e4 LT |
637 | addr = pci_get_legacy_mem(bus); |
638 | if (IS_ERR(addr)) | |
639 | return PTR_ERR(addr); | |
640 | ||
641 | vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; | |
32e62c63 | 642 | vma->vm_page_prot = prot; |
1da177e4 LT |
643 | |
644 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
32e62c63 | 645 | size, vma->vm_page_prot)) |
1da177e4 LT |
646 | return -EAGAIN; |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | /** | |
652 | * ia64_pci_legacy_read - read from legacy I/O space | |
653 | * @bus: bus to read | |
654 | * @port: legacy port value | |
655 | * @val: caller allocated storage for returned value | |
656 | * @size: number of bytes to read | |
657 | * | |
658 | * Simply reads @size bytes from @port and puts the result in @val. | |
659 | * | |
660 | * Again, this (and the write routine) are generic versions that can be | |
661 | * overridden by the platform. This is necessary on platforms that don't | |
662 | * support legacy I/O routing or that hard fail on legacy I/O timeouts. | |
663 | */ | |
664 | int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
665 | { | |
666 | int ret = size; | |
667 | ||
668 | switch (size) { | |
669 | case 1: | |
670 | *val = inb(port); | |
671 | break; | |
672 | case 2: | |
673 | *val = inw(port); | |
674 | break; | |
675 | case 4: | |
676 | *val = inl(port); | |
677 | break; | |
678 | default: | |
679 | ret = -EINVAL; | |
680 | break; | |
681 | } | |
682 | ||
683 | return ret; | |
684 | } | |
685 | ||
686 | /** | |
687 | * ia64_pci_legacy_write - perform a legacy I/O write | |
688 | * @bus: bus pointer | |
689 | * @port: port to write | |
690 | * @val: value to write | |
691 | * @size: number of bytes to write from @val | |
692 | * | |
693 | * Simply writes @size bytes of @val to @port. | |
694 | */ | |
a72391e4 | 695 | int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) |
1da177e4 | 696 | { |
408045af | 697 | int ret = size; |
1da177e4 LT |
698 | |
699 | switch (size) { | |
700 | case 1: | |
701 | outb(val, port); | |
702 | break; | |
703 | case 2: | |
704 | outw(val, port); | |
705 | break; | |
706 | case 4: | |
707 | outl(val, port); | |
708 | break; | |
709 | default: | |
710 | ret = -EINVAL; | |
711 | break; | |
712 | } | |
713 | ||
714 | return ret; | |
715 | } | |
716 | ||
3efe2d84 MW |
717 | /* It's defined in drivers/pci/pci.c */ |
718 | extern u8 pci_cache_line_size; | |
719 | ||
1da177e4 | 720 | /** |
3efe2d84 | 721 | * set_pci_cacheline_size - determine cacheline size for PCI devices |
1da177e4 LT |
722 | * |
723 | * We want to use the line-size of the outer-most cache. We assume | |
724 | * that this line-size is the same for all CPUs. | |
725 | * | |
726 | * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). | |
1da177e4 | 727 | */ |
3efe2d84 | 728 | static void __init set_pci_cacheline_size(void) |
1da177e4 LT |
729 | { |
730 | u64 levels, unique_caches; | |
731 | s64 status; | |
732 | pal_cache_config_info_t cci; | |
1da177e4 LT |
733 | |
734 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
735 | if (status != 0) { | |
3efe2d84 | 736 | printk(KERN_ERR "%s: ia64_pal_cache_summary() failed " |
d4ed8084 | 737 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 738 | return; |
1da177e4 LT |
739 | } |
740 | ||
3efe2d84 MW |
741 | status = ia64_pal_cache_config_info(levels - 1, |
742 | /* cache_type (data_or_unified)= */ 2, &cci); | |
1da177e4 | 743 | if (status != 0) { |
3efe2d84 | 744 | printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed " |
d4ed8084 | 745 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 746 | return; |
1da177e4 | 747 | } |
3efe2d84 | 748 | pci_cache_line_size = (1 << cci.pcci_line_size) / 4; |
1da177e4 LT |
749 | } |
750 | ||
3efe2d84 MW |
751 | static int __init pcibios_init(void) |
752 | { | |
753 | set_pci_cacheline_size(); | |
754 | return 0; | |
1da177e4 | 755 | } |
3efe2d84 MW |
756 | |
757 | subsys_initcall(pcibios_init); |