Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: mca.c | |
3 | * Purpose: Generic MCA handling layer | |
4 | * | |
1da177e4 LT |
5 | * Copyright (C) 2003 Hewlett-Packard Co |
6 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
7 | * | |
8 | * Copyright (C) 2002 Dell Inc. | |
fe77efb8 | 9 | * Copyright (C) Matt Domsch <Matt_Domsch@dell.com> |
1da177e4 LT |
10 | * |
11 | * Copyright (C) 2002 Intel | |
fe77efb8 | 12 | * Copyright (C) Jenna Hall <jenna.s.hall@intel.com> |
1da177e4 LT |
13 | * |
14 | * Copyright (C) 2001 Intel | |
fe77efb8 | 15 | * Copyright (C) Fred Lewis <frederick.v.lewis@intel.com> |
1da177e4 LT |
16 | * |
17 | * Copyright (C) 2000 Intel | |
fe77efb8 | 18 | * Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com> |
1da177e4 LT |
19 | * |
20 | * Copyright (C) 1999, 2004 Silicon Graphics, Inc. | |
fe77efb8 | 21 | * Copyright (C) Vijay Chander <vijay@engr.sgi.com> |
1da177e4 | 22 | * |
fe77efb8 HS |
23 | * Copyright (C) 2006 FUJITSU LIMITED |
24 | * Copyright (C) Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> | |
1da177e4 | 25 | * |
fe77efb8 HS |
26 | * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com> |
27 | * Fixed PAL/SAL update issues, began MCA bug fixes, logging issues, | |
28 | * added min save state dump, added INIT handler. | |
1da177e4 | 29 | * |
fe77efb8 HS |
30 | * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com> |
31 | * Added setup of CMCI and CPEI IRQs, logging of corrected platform | |
32 | * errors, completed code for logging of corrected & uncorrected | |
33 | * machine check errors, and updated for conformance with Nov. 2000 | |
34 | * revision of the SAL 3.0 spec. | |
35 | * | |
36 | * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com> | |
37 | * Aligned MCA stack to 16 bytes, added platform vs. CPU error flag, | |
38 | * set SAL default return values, changed error record structure to | |
39 | * linked list, added init call to sal_get_state_info_size(). | |
40 | * | |
41 | * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com> | |
42 | * GUID cleanups. | |
43 | * | |
44 | * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com> | |
45 | * Added INIT backtrace support. | |
1da177e4 LT |
46 | * |
47 | * 2003-12-08 Keith Owens <kaos@sgi.com> | |
fe77efb8 HS |
48 | * smp_call_function() must not be called from interrupt context |
49 | * (can deadlock on tasklist_lock). | |
50 | * Use keventd to call smp_call_function(). | |
1da177e4 LT |
51 | * |
52 | * 2004-02-01 Keith Owens <kaos@sgi.com> | |
fe77efb8 HS |
53 | * Avoid deadlock when using printk() for MCA and INIT records. |
54 | * Delete all record printing code, moved to salinfo_decode in user | |
55 | * space. Mark variables and functions static where possible. | |
56 | * Delete dead variables and functions. Reorder to remove the need | |
57 | * for forward declarations and to consolidate related code. | |
7f613c7d KO |
58 | * |
59 | * 2005-08-12 Keith Owens <kaos@sgi.com> | |
fe77efb8 HS |
60 | * Convert MCA/INIT handlers to use per event stacks and SAL/OS |
61 | * state. | |
9138d581 KO |
62 | * |
63 | * 2005-10-07 Keith Owens <kaos@sgi.com> | |
64 | * Add notify_die() hooks. | |
43ed3baf HS |
65 | * |
66 | * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> | |
fe77efb8 | 67 | * Add printing support for MCA/INIT. |
1612b18c RA |
68 | * |
69 | * 2007-04-27 Russ Anderson <rja@sgi.com> | |
70 | * Support multiple cpus going through OS_MCA in the same event. | |
1da177e4 | 71 | */ |
1da177e4 LT |
72 | #include <linux/types.h> |
73 | #include <linux/init.h> | |
74 | #include <linux/sched.h> | |
75 | #include <linux/interrupt.h> | |
76 | #include <linux/irq.h> | |
1da177e4 LT |
77 | #include <linux/bootmem.h> |
78 | #include <linux/acpi.h> | |
79 | #include <linux/timer.h> | |
80 | #include <linux/module.h> | |
81 | #include <linux/kernel.h> | |
82 | #include <linux/smp.h> | |
83 | #include <linux/workqueue.h> | |
4668f0cd | 84 | #include <linux/cpumask.h> |
1eeb66a1 | 85 | #include <linux/kdebug.h> |
ed5d4026 | 86 | #include <linux/cpu.h> |
1da177e4 LT |
87 | |
88 | #include <asm/delay.h> | |
89 | #include <asm/machvec.h> | |
90 | #include <asm/meminit.h> | |
91 | #include <asm/page.h> | |
92 | #include <asm/ptrace.h> | |
93 | #include <asm/system.h> | |
94 | #include <asm/sal.h> | |
95 | #include <asm/mca.h> | |
a7956113 | 96 | #include <asm/kexec.h> |
1da177e4 LT |
97 | |
98 | #include <asm/irq.h> | |
99 | #include <asm/hw_irq.h> | |
100 | ||
d2a28ad9 | 101 | #include "mca_drv.h" |
7f613c7d KO |
102 | #include "entry.h" |
103 | ||
1da177e4 LT |
104 | #if defined(IA64_MCA_DEBUG_INFO) |
105 | # define IA64_MCA_DEBUG(fmt...) printk(fmt) | |
106 | #else | |
107 | # define IA64_MCA_DEBUG(fmt...) | |
108 | #endif | |
109 | ||
110 | /* Used by mca_asm.S */ | |
1da177e4 LT |
111 | DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */ |
112 | DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */ | |
113 | DEFINE_PER_CPU(u64, ia64_mca_pal_pte); /* PTE to map PAL code */ | |
114 | DEFINE_PER_CPU(u64, ia64_mca_pal_base); /* vaddr PAL code granule */ | |
115 | ||
116 | unsigned long __per_cpu_mca[NR_CPUS]; | |
117 | ||
118 | /* In mca_asm.S */ | |
7f613c7d KO |
119 | extern void ia64_os_init_dispatch_monarch (void); |
120 | extern void ia64_os_init_dispatch_slave (void); | |
121 | ||
122 | static int monarch_cpu = -1; | |
1da177e4 LT |
123 | |
124 | static ia64_mc_info_t ia64_mc_info; | |
125 | ||
126 | #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */ | |
127 | #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */ | |
128 | #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */ | |
129 | #define CPE_HISTORY_LENGTH 5 | |
130 | #define CMC_HISTORY_LENGTH 5 | |
131 | ||
34eac2ab | 132 | #ifdef CONFIG_ACPI |
1da177e4 | 133 | static struct timer_list cpe_poll_timer; |
34eac2ab | 134 | #endif |
1da177e4 LT |
135 | static struct timer_list cmc_poll_timer; |
136 | /* | |
137 | * This variable tells whether we are currently in polling mode. | |
138 | * Start with this in the wrong state so we won't play w/ timers | |
139 | * before the system is ready. | |
140 | */ | |
141 | static int cmc_polling_enabled = 1; | |
142 | ||
143 | /* | |
144 | * Clearing this variable prevents CPE polling from getting activated | |
145 | * in mca_late_init. Use it if your system doesn't provide a CPEI, | |
146 | * but encounters problems retrieving CPE logs. This should only be | |
147 | * necessary for debugging. | |
148 | */ | |
149 | static int cpe_poll_enabled = 1; | |
150 | ||
151 | extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe); | |
152 | ||
0881fc8d | 153 | static int mca_init __initdata; |
1da177e4 | 154 | |
43ed3baf HS |
155 | /* |
156 | * limited & delayed printing support for MCA/INIT handler | |
157 | */ | |
158 | ||
159 | #define mprintk(fmt...) ia64_mca_printk(fmt) | |
160 | ||
161 | #define MLOGBUF_SIZE (512+256*NR_CPUS) | |
162 | #define MLOGBUF_MSGMAX 256 | |
163 | static char mlogbuf[MLOGBUF_SIZE]; | |
164 | static DEFINE_SPINLOCK(mlogbuf_wlock); /* mca context only */ | |
165 | static DEFINE_SPINLOCK(mlogbuf_rlock); /* normal context only */ | |
166 | static unsigned long mlogbuf_start; | |
167 | static unsigned long mlogbuf_end; | |
168 | static unsigned int mlogbuf_finished = 0; | |
169 | static unsigned long mlogbuf_timestamp = 0; | |
170 | ||
171 | static int loglevel_save = -1; | |
172 | #define BREAK_LOGLEVEL(__console_loglevel) \ | |
173 | oops_in_progress = 1; \ | |
174 | if (loglevel_save < 0) \ | |
175 | loglevel_save = __console_loglevel; \ | |
176 | __console_loglevel = 15; | |
177 | ||
178 | #define RESTORE_LOGLEVEL(__console_loglevel) \ | |
179 | if (loglevel_save >= 0) { \ | |
180 | __console_loglevel = loglevel_save; \ | |
181 | loglevel_save = -1; \ | |
182 | } \ | |
183 | mlogbuf_finished = 0; \ | |
184 | oops_in_progress = 0; | |
185 | ||
186 | /* | |
187 | * Push messages into buffer, print them later if not urgent. | |
188 | */ | |
189 | void ia64_mca_printk(const char *fmt, ...) | |
190 | { | |
191 | va_list args; | |
192 | int printed_len; | |
193 | char temp_buf[MLOGBUF_MSGMAX]; | |
194 | char *p; | |
195 | ||
196 | va_start(args, fmt); | |
197 | printed_len = vscnprintf(temp_buf, sizeof(temp_buf), fmt, args); | |
198 | va_end(args); | |
199 | ||
200 | /* Copy the output into mlogbuf */ | |
201 | if (oops_in_progress) { | |
202 | /* mlogbuf was abandoned, use printk directly instead. */ | |
203 | printk(temp_buf); | |
204 | } else { | |
205 | spin_lock(&mlogbuf_wlock); | |
206 | for (p = temp_buf; *p; p++) { | |
207 | unsigned long next = (mlogbuf_end + 1) % MLOGBUF_SIZE; | |
208 | if (next != mlogbuf_start) { | |
209 | mlogbuf[mlogbuf_end] = *p; | |
210 | mlogbuf_end = next; | |
211 | } else { | |
212 | /* buffer full */ | |
213 | break; | |
214 | } | |
215 | } | |
216 | mlogbuf[mlogbuf_end] = '\0'; | |
217 | spin_unlock(&mlogbuf_wlock); | |
218 | } | |
219 | } | |
220 | EXPORT_SYMBOL(ia64_mca_printk); | |
221 | ||
222 | /* | |
223 | * Print buffered messages. | |
224 | * NOTE: call this after returning normal context. (ex. from salinfod) | |
225 | */ | |
226 | void ia64_mlogbuf_dump(void) | |
227 | { | |
228 | char temp_buf[MLOGBUF_MSGMAX]; | |
229 | char *p; | |
230 | unsigned long index; | |
231 | unsigned long flags; | |
232 | unsigned int printed_len; | |
233 | ||
234 | /* Get output from mlogbuf */ | |
235 | while (mlogbuf_start != mlogbuf_end) { | |
236 | temp_buf[0] = '\0'; | |
237 | p = temp_buf; | |
238 | printed_len = 0; | |
239 | ||
240 | spin_lock_irqsave(&mlogbuf_rlock, flags); | |
241 | ||
242 | index = mlogbuf_start; | |
243 | while (index != mlogbuf_end) { | |
244 | *p = mlogbuf[index]; | |
245 | index = (index + 1) % MLOGBUF_SIZE; | |
246 | if (!*p) | |
247 | break; | |
248 | p++; | |
249 | if (++printed_len >= MLOGBUF_MSGMAX - 1) | |
250 | break; | |
251 | } | |
252 | *p = '\0'; | |
253 | if (temp_buf[0]) | |
254 | printk(temp_buf); | |
255 | mlogbuf_start = index; | |
256 | ||
257 | mlogbuf_timestamp = 0; | |
258 | spin_unlock_irqrestore(&mlogbuf_rlock, flags); | |
259 | } | |
260 | } | |
261 | EXPORT_SYMBOL(ia64_mlogbuf_dump); | |
262 | ||
263 | /* | |
264 | * Call this if system is going to down or if immediate flushing messages to | |
265 | * console is required. (ex. recovery was failed, crash dump is going to be | |
266 | * invoked, long-wait rendezvous etc.) | |
267 | * NOTE: this should be called from monarch. | |
268 | */ | |
269 | static void ia64_mlogbuf_finish(int wait) | |
270 | { | |
271 | BREAK_LOGLEVEL(console_loglevel); | |
272 | ||
273 | spin_lock_init(&mlogbuf_rlock); | |
274 | ia64_mlogbuf_dump(); | |
275 | printk(KERN_EMERG "mlogbuf_finish: printing switched to urgent mode, " | |
276 | "MCA/INIT might be dodgy or fail.\n"); | |
277 | ||
278 | if (!wait) | |
279 | return; | |
280 | ||
281 | /* wait for console */ | |
282 | printk("Delaying for 5 seconds...\n"); | |
283 | udelay(5*1000000); | |
284 | ||
285 | mlogbuf_finished = 1; | |
286 | } | |
43ed3baf HS |
287 | |
288 | /* | |
289 | * Print buffered messages from INIT context. | |
290 | */ | |
291 | static void ia64_mlogbuf_dump_from_init(void) | |
292 | { | |
293 | if (mlogbuf_finished) | |
294 | return; | |
295 | ||
296 | if (mlogbuf_timestamp && (mlogbuf_timestamp + 30*HZ > jiffies)) { | |
297 | printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT " | |
298 | " and the system seems to be messed up.\n"); | |
299 | ia64_mlogbuf_finish(0); | |
300 | return; | |
301 | } | |
302 | ||
303 | if (!spin_trylock(&mlogbuf_rlock)) { | |
304 | printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT. " | |
305 | "Generated messages other than stack dump will be " | |
306 | "buffered to mlogbuf and will be printed later.\n"); | |
307 | printk(KERN_ERR "INIT: If messages would not printed after " | |
308 | "this INIT, wait 30sec and assert INIT again.\n"); | |
309 | if (!mlogbuf_timestamp) | |
310 | mlogbuf_timestamp = jiffies; | |
311 | return; | |
312 | } | |
313 | spin_unlock(&mlogbuf_rlock); | |
314 | ia64_mlogbuf_dump(); | |
315 | } | |
9138d581 KO |
316 | |
317 | static void inline | |
318 | ia64_mca_spin(const char *func) | |
319 | { | |
43ed3baf HS |
320 | if (monarch_cpu == smp_processor_id()) |
321 | ia64_mlogbuf_finish(0); | |
322 | mprintk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func); | |
9138d581 KO |
323 | while (1) |
324 | cpu_relax(); | |
325 | } | |
1da177e4 LT |
326 | /* |
327 | * IA64_MCA log support | |
328 | */ | |
329 | #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */ | |
330 | #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */ | |
331 | ||
332 | typedef struct ia64_state_log_s | |
333 | { | |
334 | spinlock_t isl_lock; | |
335 | int isl_index; | |
336 | unsigned long isl_count; | |
337 | ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */ | |
338 | } ia64_state_log_t; | |
339 | ||
340 | static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES]; | |
341 | ||
342 | #define IA64_LOG_ALLOCATE(it, size) \ | |
343 | {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \ | |
344 | (ia64_err_rec_t *)alloc_bootmem(size); \ | |
345 | ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \ | |
346 | (ia64_err_rec_t *)alloc_bootmem(size);} | |
347 | #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock) | |
348 | #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s) | |
349 | #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s) | |
350 | #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index | |
351 | #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index | |
352 | #define IA64_LOG_INDEX_INC(it) \ | |
353 | {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \ | |
354 | ia64_state_log[it].isl_count++;} | |
355 | #define IA64_LOG_INDEX_DEC(it) \ | |
356 | ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index | |
357 | #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)])) | |
358 | #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)])) | |
359 | #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count | |
360 | ||
361 | /* | |
362 | * ia64_log_init | |
363 | * Reset the OS ia64 log buffer | |
364 | * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE}) | |
365 | * Outputs : None | |
366 | */ | |
0881fc8d | 367 | static void __init |
1da177e4 LT |
368 | ia64_log_init(int sal_info_type) |
369 | { | |
370 | u64 max_size = 0; | |
371 | ||
372 | IA64_LOG_NEXT_INDEX(sal_info_type) = 0; | |
373 | IA64_LOG_LOCK_INIT(sal_info_type); | |
374 | ||
375 | // SAL will tell us the maximum size of any error record of this type | |
376 | max_size = ia64_sal_get_state_info_size(sal_info_type); | |
377 | if (!max_size) | |
378 | /* alloc_bootmem() doesn't like zero-sized allocations! */ | |
379 | return; | |
380 | ||
381 | // set up OS data structures to hold error info | |
382 | IA64_LOG_ALLOCATE(sal_info_type, max_size); | |
383 | memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size); | |
384 | memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size); | |
385 | } | |
386 | ||
387 | /* | |
388 | * ia64_log_get | |
389 | * | |
390 | * Get the current MCA log from SAL and copy it into the OS log buffer. | |
391 | * | |
392 | * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE}) | |
393 | * irq_safe whether you can use printk at this point | |
394 | * Outputs : size (total record length) | |
395 | * *buffer (ptr to error record) | |
396 | * | |
397 | */ | |
398 | static u64 | |
399 | ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe) | |
400 | { | |
401 | sal_log_record_header_t *log_buffer; | |
402 | u64 total_len = 0; | |
c53421b1 | 403 | unsigned long s; |
1da177e4 LT |
404 | |
405 | IA64_LOG_LOCK(sal_info_type); | |
406 | ||
407 | /* Get the process state information */ | |
408 | log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type); | |
409 | ||
410 | total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer); | |
411 | ||
412 | if (total_len) { | |
413 | IA64_LOG_INDEX_INC(sal_info_type); | |
414 | IA64_LOG_UNLOCK(sal_info_type); | |
415 | if (irq_safe) { | |
416 | IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. " | |
417 | "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len); | |
418 | } | |
419 | *buffer = (u8 *) log_buffer; | |
420 | return total_len; | |
421 | } else { | |
422 | IA64_LOG_UNLOCK(sal_info_type); | |
423 | return 0; | |
424 | } | |
425 | } | |
426 | ||
427 | /* | |
428 | * ia64_mca_log_sal_error_record | |
429 | * | |
430 | * This function retrieves a specified error record type from SAL | |
431 | * and wakes up any processes waiting for error records. | |
432 | * | |
7f613c7d KO |
433 | * Inputs : sal_info_type (Type of error record MCA/CMC/CPE) |
434 | * FIXME: remove MCA and irq_safe. | |
1da177e4 LT |
435 | */ |
436 | static void | |
437 | ia64_mca_log_sal_error_record(int sal_info_type) | |
438 | { | |
439 | u8 *buffer; | |
440 | sal_log_record_header_t *rh; | |
441 | u64 size; | |
7f613c7d | 442 | int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA; |
1da177e4 LT |
443 | #ifdef IA64_MCA_DEBUG_INFO |
444 | static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" }; | |
445 | #endif | |
446 | ||
447 | size = ia64_log_get(sal_info_type, &buffer, irq_safe); | |
448 | if (!size) | |
449 | return; | |
450 | ||
451 | salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe); | |
452 | ||
453 | if (irq_safe) | |
454 | IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n", | |
455 | smp_processor_id(), | |
456 | sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN"); | |
457 | ||
458 | /* Clear logs from corrected errors in case there's no user-level logger */ | |
459 | rh = (sal_log_record_header_t *)buffer; | |
460 | if (rh->severity == sal_log_severity_corrected) | |
461 | ia64_sal_clear_state_info(sal_info_type); | |
462 | } | |
463 | ||
d2a28ad9 RA |
464 | /* |
465 | * search_mca_table | |
466 | * See if the MCA surfaced in an instruction range | |
467 | * that has been tagged as recoverable. | |
468 | * | |
469 | * Inputs | |
470 | * first First address range to check | |
471 | * last Last address range to check | |
472 | * ip Instruction pointer, address we are looking for | |
473 | * | |
474 | * Return value: | |
475 | * 1 on Success (in the table)/ 0 on Failure (not in the table) | |
476 | */ | |
477 | int | |
478 | search_mca_table (const struct mca_table_entry *first, | |
479 | const struct mca_table_entry *last, | |
480 | unsigned long ip) | |
481 | { | |
482 | const struct mca_table_entry *curr; | |
483 | u64 curr_start, curr_end; | |
484 | ||
485 | curr = first; | |
486 | while (curr <= last) { | |
487 | curr_start = (u64) &curr->start_addr + curr->start_addr; | |
488 | curr_end = (u64) &curr->end_addr + curr->end_addr; | |
489 | ||
490 | if ((ip >= curr_start) && (ip <= curr_end)) { | |
491 | return 1; | |
492 | } | |
493 | curr++; | |
494 | } | |
495 | return 0; | |
496 | } | |
497 | ||
498 | /* Given an address, look for it in the mca tables. */ | |
499 | int mca_recover_range(unsigned long addr) | |
500 | { | |
501 | extern struct mca_table_entry __start___mca_table[]; | |
502 | extern struct mca_table_entry __stop___mca_table[]; | |
503 | ||
504 | return search_mca_table(__start___mca_table, __stop___mca_table-1, addr); | |
505 | } | |
506 | EXPORT_SYMBOL_GPL(mca_recover_range); | |
507 | ||
1da177e4 LT |
508 | #ifdef CONFIG_ACPI |
509 | ||
55e59c51 | 510 | int cpe_vector = -1; |
ff741906 | 511 | int ia64_cpe_irq = -1; |
1da177e4 LT |
512 | |
513 | static irqreturn_t | |
7d12e780 | 514 | ia64_mca_cpe_int_handler (int cpe_irq, void *arg) |
1da177e4 LT |
515 | { |
516 | static unsigned long cpe_history[CPE_HISTORY_LENGTH]; | |
517 | static int index; | |
518 | static DEFINE_SPINLOCK(cpe_history_lock); | |
519 | ||
520 | IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n", | |
521 | __FUNCTION__, cpe_irq, smp_processor_id()); | |
522 | ||
523 | /* SAL spec states this should run w/ interrupts enabled */ | |
524 | local_irq_enable(); | |
525 | ||
1da177e4 LT |
526 | spin_lock(&cpe_history_lock); |
527 | if (!cpe_poll_enabled && cpe_vector >= 0) { | |
528 | ||
529 | int i, count = 1; /* we know 1 happened now */ | |
530 | unsigned long now = jiffies; | |
531 | ||
532 | for (i = 0; i < CPE_HISTORY_LENGTH; i++) { | |
533 | if (now - cpe_history[i] <= HZ) | |
534 | count++; | |
535 | } | |
536 | ||
537 | IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH); | |
538 | if (count >= CPE_HISTORY_LENGTH) { | |
539 | ||
540 | cpe_poll_enabled = 1; | |
541 | spin_unlock(&cpe_history_lock); | |
542 | disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR)); | |
543 | ||
544 | /* | |
545 | * Corrected errors will still be corrected, but | |
546 | * make sure there's a log somewhere that indicates | |
547 | * something is generating more than we can handle. | |
548 | */ | |
549 | printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n"); | |
550 | ||
551 | mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL); | |
552 | ||
553 | /* lock already released, get out now */ | |
ddb4f0df | 554 | goto out; |
1da177e4 LT |
555 | } else { |
556 | cpe_history[index++] = now; | |
557 | if (index == CPE_HISTORY_LENGTH) | |
558 | index = 0; | |
559 | } | |
560 | } | |
561 | spin_unlock(&cpe_history_lock); | |
ddb4f0df HS |
562 | out: |
563 | /* Get the CPE error record and log it */ | |
564 | ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE); | |
565 | ||
1da177e4 LT |
566 | return IRQ_HANDLED; |
567 | } | |
568 | ||
569 | #endif /* CONFIG_ACPI */ | |
570 | ||
1da177e4 LT |
571 | #ifdef CONFIG_ACPI |
572 | /* | |
573 | * ia64_mca_register_cpev | |
574 | * | |
575 | * Register the corrected platform error vector with SAL. | |
576 | * | |
577 | * Inputs | |
578 | * cpev Corrected Platform Error Vector number | |
579 | * | |
580 | * Outputs | |
581 | * None | |
582 | */ | |
1f3b6045 | 583 | void |
1da177e4 LT |
584 | ia64_mca_register_cpev (int cpev) |
585 | { | |
586 | /* Register the CPE interrupt vector with SAL */ | |
587 | struct ia64_sal_retval isrv; | |
588 | ||
589 | isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0); | |
590 | if (isrv.status) { | |
591 | printk(KERN_ERR "Failed to register Corrected Platform " | |
592 | "Error interrupt vector with SAL (status %ld)\n", isrv.status); | |
593 | return; | |
594 | } | |
595 | ||
596 | IA64_MCA_DEBUG("%s: corrected platform error " | |
597 | "vector %#x registered\n", __FUNCTION__, cpev); | |
598 | } | |
599 | #endif /* CONFIG_ACPI */ | |
600 | ||
1da177e4 LT |
601 | /* |
602 | * ia64_mca_cmc_vector_setup | |
603 | * | |
604 | * Setup the corrected machine check vector register in the processor. | |
605 | * (The interrupt is masked on boot. ia64_mca_late_init unmask this.) | |
606 | * This function is invoked on a per-processor basis. | |
607 | * | |
608 | * Inputs | |
609 | * None | |
610 | * | |
611 | * Outputs | |
612 | * None | |
613 | */ | |
0881fc8d | 614 | void __cpuinit |
1da177e4 LT |
615 | ia64_mca_cmc_vector_setup (void) |
616 | { | |
617 | cmcv_reg_t cmcv; | |
618 | ||
619 | cmcv.cmcv_regval = 0; | |
620 | cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */ | |
621 | cmcv.cmcv_vector = IA64_CMC_VECTOR; | |
622 | ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); | |
623 | ||
624 | IA64_MCA_DEBUG("%s: CPU %d corrected " | |
625 | "machine check vector %#x registered.\n", | |
626 | __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR); | |
627 | ||
628 | IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n", | |
629 | __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV)); | |
630 | } | |
631 | ||
632 | /* | |
633 | * ia64_mca_cmc_vector_disable | |
634 | * | |
635 | * Mask the corrected machine check vector register in the processor. | |
636 | * This function is invoked on a per-processor basis. | |
637 | * | |
638 | * Inputs | |
639 | * dummy(unused) | |
640 | * | |
641 | * Outputs | |
642 | * None | |
643 | */ | |
644 | static void | |
645 | ia64_mca_cmc_vector_disable (void *dummy) | |
646 | { | |
647 | cmcv_reg_t cmcv; | |
648 | ||
649 | cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); | |
650 | ||
651 | cmcv.cmcv_mask = 1; /* Mask/disable interrupt */ | |
652 | ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); | |
653 | ||
654 | IA64_MCA_DEBUG("%s: CPU %d corrected " | |
655 | "machine check vector %#x disabled.\n", | |
656 | __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector); | |
657 | } | |
658 | ||
659 | /* | |
660 | * ia64_mca_cmc_vector_enable | |
661 | * | |
662 | * Unmask the corrected machine check vector register in the processor. | |
663 | * This function is invoked on a per-processor basis. | |
664 | * | |
665 | * Inputs | |
666 | * dummy(unused) | |
667 | * | |
668 | * Outputs | |
669 | * None | |
670 | */ | |
671 | static void | |
672 | ia64_mca_cmc_vector_enable (void *dummy) | |
673 | { | |
674 | cmcv_reg_t cmcv; | |
675 | ||
676 | cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); | |
677 | ||
678 | cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */ | |
679 | ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); | |
680 | ||
681 | IA64_MCA_DEBUG("%s: CPU %d corrected " | |
682 | "machine check vector %#x enabled.\n", | |
683 | __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector); | |
684 | } | |
685 | ||
686 | /* | |
687 | * ia64_mca_cmc_vector_disable_keventd | |
688 | * | |
689 | * Called via keventd (smp_call_function() is not safe in interrupt context) to | |
690 | * disable the cmc interrupt vector. | |
691 | */ | |
692 | static void | |
6d5aefb8 | 693 | ia64_mca_cmc_vector_disable_keventd(struct work_struct *unused) |
1da177e4 LT |
694 | { |
695 | on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0); | |
696 | } | |
697 | ||
698 | /* | |
699 | * ia64_mca_cmc_vector_enable_keventd | |
700 | * | |
701 | * Called via keventd (smp_call_function() is not safe in interrupt context) to | |
702 | * enable the cmc interrupt vector. | |
703 | */ | |
704 | static void | |
6d5aefb8 | 705 | ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused) |
1da177e4 LT |
706 | { |
707 | on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0); | |
708 | } | |
709 | ||
1da177e4 LT |
710 | /* |
711 | * ia64_mca_wakeup | |
712 | * | |
e1b1eb01 | 713 | * Send an inter-cpu interrupt to wake-up a particular cpu. |
1da177e4 LT |
714 | * |
715 | * Inputs : cpuid | |
716 | * Outputs : None | |
717 | */ | |
718 | static void | |
719 | ia64_mca_wakeup(int cpu) | |
720 | { | |
721 | platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0); | |
1da177e4 LT |
722 | } |
723 | ||
724 | /* | |
725 | * ia64_mca_wakeup_all | |
726 | * | |
e1b1eb01 | 727 | * Wakeup all the slave cpus which have rendez'ed previously. |
1da177e4 LT |
728 | * |
729 | * Inputs : None | |
730 | * Outputs : None | |
731 | */ | |
732 | static void | |
733 | ia64_mca_wakeup_all(void) | |
734 | { | |
735 | int cpu; | |
736 | ||
737 | /* Clear the Rendez checkin flag for all cpus */ | |
ddf6d0a0 | 738 | for_each_online_cpu(cpu) { |
1da177e4 LT |
739 | if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE) |
740 | ia64_mca_wakeup(cpu); | |
741 | } | |
742 | ||
743 | } | |
744 | ||
745 | /* | |
746 | * ia64_mca_rendez_interrupt_handler | |
747 | * | |
748 | * This is handler used to put slave processors into spinloop | |
749 | * while the monarch processor does the mca handling and later | |
e1b1eb01 RA |
750 | * wake each slave up once the monarch is done. The state |
751 | * IA64_MCA_RENDEZ_CHECKIN_DONE indicates the cpu is rendez'ed | |
752 | * in SAL. The state IA64_MCA_RENDEZ_CHECKIN_NOTDONE indicates | |
753 | * the cpu has come out of OS rendezvous. | |
1da177e4 LT |
754 | * |
755 | * Inputs : None | |
756 | * Outputs : None | |
757 | */ | |
758 | static irqreturn_t | |
7d12e780 | 759 | ia64_mca_rendez_int_handler(int rendez_irq, void *arg) |
1da177e4 LT |
760 | { |
761 | unsigned long flags; | |
762 | int cpu = smp_processor_id(); | |
958b166c KO |
763 | struct ia64_mca_notify_die nd = |
764 | { .sos = NULL, .monarch_cpu = &monarch_cpu }; | |
1da177e4 LT |
765 | |
766 | /* Mask all interrupts */ | |
767 | local_irq_save(flags); | |
7d12e780 DH |
768 | if (notify_die(DIE_MCA_RENDZVOUS_ENTER, "MCA", get_irq_regs(), |
769 | (long)&nd, 0, 0) == NOTIFY_STOP) | |
9138d581 | 770 | ia64_mca_spin(__FUNCTION__); |
1da177e4 LT |
771 | |
772 | ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE; | |
773 | /* Register with the SAL monarch that the slave has | |
774 | * reached SAL | |
775 | */ | |
776 | ia64_sal_mc_rendez(); | |
777 | ||
7d12e780 DH |
778 | if (notify_die(DIE_MCA_RENDZVOUS_PROCESS, "MCA", get_irq_regs(), |
779 | (long)&nd, 0, 0) == NOTIFY_STOP) | |
9138d581 KO |
780 | ia64_mca_spin(__FUNCTION__); |
781 | ||
7f613c7d KO |
782 | /* Wait for the monarch cpu to exit. */ |
783 | while (monarch_cpu != -1) | |
784 | cpu_relax(); /* spin until monarch leaves */ | |
1da177e4 | 785 | |
7d12e780 DH |
786 | if (notify_die(DIE_MCA_RENDZVOUS_LEAVE, "MCA", get_irq_regs(), |
787 | (long)&nd, 0, 0) == NOTIFY_STOP) | |
9138d581 KO |
788 | ia64_mca_spin(__FUNCTION__); |
789 | ||
e1b1eb01 | 790 | ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; |
1da177e4 LT |
791 | /* Enable all interrupts */ |
792 | local_irq_restore(flags); | |
793 | return IRQ_HANDLED; | |
794 | } | |
795 | ||
796 | /* | |
797 | * ia64_mca_wakeup_int_handler | |
798 | * | |
799 | * The interrupt handler for processing the inter-cpu interrupt to the | |
800 | * slave cpu which was spinning in the rendez loop. | |
801 | * Since this spinning is done by turning off the interrupts and | |
802 | * polling on the wakeup-interrupt bit in the IRR, there is | |
803 | * nothing useful to be done in the handler. | |
804 | * | |
805 | * Inputs : wakeup_irq (Wakeup-interrupt bit) | |
806 | * arg (Interrupt handler specific argument) | |
1da177e4 LT |
807 | * Outputs : None |
808 | * | |
809 | */ | |
810 | static irqreturn_t | |
7d12e780 | 811 | ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg) |
1da177e4 LT |
812 | { |
813 | return IRQ_HANDLED; | |
814 | } | |
815 | ||
1da177e4 LT |
816 | /* Function pointer for extra MCA recovery */ |
817 | int (*ia64_mca_ucmc_extension) | |
7f613c7d | 818 | (void*,struct ia64_sal_os_state*) |
1da177e4 LT |
819 | = NULL; |
820 | ||
821 | int | |
7f613c7d | 822 | ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *)) |
1da177e4 LT |
823 | { |
824 | if (ia64_mca_ucmc_extension) | |
825 | return 1; | |
826 | ||
827 | ia64_mca_ucmc_extension = fn; | |
828 | return 0; | |
829 | } | |
830 | ||
831 | void | |
832 | ia64_unreg_MCA_extension(void) | |
833 | { | |
834 | if (ia64_mca_ucmc_extension) | |
835 | ia64_mca_ucmc_extension = NULL; | |
836 | } | |
837 | ||
838 | EXPORT_SYMBOL(ia64_reg_MCA_extension); | |
839 | EXPORT_SYMBOL(ia64_unreg_MCA_extension); | |
840 | ||
7f613c7d KO |
841 | |
842 | static inline void | |
843 | copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat) | |
844 | { | |
845 | u64 fslot, tslot, nat; | |
846 | *tr = *fr; | |
847 | fslot = ((unsigned long)fr >> 3) & 63; | |
848 | tslot = ((unsigned long)tr >> 3) & 63; | |
849 | *tnat &= ~(1UL << tslot); | |
850 | nat = (fnat >> fslot) & 1; | |
851 | *tnat |= (nat << tslot); | |
852 | } | |
853 | ||
e9ac054d KO |
854 | /* Change the comm field on the MCA/INT task to include the pid that |
855 | * was interrupted, it makes for easier debugging. If that pid was 0 | |
856 | * (swapper or nested MCA/INIT) then use the start of the previous comm | |
857 | * field suffixed with its cpu. | |
858 | */ | |
859 | ||
860 | static void | |
36c8b586 | 861 | ia64_mca_modify_comm(const struct task_struct *previous_current) |
e9ac054d KO |
862 | { |
863 | char *p, comm[sizeof(current->comm)]; | |
864 | if (previous_current->pid) | |
865 | snprintf(comm, sizeof(comm), "%s %d", | |
866 | current->comm, previous_current->pid); | |
867 | else { | |
868 | int l; | |
869 | if ((p = strchr(previous_current->comm, ' '))) | |
870 | l = p - previous_current->comm; | |
871 | else | |
872 | l = strlen(previous_current->comm); | |
873 | snprintf(comm, sizeof(comm), "%s %*s %d", | |
874 | current->comm, l, previous_current->comm, | |
875 | task_thread_info(previous_current)->cpu); | |
876 | } | |
877 | memcpy(current->comm, comm, sizeof(current->comm)); | |
878 | } | |
879 | ||
7f613c7d KO |
880 | /* On entry to this routine, we are running on the per cpu stack, see |
881 | * mca_asm.h. The original stack has not been touched by this event. Some of | |
882 | * the original stack's registers will be in the RBS on this stack. This stack | |
883 | * also contains a partial pt_regs and switch_stack, the rest of the data is in | |
884 | * PAL minstate. | |
885 | * | |
886 | * The first thing to do is modify the original stack to look like a blocked | |
887 | * task so we can run backtrace on the original task. Also mark the per cpu | |
888 | * stack as current to ensure that we use the correct task state, it also means | |
889 | * that we can do backtrace on the MCA/INIT handler code itself. | |
890 | */ | |
891 | ||
36c8b586 | 892 | static struct task_struct * |
7f613c7d KO |
893 | ia64_mca_modify_original_stack(struct pt_regs *regs, |
894 | const struct switch_stack *sw, | |
895 | struct ia64_sal_os_state *sos, | |
896 | const char *type) | |
897 | { | |
e9ac054d | 898 | char *p; |
7f613c7d KO |
899 | ia64_va va; |
900 | extern char ia64_leave_kernel[]; /* Need asm address, not function descriptor */ | |
901 | const pal_min_state_area_t *ms = sos->pal_min_state; | |
36c8b586 | 902 | struct task_struct *previous_current; |
7f613c7d KO |
903 | struct pt_regs *old_regs; |
904 | struct switch_stack *old_sw; | |
905 | unsigned size = sizeof(struct pt_regs) + | |
906 | sizeof(struct switch_stack) + 16; | |
907 | u64 *old_bspstore, *old_bsp; | |
908 | u64 *new_bspstore, *new_bsp; | |
909 | u64 old_unat, old_rnat, new_rnat, nat; | |
910 | u64 slots, loadrs = regs->loadrs; | |
911 | u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1]; | |
912 | u64 ar_bspstore = regs->ar_bspstore; | |
913 | u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16); | |
914 | const u64 *bank; | |
915 | const char *msg; | |
916 | int cpu = smp_processor_id(); | |
917 | ||
918 | previous_current = curr_task(cpu); | |
919 | set_curr_task(cpu, current); | |
920 | if ((p = strchr(current->comm, ' '))) | |
921 | *p = '\0'; | |
922 | ||
923 | /* Best effort attempt to cope with MCA/INIT delivered while in | |
924 | * physical mode. | |
925 | */ | |
926 | regs->cr_ipsr = ms->pmsa_ipsr; | |
927 | if (ia64_psr(regs)->dt == 0) { | |
928 | va.l = r12; | |
929 | if (va.f.reg == 0) { | |
930 | va.f.reg = 7; | |
931 | r12 = va.l; | |
932 | } | |
933 | va.l = r13; | |
934 | if (va.f.reg == 0) { | |
935 | va.f.reg = 7; | |
936 | r13 = va.l; | |
937 | } | |
938 | } | |
939 | if (ia64_psr(regs)->rt == 0) { | |
940 | va.l = ar_bspstore; | |
941 | if (va.f.reg == 0) { | |
942 | va.f.reg = 7; | |
943 | ar_bspstore = va.l; | |
944 | } | |
945 | va.l = ar_bsp; | |
946 | if (va.f.reg == 0) { | |
947 | va.f.reg = 7; | |
948 | ar_bsp = va.l; | |
949 | } | |
950 | } | |
951 | ||
952 | /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers | |
953 | * have been copied to the old stack, the old stack may fail the | |
954 | * validation tests below. So ia64_old_stack() must restore the dirty | |
955 | * registers from the new stack. The old and new bspstore probably | |
956 | * have different alignments, so loadrs calculated on the old bsp | |
957 | * cannot be used to restore from the new bsp. Calculate a suitable | |
958 | * loadrs for the new stack and save it in the new pt_regs, where | |
959 | * ia64_old_stack() can get it. | |
960 | */ | |
961 | old_bspstore = (u64 *)ar_bspstore; | |
962 | old_bsp = (u64 *)ar_bsp; | |
963 | slots = ia64_rse_num_regs(old_bspstore, old_bsp); | |
964 | new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET); | |
965 | new_bsp = ia64_rse_skip_regs(new_bspstore, slots); | |
966 | regs->loadrs = (new_bsp - new_bspstore) * 8 << 16; | |
967 | ||
968 | /* Verify the previous stack state before we change it */ | |
969 | if (user_mode(regs)) { | |
970 | msg = "occurred in user space"; | |
e9ac054d KO |
971 | /* previous_current is guaranteed to be valid when the task was |
972 | * in user space, so ... | |
973 | */ | |
974 | ia64_mca_modify_comm(previous_current); | |
7f613c7d KO |
975 | goto no_mod; |
976 | } | |
d2a28ad9 | 977 | |
1612b18c RA |
978 | if (r13 != sos->prev_IA64_KR_CURRENT) { |
979 | msg = "inconsistent previous current and r13"; | |
980 | goto no_mod; | |
981 | } | |
982 | ||
d2a28ad9 | 983 | if (!mca_recover_range(ms->pmsa_iip)) { |
d2a28ad9 RA |
984 | if ((r12 - r13) >= KERNEL_STACK_SIZE) { |
985 | msg = "inconsistent r12 and r13"; | |
986 | goto no_mod; | |
987 | } | |
988 | if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) { | |
989 | msg = "inconsistent ar.bspstore and r13"; | |
990 | goto no_mod; | |
991 | } | |
992 | va.p = old_bspstore; | |
993 | if (va.f.reg < 5) { | |
994 | msg = "old_bspstore is in the wrong region"; | |
995 | goto no_mod; | |
996 | } | |
997 | if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) { | |
998 | msg = "inconsistent ar.bsp and r13"; | |
999 | goto no_mod; | |
1000 | } | |
1001 | size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8; | |
1002 | if (ar_bspstore + size > r12) { | |
1003 | msg = "no room for blocked state"; | |
1004 | goto no_mod; | |
1005 | } | |
7f613c7d KO |
1006 | } |
1007 | ||
e9ac054d | 1008 | ia64_mca_modify_comm(previous_current); |
7f613c7d KO |
1009 | |
1010 | /* Make the original task look blocked. First stack a struct pt_regs, | |
1011 | * describing the state at the time of interrupt. mca_asm.S built a | |
1012 | * partial pt_regs, copy it and fill in the blanks using minstate. | |
1013 | */ | |
1014 | p = (char *)r12 - sizeof(*regs); | |
1015 | old_regs = (struct pt_regs *)p; | |
1016 | memcpy(old_regs, regs, sizeof(*regs)); | |
1017 | /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use | |
1018 | * pmsa_{xip,xpsr,xfs} | |
1019 | */ | |
1020 | if (ia64_psr(regs)->ic) { | |
1021 | old_regs->cr_iip = ms->pmsa_iip; | |
1022 | old_regs->cr_ipsr = ms->pmsa_ipsr; | |
1023 | old_regs->cr_ifs = ms->pmsa_ifs; | |
1024 | } else { | |
1025 | old_regs->cr_iip = ms->pmsa_xip; | |
1026 | old_regs->cr_ipsr = ms->pmsa_xpsr; | |
1027 | old_regs->cr_ifs = ms->pmsa_xfs; | |
1028 | } | |
1029 | old_regs->pr = ms->pmsa_pr; | |
1030 | old_regs->b0 = ms->pmsa_br0; | |
1031 | old_regs->loadrs = loadrs; | |
1032 | old_regs->ar_rsc = ms->pmsa_rsc; | |
1033 | old_unat = old_regs->ar_unat; | |
1034 | copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat); | |
1035 | copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat); | |
1036 | copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat); | |
1037 | copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat); | |
1038 | copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat); | |
1039 | copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat); | |
1040 | copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat); | |
1041 | copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat); | |
1042 | copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat); | |
1043 | copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat); | |
1044 | copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat); | |
1045 | if (ia64_psr(old_regs)->bn) | |
1046 | bank = ms->pmsa_bank1_gr; | |
1047 | else | |
1048 | bank = ms->pmsa_bank0_gr; | |
1049 | copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat); | |
1050 | copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat); | |
1051 | copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat); | |
1052 | copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat); | |
1053 | copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat); | |
1054 | copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat); | |
1055 | copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat); | |
1056 | copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat); | |
1057 | copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat); | |
1058 | copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat); | |
1059 | copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat); | |
1060 | copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat); | |
1061 | copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat); | |
1062 | copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat); | |
1063 | copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat); | |
1064 | copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat); | |
1065 | ||
1066 | /* Next stack a struct switch_stack. mca_asm.S built a partial | |
1067 | * switch_stack, copy it and fill in the blanks using pt_regs and | |
1068 | * minstate. | |
1069 | * | |
1070 | * In the synthesized switch_stack, b0 points to ia64_leave_kernel, | |
1071 | * ar.pfs is set to 0. | |
1072 | * | |
1073 | * unwind.c::unw_unwind() does special processing for interrupt frames. | |
1074 | * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate | |
1075 | * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not | |
1076 | * that this is documented, of course. Set PRED_NON_SYSCALL in the | |
1077 | * switch_stack on the original stack so it will unwind correctly when | |
1078 | * unwind.c reads pt_regs. | |
1079 | * | |
1080 | * thread.ksp is updated to point to the synthesized switch_stack. | |
1081 | */ | |
1082 | p -= sizeof(struct switch_stack); | |
1083 | old_sw = (struct switch_stack *)p; | |
1084 | memcpy(old_sw, sw, sizeof(*sw)); | |
1085 | old_sw->caller_unat = old_unat; | |
1086 | old_sw->ar_fpsr = old_regs->ar_fpsr; | |
1087 | copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat); | |
1088 | copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat); | |
1089 | copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat); | |
1090 | copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat); | |
1091 | old_sw->b0 = (u64)ia64_leave_kernel; | |
1092 | old_sw->b1 = ms->pmsa_br1; | |
1093 | old_sw->ar_pfs = 0; | |
1094 | old_sw->ar_unat = old_unat; | |
1095 | old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL); | |
1096 | previous_current->thread.ksp = (u64)p - 16; | |
1097 | ||
1098 | /* Finally copy the original stack's registers back to its RBS. | |
1099 | * Registers from ar.bspstore through ar.bsp at the time of the event | |
1100 | * are in the current RBS, copy them back to the original stack. The | |
1101 | * copy must be done register by register because the original bspstore | |
1102 | * and the current one have different alignments, so the saved RNAT | |
1103 | * data occurs at different places. | |
1104 | * | |
1105 | * mca_asm does cover, so the old_bsp already includes all registers at | |
1106 | * the time of MCA/INIT. It also does flushrs, so all registers before | |
1107 | * this function have been written to backing store on the MCA/INIT | |
1108 | * stack. | |
1109 | */ | |
1110 | new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore)); | |
1111 | old_rnat = regs->ar_rnat; | |
1112 | while (slots--) { | |
1113 | if (ia64_rse_is_rnat_slot(new_bspstore)) { | |
1114 | new_rnat = ia64_get_rnat(new_bspstore++); | |
1115 | } | |
1116 | if (ia64_rse_is_rnat_slot(old_bspstore)) { | |
1117 | *old_bspstore++ = old_rnat; | |
1118 | old_rnat = 0; | |
1119 | } | |
1120 | nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL; | |
1121 | old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore)); | |
1122 | old_rnat |= (nat << ia64_rse_slot_num(old_bspstore)); | |
1123 | *old_bspstore++ = *new_bspstore++; | |
1124 | } | |
1125 | old_sw->ar_bspstore = (unsigned long)old_bspstore; | |
1126 | old_sw->ar_rnat = old_rnat; | |
1127 | ||
1128 | sos->prev_task = previous_current; | |
1129 | return previous_current; | |
1130 | ||
1131 | no_mod: | |
1132 | printk(KERN_INFO "cpu %d, %s %s, original stack not modified\n", | |
1133 | smp_processor_id(), type, msg); | |
1134 | return previous_current; | |
1135 | } | |
1136 | ||
1137 | /* The monarch/slave interaction is based on monarch_cpu and requires that all | |
1138 | * slaves have entered rendezvous before the monarch leaves. If any cpu has | |
1139 | * not entered rendezvous yet then wait a bit. The assumption is that any | |
1140 | * slave that has not rendezvoused after a reasonable time is never going to do | |
1141 | * so. In this context, slave includes cpus that respond to the MCA rendezvous | |
1142 | * interrupt, as well as cpus that receive the INIT slave event. | |
1143 | */ | |
1144 | ||
1145 | static void | |
356a5c1c | 1146 | ia64_wait_for_slaves(int monarch, const char *type) |
7f613c7d | 1147 | { |
2bc5c282 RA |
1148 | int c, i , wait; |
1149 | ||
1150 | /* | |
1151 | * wait 5 seconds total for slaves (arbitrary) | |
1152 | */ | |
1153 | for (i = 0; i < 5000; i++) { | |
1154 | wait = 0; | |
1155 | for_each_online_cpu(c) { | |
1156 | if (c == monarch) | |
1157 | continue; | |
1158 | if (ia64_mc_info.imi_rendez_checkin[c] | |
1159 | == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) { | |
1160 | udelay(1000); /* short wait */ | |
1161 | wait = 1; | |
1162 | break; | |
1163 | } | |
7f613c7d | 1164 | } |
2bc5c282 RA |
1165 | if (!wait) |
1166 | goto all_in; | |
7f613c7d | 1167 | } |
2bc5c282 | 1168 | |
43ed3baf HS |
1169 | /* |
1170 | * Maybe slave(s) dead. Print buffered messages immediately. | |
1171 | */ | |
1172 | ia64_mlogbuf_finish(0); | |
1173 | mprintk(KERN_INFO "OS %s slave did not rendezvous on cpu", type); | |
9336b083 KO |
1174 | for_each_online_cpu(c) { |
1175 | if (c == monarch) | |
1176 | continue; | |
1177 | if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) | |
43ed3baf | 1178 | mprintk(" %d", c); |
9336b083 | 1179 | } |
43ed3baf | 1180 | mprintk("\n"); |
9336b083 KO |
1181 | return; |
1182 | ||
1183 | all_in: | |
43ed3baf | 1184 | mprintk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type); |
9336b083 | 1185 | return; |
7f613c7d KO |
1186 | } |
1187 | ||
1da177e4 | 1188 | /* |
7f613c7d | 1189 | * ia64_mca_handler |
1da177e4 LT |
1190 | * |
1191 | * This is uncorrectable machine check handler called from OS_MCA | |
1192 | * dispatch code which is in turn called from SAL_CHECK(). | |
1193 | * This is the place where the core of OS MCA handling is done. | |
1194 | * Right now the logs are extracted and displayed in a well-defined | |
1195 | * format. This handler code is supposed to be run only on the | |
1196 | * monarch processor. Once the monarch is done with MCA handling | |
1197 | * further MCA logging is enabled by clearing logs. | |
1198 | * Monarch also has the duty of sending wakeup-IPIs to pull the | |
1199 | * slave processors out of rendezvous spinloop. | |
1612b18c RA |
1200 | * |
1201 | * If multiple processors call into OS_MCA, the first will become | |
1202 | * the monarch. Subsequent cpus will be recorded in the mca_cpu | |
1203 | * bitmask. After the first monarch has processed its MCA, it | |
1204 | * will wake up the next cpu in the mca_cpu bitmask and then go | |
1205 | * into the rendezvous loop. When all processors have serviced | |
1206 | * their MCA, the last monarch frees up the rest of the processors. | |
1da177e4 LT |
1207 | */ |
1208 | void | |
7f613c7d KO |
1209 | ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw, |
1210 | struct ia64_sal_os_state *sos) | |
1da177e4 | 1211 | { |
7f613c7d | 1212 | int recover, cpu = smp_processor_id(); |
36c8b586 | 1213 | struct task_struct *previous_current; |
958b166c KO |
1214 | struct ia64_mca_notify_die nd = |
1215 | { .sos = sos, .monarch_cpu = &monarch_cpu }; | |
1612b18c RA |
1216 | static atomic_t mca_count; |
1217 | static cpumask_t mca_cpu; | |
7f613c7d | 1218 | |
1612b18c RA |
1219 | if (atomic_add_return(1, &mca_count) == 1) { |
1220 | monarch_cpu = cpu; | |
1221 | sos->monarch = 1; | |
1222 | } else { | |
1223 | cpu_set(cpu, mca_cpu); | |
1224 | sos->monarch = 0; | |
1225 | } | |
43ed3baf HS |
1226 | mprintk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d " |
1227 | "monarch=%ld\n", sos->proc_state_param, cpu, sos->monarch); | |
9336b083 | 1228 | |
7f613c7d | 1229 | previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA"); |
1612b18c | 1230 | |
958b166c | 1231 | if (notify_die(DIE_MCA_MONARCH_ENTER, "MCA", regs, (long)&nd, 0, 0) |
9138d581 KO |
1232 | == NOTIFY_STOP) |
1233 | ia64_mca_spin(__FUNCTION__); | |
e1b1eb01 RA |
1234 | |
1235 | ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA; | |
1612b18c RA |
1236 | if (sos->monarch) { |
1237 | ia64_wait_for_slaves(cpu, "MCA"); | |
e1b1eb01 RA |
1238 | |
1239 | /* Wakeup all the processors which are spinning in the | |
1240 | * rendezvous loop. They will leave SAL, then spin in the OS | |
1241 | * with interrupts disabled until this monarch cpu leaves the | |
1242 | * MCA handler. That gets control back to the OS so we can | |
1243 | * backtrace the other cpus, backtrace when spinning in SAL | |
1244 | * does not work. | |
1245 | */ | |
1246 | ia64_mca_wakeup_all(); | |
1247 | if (notify_die(DIE_MCA_MONARCH_PROCESS, "MCA", regs, (long)&nd, 0, 0) | |
1248 | == NOTIFY_STOP) | |
1249 | ia64_mca_spin(__FUNCTION__); | |
1612b18c | 1250 | } else { |
1612b18c RA |
1251 | while (cpu_isset(cpu, mca_cpu)) |
1252 | cpu_relax(); /* spin until monarch wakes us */ | |
1612b18c | 1253 | } |
7f613c7d | 1254 | |
1da177e4 LT |
1255 | /* Get the MCA error record and log it */ |
1256 | ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA); | |
1257 | ||
618b206f RA |
1258 | /* MCA error recovery */ |
1259 | recover = (ia64_mca_ucmc_extension | |
1da177e4 LT |
1260 | && ia64_mca_ucmc_extension( |
1261 | IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA), | |
7f613c7d | 1262 | sos)); |
1da177e4 LT |
1263 | |
1264 | if (recover) { | |
1265 | sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA); | |
1266 | rh->severity = sal_log_severity_corrected; | |
1267 | ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA); | |
7f613c7d | 1268 | sos->os_status = IA64_MCA_CORRECTED; |
43ed3baf HS |
1269 | } else { |
1270 | /* Dump buffered message to console */ | |
1271 | ia64_mlogbuf_finish(1); | |
45a98fc6 | 1272 | #ifdef CONFIG_KEXEC |
a7956113 ZN |
1273 | atomic_set(&kdump_in_progress, 1); |
1274 | monarch_cpu = -1; | |
1275 | #endif | |
1da177e4 | 1276 | } |
958b166c | 1277 | if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, (long)&nd, 0, recover) |
9138d581 KO |
1278 | == NOTIFY_STOP) |
1279 | ia64_mca_spin(__FUNCTION__); | |
1da177e4 | 1280 | |
1612b18c RA |
1281 | |
1282 | if (atomic_dec_return(&mca_count) > 0) { | |
1283 | int i; | |
1284 | ||
1285 | /* wake up the next monarch cpu, | |
1286 | * and put this cpu in the rendez loop. | |
1287 | */ | |
1612b18c RA |
1288 | for_each_online_cpu(i) { |
1289 | if (cpu_isset(i, mca_cpu)) { | |
1290 | monarch_cpu = i; | |
1291 | cpu_clear(i, mca_cpu); /* wake next cpu */ | |
1292 | while (monarch_cpu != -1) | |
1293 | cpu_relax(); /* spin until last cpu leaves */ | |
1612b18c | 1294 | set_curr_task(cpu, previous_current); |
e1b1eb01 RA |
1295 | ia64_mc_info.imi_rendez_checkin[cpu] |
1296 | = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; | |
1612b18c RA |
1297 | return; |
1298 | } | |
1299 | } | |
1300 | } | |
7f613c7d | 1301 | set_curr_task(cpu, previous_current); |
e1b1eb01 RA |
1302 | ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; |
1303 | monarch_cpu = -1; /* This frees the slaves and previous monarchs */ | |
1da177e4 LT |
1304 | } |
1305 | ||
6d5aefb8 DH |
1306 | static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd); |
1307 | static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd); | |
1da177e4 LT |
1308 | |
1309 | /* | |
1310 | * ia64_mca_cmc_int_handler | |
1311 | * | |
1312 | * This is corrected machine check interrupt handler. | |
1313 | * Right now the logs are extracted and displayed in a well-defined | |
1314 | * format. | |
1315 | * | |
1316 | * Inputs | |
1317 | * interrupt number | |
1318 | * client data arg ptr | |
1da177e4 LT |
1319 | * |
1320 | * Outputs | |
1321 | * None | |
1322 | */ | |
1323 | static irqreturn_t | |
7d12e780 | 1324 | ia64_mca_cmc_int_handler(int cmc_irq, void *arg) |
1da177e4 LT |
1325 | { |
1326 | static unsigned long cmc_history[CMC_HISTORY_LENGTH]; | |
1327 | static int index; | |
1328 | static DEFINE_SPINLOCK(cmc_history_lock); | |
1329 | ||
1330 | IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n", | |
1331 | __FUNCTION__, cmc_irq, smp_processor_id()); | |
1332 | ||
1333 | /* SAL spec states this should run w/ interrupts enabled */ | |
1334 | local_irq_enable(); | |
1335 | ||
1da177e4 LT |
1336 | spin_lock(&cmc_history_lock); |
1337 | if (!cmc_polling_enabled) { | |
1338 | int i, count = 1; /* we know 1 happened now */ | |
1339 | unsigned long now = jiffies; | |
1340 | ||
1341 | for (i = 0; i < CMC_HISTORY_LENGTH; i++) { | |
1342 | if (now - cmc_history[i] <= HZ) | |
1343 | count++; | |
1344 | } | |
1345 | ||
1346 | IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH); | |
1347 | if (count >= CMC_HISTORY_LENGTH) { | |
1348 | ||
1349 | cmc_polling_enabled = 1; | |
1350 | spin_unlock(&cmc_history_lock); | |
76e677e2 BS |
1351 | /* If we're being hit with CMC interrupts, we won't |
1352 | * ever execute the schedule_work() below. Need to | |
1353 | * disable CMC interrupts on this processor now. | |
1354 | */ | |
1355 | ia64_mca_cmc_vector_disable(NULL); | |
1da177e4 LT |
1356 | schedule_work(&cmc_disable_work); |
1357 | ||
1358 | /* | |
1359 | * Corrected errors will still be corrected, but | |
1360 | * make sure there's a log somewhere that indicates | |
1361 | * something is generating more than we can handle. | |
1362 | */ | |
1363 | printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n"); | |
1364 | ||
1365 | mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL); | |
1366 | ||
1367 | /* lock already released, get out now */ | |
ddb4f0df | 1368 | goto out; |
1da177e4 LT |
1369 | } else { |
1370 | cmc_history[index++] = now; | |
1371 | if (index == CMC_HISTORY_LENGTH) | |
1372 | index = 0; | |
1373 | } | |
1374 | } | |
1375 | spin_unlock(&cmc_history_lock); | |
ddb4f0df HS |
1376 | out: |
1377 | /* Get the CMC error record and log it */ | |
1378 | ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC); | |
1379 | ||
1da177e4 LT |
1380 | return IRQ_HANDLED; |
1381 | } | |
1382 | ||
1383 | /* | |
1384 | * ia64_mca_cmc_int_caller | |
1385 | * | |
1386 | * Triggered by sw interrupt from CMC polling routine. Calls | |
1387 | * real interrupt handler and either triggers a sw interrupt | |
1388 | * on the next cpu or does cleanup at the end. | |
1389 | * | |
1390 | * Inputs | |
1391 | * interrupt number | |
1392 | * client data arg ptr | |
1da177e4 LT |
1393 | * Outputs |
1394 | * handled | |
1395 | */ | |
1396 | static irqreturn_t | |
7d12e780 | 1397 | ia64_mca_cmc_int_caller(int cmc_irq, void *arg) |
1da177e4 LT |
1398 | { |
1399 | static int start_count = -1; | |
1400 | unsigned int cpuid; | |
1401 | ||
1402 | cpuid = smp_processor_id(); | |
1403 | ||
1404 | /* If first cpu, update count */ | |
1405 | if (start_count == -1) | |
1406 | start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC); | |
1407 | ||
7d12e780 | 1408 | ia64_mca_cmc_int_handler(cmc_irq, arg); |
1da177e4 LT |
1409 | |
1410 | for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++); | |
1411 | ||
1412 | if (cpuid < NR_CPUS) { | |
1413 | platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0); | |
1414 | } else { | |
1415 | /* If no log record, switch out of polling mode */ | |
1416 | if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) { | |
1417 | ||
1418 | printk(KERN_WARNING "Returning to interrupt driven CMC handler\n"); | |
1419 | schedule_work(&cmc_enable_work); | |
1420 | cmc_polling_enabled = 0; | |
1421 | ||
1422 | } else { | |
1423 | ||
1424 | mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL); | |
1425 | } | |
1426 | ||
1427 | start_count = -1; | |
1428 | } | |
1429 | ||
1430 | return IRQ_HANDLED; | |
1431 | } | |
1432 | ||
1433 | /* | |
1434 | * ia64_mca_cmc_poll | |
1435 | * | |
1436 | * Poll for Corrected Machine Checks (CMCs) | |
1437 | * | |
1438 | * Inputs : dummy(unused) | |
1439 | * Outputs : None | |
1440 | * | |
1441 | */ | |
1442 | static void | |
1443 | ia64_mca_cmc_poll (unsigned long dummy) | |
1444 | { | |
1445 | /* Trigger a CMC interrupt cascade */ | |
1446 | platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0); | |
1447 | } | |
1448 | ||
1449 | /* | |
1450 | * ia64_mca_cpe_int_caller | |
1451 | * | |
1452 | * Triggered by sw interrupt from CPE polling routine. Calls | |
1453 | * real interrupt handler and either triggers a sw interrupt | |
1454 | * on the next cpu or does cleanup at the end. | |
1455 | * | |
1456 | * Inputs | |
1457 | * interrupt number | |
1458 | * client data arg ptr | |
1da177e4 LT |
1459 | * Outputs |
1460 | * handled | |
1461 | */ | |
1462 | #ifdef CONFIG_ACPI | |
1463 | ||
1464 | static irqreturn_t | |
7d12e780 | 1465 | ia64_mca_cpe_int_caller(int cpe_irq, void *arg) |
1da177e4 LT |
1466 | { |
1467 | static int start_count = -1; | |
1468 | static int poll_time = MIN_CPE_POLL_INTERVAL; | |
1469 | unsigned int cpuid; | |
1470 | ||
1471 | cpuid = smp_processor_id(); | |
1472 | ||
1473 | /* If first cpu, update count */ | |
1474 | if (start_count == -1) | |
1475 | start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE); | |
1476 | ||
7d12e780 | 1477 | ia64_mca_cpe_int_handler(cpe_irq, arg); |
1da177e4 LT |
1478 | |
1479 | for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++); | |
1480 | ||
1481 | if (cpuid < NR_CPUS) { | |
1482 | platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0); | |
1483 | } else { | |
1484 | /* | |
1485 | * If a log was recorded, increase our polling frequency, | |
1486 | * otherwise, backoff or return to interrupt mode. | |
1487 | */ | |
1488 | if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) { | |
1489 | poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2); | |
1490 | } else if (cpe_vector < 0) { | |
1491 | poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2); | |
1492 | } else { | |
1493 | poll_time = MIN_CPE_POLL_INTERVAL; | |
1494 | ||
1495 | printk(KERN_WARNING "Returning to interrupt driven CPE handler\n"); | |
1496 | enable_irq(local_vector_to_irq(IA64_CPE_VECTOR)); | |
1497 | cpe_poll_enabled = 0; | |
1498 | } | |
1499 | ||
1500 | if (cpe_poll_enabled) | |
1501 | mod_timer(&cpe_poll_timer, jiffies + poll_time); | |
1502 | start_count = -1; | |
1503 | } | |
1504 | ||
1505 | return IRQ_HANDLED; | |
1506 | } | |
1507 | ||
1da177e4 LT |
1508 | /* |
1509 | * ia64_mca_cpe_poll | |
1510 | * | |
1511 | * Poll for Corrected Platform Errors (CPEs), trigger interrupt | |
1512 | * on first cpu, from there it will trickle through all the cpus. | |
1513 | * | |
1514 | * Inputs : dummy(unused) | |
1515 | * Outputs : None | |
1516 | * | |
1517 | */ | |
1518 | static void | |
1519 | ia64_mca_cpe_poll (unsigned long dummy) | |
1520 | { | |
1521 | /* Trigger a CPE interrupt cascade */ | |
1522 | platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0); | |
1523 | } | |
1524 | ||
b655913b PC |
1525 | #endif /* CONFIG_ACPI */ |
1526 | ||
9138d581 KO |
1527 | static int |
1528 | default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data) | |
1529 | { | |
1530 | int c; | |
1531 | struct task_struct *g, *t; | |
1532 | if (val != DIE_INIT_MONARCH_PROCESS) | |
1533 | return NOTIFY_DONE; | |
311f594d JL |
1534 | #ifdef CONFIG_KEXEC |
1535 | if (atomic_read(&kdump_in_progress)) | |
1536 | return NOTIFY_DONE; | |
1537 | #endif | |
43ed3baf HS |
1538 | |
1539 | /* | |
1540 | * FIXME: mlogbuf will brim over with INIT stack dumps. | |
1541 | * To enable show_stack from INIT, we use oops_in_progress which should | |
1542 | * be used in real oops. This would cause something wrong after INIT. | |
1543 | */ | |
1544 | BREAK_LOGLEVEL(console_loglevel); | |
1545 | ia64_mlogbuf_dump_from_init(); | |
1546 | ||
9138d581 KO |
1547 | printk(KERN_ERR "Processes interrupted by INIT -"); |
1548 | for_each_online_cpu(c) { | |
1549 | struct ia64_sal_os_state *s; | |
1550 | t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET); | |
1551 | s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET); | |
1552 | g = s->prev_task; | |
1553 | if (g) { | |
1554 | if (g->pid) | |
1555 | printk(" %d", g->pid); | |
1556 | else | |
1557 | printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g); | |
1558 | } | |
1559 | } | |
1560 | printk("\n\n"); | |
1561 | if (read_trylock(&tasklist_lock)) { | |
1562 | do_each_thread (g, t) { | |
1563 | printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm); | |
1564 | show_stack(t, NULL); | |
1565 | } while_each_thread (g, t); | |
1566 | read_unlock(&tasklist_lock); | |
1567 | } | |
43ed3baf HS |
1568 | /* FIXME: This will not restore zapped printk locks. */ |
1569 | RESTORE_LOGLEVEL(console_loglevel); | |
9138d581 KO |
1570 | return NOTIFY_DONE; |
1571 | } | |
1572 | ||
1da177e4 LT |
1573 | /* |
1574 | * C portion of the OS INIT handler | |
1575 | * | |
7f613c7d | 1576 | * Called from ia64_os_init_dispatch |
1da177e4 | 1577 | * |
7f613c7d KO |
1578 | * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for |
1579 | * this event. This code is used for both monarch and slave INIT events, see | |
1580 | * sos->monarch. | |
1da177e4 | 1581 | * |
7f613c7d KO |
1582 | * All INIT events switch to the INIT stack and change the previous process to |
1583 | * blocked status. If one of the INIT events is the monarch then we are | |
1584 | * probably processing the nmi button/command. Use the monarch cpu to dump all | |
1585 | * the processes. The slave INIT events all spin until the monarch cpu | |
1586 | * returns. We can also get INIT slave events for MCA, in which case the MCA | |
1587 | * process is the monarch. | |
1da177e4 | 1588 | */ |
7f613c7d | 1589 | |
1da177e4 | 1590 | void |
7f613c7d KO |
1591 | ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw, |
1592 | struct ia64_sal_os_state *sos) | |
1da177e4 | 1593 | { |
7f613c7d KO |
1594 | static atomic_t slaves; |
1595 | static atomic_t monarchs; | |
36c8b586 | 1596 | struct task_struct *previous_current; |
9138d581 | 1597 | int cpu = smp_processor_id(); |
958b166c KO |
1598 | struct ia64_mca_notify_die nd = |
1599 | { .sos = sos, .monarch_cpu = &monarch_cpu }; | |
1da177e4 | 1600 | |
958b166c KO |
1601 | (void) notify_die(DIE_INIT_ENTER, "INIT", regs, (long)&nd, 0, 0); |
1602 | ||
43ed3baf | 1603 | mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n", |
7f613c7d KO |
1604 | sos->proc_state_param, cpu, sos->monarch); |
1605 | salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0); | |
1da177e4 | 1606 | |
7f613c7d KO |
1607 | previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT"); |
1608 | sos->os_status = IA64_INIT_RESUME; | |
1609 | ||
1610 | /* FIXME: Workaround for broken proms that drive all INIT events as | |
1611 | * slaves. The last slave that enters is promoted to be a monarch. | |
1612 | * Remove this code in September 2006, that gives platforms a year to | |
1613 | * fix their proms and get their customers updated. | |
1da177e4 | 1614 | */ |
7f613c7d | 1615 | if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) { |
43ed3baf | 1616 | mprintk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n", |
7f613c7d KO |
1617 | __FUNCTION__, cpu); |
1618 | atomic_dec(&slaves); | |
1619 | sos->monarch = 1; | |
1620 | } | |
1da177e4 | 1621 | |
7f613c7d KO |
1622 | /* FIXME: Workaround for broken proms that drive all INIT events as |
1623 | * monarchs. Second and subsequent monarchs are demoted to slaves. | |
1624 | * Remove this code in September 2006, that gives platforms a year to | |
1625 | * fix their proms and get their customers updated. | |
1626 | */ | |
1627 | if (sos->monarch && atomic_add_return(1, &monarchs) > 1) { | |
43ed3baf | 1628 | mprintk(KERN_WARNING "%s: Demoting cpu %d to slave.\n", |
7f613c7d KO |
1629 | __FUNCTION__, cpu); |
1630 | atomic_dec(&monarchs); | |
1631 | sos->monarch = 0; | |
1632 | } | |
1633 | ||
1634 | if (!sos->monarch) { | |
1635 | ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT; | |
1636 | while (monarch_cpu == -1) | |
1637 | cpu_relax(); /* spin until monarch enters */ | |
958b166c | 1638 | if (notify_die(DIE_INIT_SLAVE_ENTER, "INIT", regs, (long)&nd, 0, 0) |
9138d581 KO |
1639 | == NOTIFY_STOP) |
1640 | ia64_mca_spin(__FUNCTION__); | |
958b166c | 1641 | if (notify_die(DIE_INIT_SLAVE_PROCESS, "INIT", regs, (long)&nd, 0, 0) |
9138d581 KO |
1642 | == NOTIFY_STOP) |
1643 | ia64_mca_spin(__FUNCTION__); | |
7f613c7d KO |
1644 | while (monarch_cpu != -1) |
1645 | cpu_relax(); /* spin until monarch leaves */ | |
958b166c | 1646 | if (notify_die(DIE_INIT_SLAVE_LEAVE, "INIT", regs, (long)&nd, 0, 0) |
9138d581 KO |
1647 | == NOTIFY_STOP) |
1648 | ia64_mca_spin(__FUNCTION__); | |
43ed3baf | 1649 | mprintk("Slave on cpu %d returning to normal service.\n", cpu); |
7f613c7d KO |
1650 | set_curr_task(cpu, previous_current); |
1651 | ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; | |
1652 | atomic_dec(&slaves); | |
1653 | return; | |
1654 | } | |
1655 | ||
1656 | monarch_cpu = cpu; | |
958b166c | 1657 | if (notify_die(DIE_INIT_MONARCH_ENTER, "INIT", regs, (long)&nd, 0, 0) |
9138d581 KO |
1658 | == NOTIFY_STOP) |
1659 | ia64_mca_spin(__FUNCTION__); | |
7f613c7d KO |
1660 | |
1661 | /* | |
1662 | * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be | |
1663 | * generated via the BMC's command-line interface, but since the console is on the | |
1664 | * same serial line, the user will need some time to switch out of the BMC before | |
1665 | * the dump begins. | |
1666 | */ | |
43ed3baf | 1667 | mprintk("Delaying for 5 seconds...\n"); |
7f613c7d | 1668 | udelay(5*1000000); |
356a5c1c | 1669 | ia64_wait_for_slaves(cpu, "INIT"); |
9138d581 KO |
1670 | /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through |
1671 | * to default_monarch_init_process() above and just print all the | |
1672 | * tasks. | |
1673 | */ | |
958b166c | 1674 | if (notify_die(DIE_INIT_MONARCH_PROCESS, "INIT", regs, (long)&nd, 0, 0) |
9138d581 KO |
1675 | == NOTIFY_STOP) |
1676 | ia64_mca_spin(__FUNCTION__); | |
958b166c | 1677 | if (notify_die(DIE_INIT_MONARCH_LEAVE, "INIT", regs, (long)&nd, 0, 0) |
9138d581 KO |
1678 | == NOTIFY_STOP) |
1679 | ia64_mca_spin(__FUNCTION__); | |
43ed3baf | 1680 | mprintk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu); |
7f613c7d KO |
1681 | atomic_dec(&monarchs); |
1682 | set_curr_task(cpu, previous_current); | |
1683 | monarch_cpu = -1; | |
1684 | return; | |
1da177e4 LT |
1685 | } |
1686 | ||
1687 | static int __init | |
1688 | ia64_mca_disable_cpe_polling(char *str) | |
1689 | { | |
1690 | cpe_poll_enabled = 0; | |
1691 | return 1; | |
1692 | } | |
1693 | ||
1694 | __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling); | |
1695 | ||
1696 | static struct irqaction cmci_irqaction = { | |
1697 | .handler = ia64_mca_cmc_int_handler, | |
121a4226 | 1698 | .flags = IRQF_DISABLED, |
1da177e4 LT |
1699 | .name = "cmc_hndlr" |
1700 | }; | |
1701 | ||
1702 | static struct irqaction cmcp_irqaction = { | |
1703 | .handler = ia64_mca_cmc_int_caller, | |
121a4226 | 1704 | .flags = IRQF_DISABLED, |
1da177e4 LT |
1705 | .name = "cmc_poll" |
1706 | }; | |
1707 | ||
1708 | static struct irqaction mca_rdzv_irqaction = { | |
1709 | .handler = ia64_mca_rendez_int_handler, | |
121a4226 | 1710 | .flags = IRQF_DISABLED, |
1da177e4 LT |
1711 | .name = "mca_rdzv" |
1712 | }; | |
1713 | ||
1714 | static struct irqaction mca_wkup_irqaction = { | |
1715 | .handler = ia64_mca_wakeup_int_handler, | |
121a4226 | 1716 | .flags = IRQF_DISABLED, |
1da177e4 LT |
1717 | .name = "mca_wkup" |
1718 | }; | |
1719 | ||
1720 | #ifdef CONFIG_ACPI | |
1721 | static struct irqaction mca_cpe_irqaction = { | |
1722 | .handler = ia64_mca_cpe_int_handler, | |
121a4226 | 1723 | .flags = IRQF_DISABLED, |
1da177e4 LT |
1724 | .name = "cpe_hndlr" |
1725 | }; | |
1726 | ||
1727 | static struct irqaction mca_cpep_irqaction = { | |
1728 | .handler = ia64_mca_cpe_int_caller, | |
121a4226 | 1729 | .flags = IRQF_DISABLED, |
1da177e4 LT |
1730 | .name = "cpe_poll" |
1731 | }; | |
1732 | #endif /* CONFIG_ACPI */ | |
1733 | ||
7f613c7d KO |
1734 | /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on |
1735 | * these stacks can never sleep, they cannot return from the kernel to user | |
1736 | * space, they do not appear in a normal ps listing. So there is no need to | |
1737 | * format most of the fields. | |
1738 | */ | |
1739 | ||
0881fc8d | 1740 | static void __cpuinit |
7f613c7d KO |
1741 | format_mca_init_stack(void *mca_data, unsigned long offset, |
1742 | const char *type, int cpu) | |
1743 | { | |
1744 | struct task_struct *p = (struct task_struct *)((char *)mca_data + offset); | |
1745 | struct thread_info *ti; | |
1746 | memset(p, 0, KERNEL_STACK_SIZE); | |
ab03591d | 1747 | ti = task_thread_info(p); |
7f613c7d KO |
1748 | ti->flags = _TIF_MCA_INIT; |
1749 | ti->preempt_count = 1; | |
1750 | ti->task = p; | |
1751 | ti->cpu = cpu; | |
f7e4217b | 1752 | p->stack = ti; |
7f613c7d | 1753 | p->state = TASK_UNINTERRUPTIBLE; |
4668f0cd | 1754 | cpu_set(cpu, p->cpus_allowed); |
7f613c7d KO |
1755 | INIT_LIST_HEAD(&p->tasks); |
1756 | p->parent = p->real_parent = p->group_leader = p; | |
1757 | INIT_LIST_HEAD(&p->children); | |
1758 | INIT_LIST_HEAD(&p->sibling); | |
1759 | strncpy(p->comm, type, sizeof(p->comm)-1); | |
1760 | } | |
1761 | ||
056e6d89 SR |
1762 | /* Caller prevents this from being called after init */ |
1763 | static void * __init_refok mca_bootmem(void) | |
1764 | { | |
1765 | void *p; | |
1da177e4 | 1766 | |
056e6d89 SR |
1767 | p = alloc_bootmem(sizeof(struct ia64_mca_cpu) * NR_CPUS + |
1768 | KERNEL_STACK_SIZE); | |
1769 | return (void *)ALIGN((unsigned long)p, KERNEL_STACK_SIZE); | |
1770 | } | |
1771 | ||
1772 | /* Do per-CPU MCA-related initialization. */ | |
0881fc8d | 1773 | void __cpuinit |
1da177e4 LT |
1774 | ia64_mca_cpu_init(void *cpu_data) |
1775 | { | |
1776 | void *pal_vaddr; | |
ff741906 | 1777 | static int first_time = 1; |
1da177e4 | 1778 | |
ff741906 | 1779 | if (first_time) { |
1da177e4 LT |
1780 | void *mca_data; |
1781 | int cpu; | |
1782 | ||
ff741906 | 1783 | first_time = 0; |
056e6d89 | 1784 | mca_data = mca_bootmem(); |
1da177e4 | 1785 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
7f613c7d KO |
1786 | format_mca_init_stack(mca_data, |
1787 | offsetof(struct ia64_mca_cpu, mca_stack), | |
1788 | "MCA", cpu); | |
1789 | format_mca_init_stack(mca_data, | |
1790 | offsetof(struct ia64_mca_cpu, init_stack), | |
1791 | "INIT", cpu); | |
1da177e4 LT |
1792 | __per_cpu_mca[cpu] = __pa(mca_data); |
1793 | mca_data += sizeof(struct ia64_mca_cpu); | |
1794 | } | |
1795 | } | |
1796 | ||
7f613c7d KO |
1797 | /* |
1798 | * The MCA info structure was allocated earlier and its | |
1799 | * physical address saved in __per_cpu_mca[cpu]. Copy that | |
1800 | * address * to ia64_mca_data so we can access it as a per-CPU | |
1801 | * variable. | |
1802 | */ | |
1da177e4 LT |
1803 | __get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()]; |
1804 | ||
1805 | /* | |
1806 | * Stash away a copy of the PTE needed to map the per-CPU page. | |
1807 | * We may need it during MCA recovery. | |
1808 | */ | |
1809 | __get_cpu_var(ia64_mca_per_cpu_pte) = | |
1810 | pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL)); | |
1811 | ||
7f613c7d KO |
1812 | /* |
1813 | * Also, stash away a copy of the PAL address and the PTE | |
1814 | * needed to map it. | |
1815 | */ | |
1816 | pal_vaddr = efi_get_pal_addr(); | |
1da177e4 LT |
1817 | if (!pal_vaddr) |
1818 | return; | |
1819 | __get_cpu_var(ia64_mca_pal_base) = | |
1820 | GRANULEROUNDDOWN((unsigned long) pal_vaddr); | |
1821 | __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr), | |
1822 | PAGE_KERNEL)); | |
1823 | } | |
1824 | ||
ed5d4026 HS |
1825 | static void __cpuinit ia64_mca_cmc_vector_adjust(void *dummy) |
1826 | { | |
1827 | unsigned long flags; | |
1828 | ||
1829 | local_irq_save(flags); | |
1830 | if (!cmc_polling_enabled) | |
1831 | ia64_mca_cmc_vector_enable(NULL); | |
1832 | local_irq_restore(flags); | |
1833 | } | |
1834 | ||
1835 | static int __cpuinit mca_cpu_callback(struct notifier_block *nfb, | |
1836 | unsigned long action, | |
1837 | void *hcpu) | |
1838 | { | |
1839 | int hotcpu = (unsigned long) hcpu; | |
1840 | ||
1841 | switch (action) { | |
1842 | case CPU_ONLINE: | |
1843 | case CPU_ONLINE_FROZEN: | |
1844 | smp_call_function_single(hotcpu, ia64_mca_cmc_vector_adjust, | |
1845 | NULL, 1, 0); | |
1846 | break; | |
1847 | } | |
1848 | return NOTIFY_OK; | |
1849 | } | |
1850 | ||
1851 | static struct notifier_block mca_cpu_notifier __cpuinitdata = { | |
1852 | .notifier_call = mca_cpu_callback | |
1853 | }; | |
1854 | ||
1da177e4 LT |
1855 | /* |
1856 | * ia64_mca_init | |
1857 | * | |
1858 | * Do all the system level mca specific initialization. | |
1859 | * | |
1860 | * 1. Register spinloop and wakeup request interrupt vectors | |
1861 | * | |
1862 | * 2. Register OS_MCA handler entry point | |
1863 | * | |
1864 | * 3. Register OS_INIT handler entry point | |
1865 | * | |
1866 | * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS. | |
1867 | * | |
1868 | * Note that this initialization is done very early before some kernel | |
1869 | * services are available. | |
1870 | * | |
1871 | * Inputs : None | |
1872 | * | |
1873 | * Outputs : None | |
1874 | */ | |
1875 | void __init | |
1876 | ia64_mca_init(void) | |
1877 | { | |
7f613c7d KO |
1878 | ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch; |
1879 | ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave; | |
1da177e4 LT |
1880 | ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch; |
1881 | int i; | |
1882 | s64 rc; | |
1883 | struct ia64_sal_retval isrv; | |
1884 | u64 timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */ | |
9138d581 KO |
1885 | static struct notifier_block default_init_monarch_nb = { |
1886 | .notifier_call = default_monarch_init_process, | |
1887 | .priority = 0/* we need to notified last */ | |
1888 | }; | |
1da177e4 LT |
1889 | |
1890 | IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__); | |
1891 | ||
1892 | /* Clear the Rendez checkin flag for all cpus */ | |
1893 | for(i = 0 ; i < NR_CPUS; i++) | |
1894 | ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; | |
1895 | ||
1896 | /* | |
1897 | * Register the rendezvous spinloop and wakeup mechanism with SAL | |
1898 | */ | |
1899 | ||
1900 | /* Register the rendezvous interrupt vector with SAL */ | |
1901 | while (1) { | |
1902 | isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT, | |
1903 | SAL_MC_PARAM_MECHANISM_INT, | |
1904 | IA64_MCA_RENDEZ_VECTOR, | |
1905 | timeout, | |
1906 | SAL_MC_PARAM_RZ_ALWAYS); | |
1907 | rc = isrv.status; | |
1908 | if (rc == 0) | |
1909 | break; | |
1910 | if (rc == -2) { | |
1911 | printk(KERN_INFO "Increasing MCA rendezvous timeout from " | |
1912 | "%ld to %ld milliseconds\n", timeout, isrv.v0); | |
1913 | timeout = isrv.v0; | |
958b166c | 1914 | (void) notify_die(DIE_MCA_NEW_TIMEOUT, "MCA", NULL, timeout, 0, 0); |
1da177e4 LT |
1915 | continue; |
1916 | } | |
1917 | printk(KERN_ERR "Failed to register rendezvous interrupt " | |
1918 | "with SAL (status %ld)\n", rc); | |
1919 | return; | |
1920 | } | |
1921 | ||
1922 | /* Register the wakeup interrupt vector with SAL */ | |
1923 | isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP, | |
1924 | SAL_MC_PARAM_MECHANISM_INT, | |
1925 | IA64_MCA_WAKEUP_VECTOR, | |
1926 | 0, 0); | |
1927 | rc = isrv.status; | |
1928 | if (rc) { | |
1929 | printk(KERN_ERR "Failed to register wakeup interrupt with SAL " | |
1930 | "(status %ld)\n", rc); | |
1931 | return; | |
1932 | } | |
1933 | ||
1934 | IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__); | |
1935 | ||
1936 | ia64_mc_info.imi_mca_handler = ia64_tpa(mca_hldlr_ptr->fp); | |
1937 | /* | |
1938 | * XXX - disable SAL checksum by setting size to 0; should be | |
1939 | * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch); | |
1940 | */ | |
1941 | ia64_mc_info.imi_mca_handler_size = 0; | |
1942 | ||
1943 | /* Register the os mca handler with SAL */ | |
1944 | if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA, | |
1945 | ia64_mc_info.imi_mca_handler, | |
1946 | ia64_tpa(mca_hldlr_ptr->gp), | |
1947 | ia64_mc_info.imi_mca_handler_size, | |
1948 | 0, 0, 0))) | |
1949 | { | |
1950 | printk(KERN_ERR "Failed to register OS MCA handler with SAL " | |
1951 | "(status %ld)\n", rc); | |
1952 | return; | |
1953 | } | |
1954 | ||
1955 | IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__, | |
1956 | ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp)); | |
1957 | ||
1958 | /* | |
1959 | * XXX - disable SAL checksum by setting size to 0, should be | |
1960 | * size of the actual init handler in mca_asm.S. | |
1961 | */ | |
7f613c7d | 1962 | ia64_mc_info.imi_monarch_init_handler = ia64_tpa(init_hldlr_ptr_monarch->fp); |
1da177e4 | 1963 | ia64_mc_info.imi_monarch_init_handler_size = 0; |
7f613c7d | 1964 | ia64_mc_info.imi_slave_init_handler = ia64_tpa(init_hldlr_ptr_slave->fp); |
1da177e4 LT |
1965 | ia64_mc_info.imi_slave_init_handler_size = 0; |
1966 | ||
1967 | IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__, | |
1968 | ia64_mc_info.imi_monarch_init_handler); | |
1969 | ||
1970 | /* Register the os init handler with SAL */ | |
1971 | if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT, | |
1972 | ia64_mc_info.imi_monarch_init_handler, | |
1973 | ia64_tpa(ia64_getreg(_IA64_REG_GP)), | |
1974 | ia64_mc_info.imi_monarch_init_handler_size, | |
1975 | ia64_mc_info.imi_slave_init_handler, | |
1976 | ia64_tpa(ia64_getreg(_IA64_REG_GP)), | |
1977 | ia64_mc_info.imi_slave_init_handler_size))) | |
1978 | { | |
1979 | printk(KERN_ERR "Failed to register m/s INIT handlers with SAL " | |
1980 | "(status %ld)\n", rc); | |
1981 | return; | |
1982 | } | |
9138d581 KO |
1983 | if (register_die_notifier(&default_init_monarch_nb)) { |
1984 | printk(KERN_ERR "Failed to register default monarch INIT process\n"); | |
1985 | return; | |
1986 | } | |
1da177e4 LT |
1987 | |
1988 | IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__); | |
1989 | ||
1990 | /* | |
1991 | * Configure the CMCI/P vector and handler. Interrupts for CMC are | |
1992 | * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c). | |
1993 | */ | |
1994 | register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction); | |
1995 | register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction); | |
1996 | ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */ | |
1997 | ||
1998 | /* Setup the MCA rendezvous interrupt vector */ | |
1999 | register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction); | |
2000 | ||
2001 | /* Setup the MCA wakeup interrupt vector */ | |
2002 | register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction); | |
2003 | ||
2004 | #ifdef CONFIG_ACPI | |
bb68c12b | 2005 | /* Setup the CPEI/P handler */ |
1da177e4 LT |
2006 | register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction); |
2007 | #endif | |
2008 | ||
2009 | /* Initialize the areas set aside by the OS to buffer the | |
2010 | * platform/processor error states for MCA/INIT/CMC | |
2011 | * handling. | |
2012 | */ | |
2013 | ia64_log_init(SAL_INFO_TYPE_MCA); | |
2014 | ia64_log_init(SAL_INFO_TYPE_INIT); | |
2015 | ia64_log_init(SAL_INFO_TYPE_CMC); | |
2016 | ia64_log_init(SAL_INFO_TYPE_CPE); | |
2017 | ||
2018 | mca_init = 1; | |
2019 | printk(KERN_INFO "MCA related initialization done\n"); | |
2020 | } | |
2021 | ||
2022 | /* | |
2023 | * ia64_mca_late_init | |
2024 | * | |
2025 | * Opportunity to setup things that require initialization later | |
2026 | * than ia64_mca_init. Setup a timer to poll for CPEs if the | |
2027 | * platform doesn't support an interrupt driven mechanism. | |
2028 | * | |
2029 | * Inputs : None | |
2030 | * Outputs : Status | |
2031 | */ | |
2032 | static int __init | |
2033 | ia64_mca_late_init(void) | |
2034 | { | |
2035 | if (!mca_init) | |
2036 | return 0; | |
2037 | ||
ed5d4026 HS |
2038 | register_hotcpu_notifier(&mca_cpu_notifier); |
2039 | ||
1da177e4 LT |
2040 | /* Setup the CMCI/P vector and handler */ |
2041 | init_timer(&cmc_poll_timer); | |
2042 | cmc_poll_timer.function = ia64_mca_cmc_poll; | |
2043 | ||
2044 | /* Unmask/enable the vector */ | |
2045 | cmc_polling_enabled = 0; | |
2046 | schedule_work(&cmc_enable_work); | |
2047 | ||
2048 | IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__); | |
2049 | ||
2050 | #ifdef CONFIG_ACPI | |
2051 | /* Setup the CPEI/P vector and handler */ | |
bb68c12b | 2052 | cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI); |
1da177e4 LT |
2053 | init_timer(&cpe_poll_timer); |
2054 | cpe_poll_timer.function = ia64_mca_cpe_poll; | |
2055 | ||
2056 | { | |
2057 | irq_desc_t *desc; | |
2058 | unsigned int irq; | |
2059 | ||
2060 | if (cpe_vector >= 0) { | |
2061 | /* If platform supports CPEI, enable the irq. */ | |
a1287476 RA |
2062 | irq = local_vector_to_irq(cpe_vector); |
2063 | if (irq > 0) { | |
2064 | cpe_poll_enabled = 0; | |
2065 | desc = irq_desc + irq; | |
2066 | desc->status |= IRQ_PER_CPU; | |
2067 | setup_irq(irq, &mca_cpe_irqaction); | |
2068 | ia64_cpe_irq = irq; | |
2069 | ia64_mca_register_cpev(cpe_vector); | |
2070 | IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", | |
2071 | __FUNCTION__); | |
2072 | return 0; | |
1da177e4 | 2073 | } |
a1287476 RA |
2074 | printk(KERN_ERR "%s: Failed to find irq for CPE " |
2075 | "interrupt handler, vector %d\n", | |
2076 | __FUNCTION__, cpe_vector); | |
2077 | } | |
2078 | /* If platform doesn't support CPEI, get the timer going. */ | |
2079 | if (cpe_poll_enabled) { | |
2080 | ia64_mca_cpe_poll(0UL); | |
2081 | IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__); | |
1da177e4 LT |
2082 | } |
2083 | } | |
2084 | #endif | |
2085 | ||
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | device_initcall(ia64_mca_late_init); |