[linux-2.6-block.git] / arch / ia64 / kernel / irq_ia64.c

// SPDX-License-Identifier: GPL-2.0
/*
 * linux/arch/ia64/kernel/irq_ia64.c
 *
 * Copyright (C) 1998-2001 Hewlett-Packard Co
 *	Stephane Eranian <eranian@hpl.hp.com>
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 *  6/10/99: Updated to bring in sync with x86 version to facilitate
 *	     support for SMP and different interrupt controllers.
 *
 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
 *                      PCI to vector allocation routine.
 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
 *						Added CPU Hotplug handling for IPF.
 */

#include <linux/module.h>

#include <linux/jiffies.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>
#include <linux/ptrace.h>
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/ratelimit.h>
#include <linux/acpi.h>
#include <linux/sched.h>

#include <asm/delay.h>
#include <asm/intrinsics.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>

#ifdef CONFIG_PERFMON
# include <asm/perfmon.h>
#endif

#define IRQ_DEBUG	0

#define IRQ_VECTOR_UNASSIGNED	(0)

#define IRQ_UNUSED		(0)
#define IRQ_USED		(1)
#define IRQ_RSVD		(2)

int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;

/* default base addr of IPI table */
void __iomem *ipi_base_addr = ((void __iomem *)
			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));

static cpumask_t vector_allocation_domain(int cpu);

/*
 * Legacy IRQ to IA-64 vector translation table.
 */
__u8 isa_irq_to_vector_map[16] = {
	/* 8259 IRQ translation, first 16 entries */
	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
};
EXPORT_SYMBOL(isa_irq_to_vector_map);

DEFINE_SPINLOCK(vector_lock);

struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
	[0 ... NR_IRQS - 1] = {
		.vector = IRQ_VECTOR_UNASSIGNED,
		.domain = CPU_MASK_NONE
	}
};

DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	[0 ... IA64_NUM_VECTORS - 1] = -1
};

static cpumask_t vector_table[IA64_NUM_VECTORS] = {
	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
};

static int irq_status[NR_IRQS] = {
	[0 ... NR_IRQS -1] = IRQ_UNUSED
};

static inline int find_unassigned_irq(void)
{
	int irq;

	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
		if (irq_status[irq] == IRQ_UNUSED)
			return irq;
	return -ENOSPC;
}

static inline int find_unassigned_vector(cpumask_t domain)
{
	cpumask_t mask;
	int pos, vector;

	cpumask_and(&mask, &domain, cpu_online_mask);
	if (cpumask_empty(&mask))
		return -EINVAL;

	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
		vector = IA64_FIRST_DEVICE_VECTOR + pos;
		cpumask_and(&mask, &domain, &vector_table[vector]);
		if (!cpumask_empty(&mask))
			continue;
		return vector;
	}
	return -ENOSPC;
}

static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	cpumask_t mask;
	int cpu;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);

	cpumask_and(&mask, &domain, cpu_online_mask);
	if (cpumask_empty(&mask))
		return -EINVAL;
	if ((cfg->vector == vector) && cpumask_equal(&cfg->domain, &domain))
		return 0;
	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
		return -EBUSY;
	for_each_cpu(cpu, &mask)
		per_cpu(vector_irq, cpu)[vector] = irq;
	cfg->vector = vector;
	cfg->domain = domain;
	irq_status[irq] = IRQ_USED;
	cpumask_or(&vector_table[vector], &vector_table[vector], &domain);
	return 0;
}

int bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __bind_irq_vector(irq, vector, domain);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

static void __clear_irq_vector(int irq)
{
	int vector, cpu;
	cpumask_t domain;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	vector = cfg->vector;
	domain = cfg->domain;
	for_each_cpu_and(cpu, &cfg->domain, cpu_online_mask)
		per_cpu(vector_irq, cpu)[vector] = -1;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	irq_status[irq] = IRQ_UNUSED;
	cpumask_andnot(&vector_table[vector], &vector_table[vector], &domain);
}

static void clear_irq_vector(int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	spin_unlock_irqrestore(&vector_lock, flags);
}

int
ia64_native_assign_irq_vector (int irq)
{
	unsigned long flags;
	int vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	vector = -ENOSPC;

	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	if (irq == AUTO_ASSIGN)
		irq = vector;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	return vector;
}

void
ia64_native_free_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return;
	clear_irq_vector(vector);
}

int
reserve_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return -EINVAL;
	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
}

/*
 * Initialize vector_irq on a new cpu. This function must be called
 * with vector_lock held.
 */
void __setup_vector_irq(int cpu)
{
	int irq, vector;

	/* Clear vector_irq */
	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
		per_cpu(vector_irq, cpu)[vector] = -1;
	/* Mark the inuse vectors */
	for (irq = 0; irq < NR_IRQS; ++irq) {
		if (!cpumask_test_cpu(cpu, &irq_cfg[irq].domain))
			continue;
		vector = irq_to_vector(irq);
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
}

#ifdef CONFIG_SMP

static enum vector_domain_type {
	VECTOR_DOMAIN_NONE,
	VECTOR_DOMAIN_PERCPU
} vector_domain_type = VECTOR_DOMAIN_NONE;

static cpumask_t vector_allocation_domain(int cpu)
{
	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
		return *cpumask_of(cpu);
	return CPU_MASK_ALL;
}

static int __irq_prepare_move(int irq, int cpu)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	int vector;
	cpumask_t domain;

	if (cfg->move_in_progress || cfg->move_cleanup_count)
		return -EBUSY;
	if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
		return -EINVAL;
	if (cpumask_test_cpu(cpu, &cfg->domain))
		return 0;
	domain = vector_allocation_domain(cpu);
	vector = find_unassigned_vector(domain);
	if (vector < 0)
		return -ENOSPC;
	cfg->move_in_progress = 1;
	cfg->old_domain = cfg->domain;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
	return 0;
}

int irq_prepare_move(int irq, int cpu)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __irq_prepare_move(irq, cpu);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

void irq_complete_move(unsigned irq)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	cpumask_t cleanup_mask;
	int i;

	if (likely(!cfg->move_in_progress))
		return;

	if (unlikely(cpumask_test_cpu(smp_processor_id(), &cfg->old_domain)))
		return;

	cpumask_and(&cleanup_mask, &cfg->old_domain, cpu_online_mask);
	cfg->move_cleanup_count = cpumask_weight(&cleanup_mask);
	for_each_cpu(i, &cleanup_mask)
		ia64_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	cfg->move_in_progress = 0;
}

static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
{
	int me = smp_processor_id();
	ia64_vector vector;
	unsigned long flags;

	for (vector = IA64_FIRST_DEVICE_VECTOR;
	     vector < IA64_LAST_DEVICE_VECTOR; vector++) {
		int irq;
		struct irq_desc *desc;
		struct irq_cfg *cfg;
		irq = __this_cpu_read(vector_irq[vector]);
		if (irq < 0)
			continue;

		desc = irq_to_desc(irq);
		cfg = irq_cfg + irq;
		raw_spin_lock(&desc->lock);
		if (!cfg->move_cleanup_count)
			goto unlock;

		if (!cpumask_test_cpu(me, &cfg->old_domain))
			goto unlock;

		spin_lock_irqsave(&vector_lock, flags);
		__this_cpu_write(vector_irq[vector], -1);
		cpumask_clear_cpu(me, &vector_table[vector]);
		spin_unlock_irqrestore(&vector_lock, flags);
		cfg->move_cleanup_count--;
	unlock:
		raw_spin_unlock(&desc->lock);
	}
	return IRQ_HANDLED;
}

static struct irqaction irq_move_irqaction = {
	.handler =	smp_irq_move_cleanup_interrupt,
	.name =		"irq_move"
};

static int __init parse_vector_domain(char *arg)
{
	if (!arg)
		return -EINVAL;
	if (!strcmp(arg, "percpu")) {
		vector_domain_type = VECTOR_DOMAIN_PERCPU;
		no_int_routing = 1;
	}
	return 0;
}
early_param("vector", parse_vector_domain);
#else
static cpumask_t vector_allocation_domain(int cpu)
{
	return CPU_MASK_ALL;
}
#endif


void destroy_and_reserve_irq(unsigned int irq)
{
	unsigned long flags;

	irq_init_desc(irq);
	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	irq_status[irq] = IRQ_RSVD;
	spin_unlock_irqrestore(&vector_lock, flags);
}

/*
 * Dynamic irq allocate and deallocation for MSI
 */
int create_irq(void)
{
	unsigned long flags;
	int irq, vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	irq = vector = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	irq = find_unassigned_irq();
	if (irq < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	if (irq >= 0)
		irq_init_desc(irq);
	return irq;
}

void destroy_irq(unsigned int irq)
{
	irq_init_desc(irq);
	clear_irq_vector(irq);
}

#ifdef CONFIG_SMP
#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
#	define IS_LOCAL_TLB_FLUSH(vec)	(vec == IA64_IPI_LOCAL_TLB_FLUSH)
#else
#	define IS_RESCHEDULE(vec)	(0)
#	define IS_LOCAL_TLB_FLUSH(vec)	(0)
#endif
/*
 * That's where the IVT branches when we get an external
 * interrupt. This branches to the correct hardware IRQ handler via
 * function ptr.
 */
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	unsigned long saved_tpr;

#if IRQ_DEBUG
	{
		unsigned long bsp, sp;

		/*
		 * Note: if the interrupt happened while executing in
		 * the context switch routine (ia64_switch_to), we may
		 * get a spurious stack overflow here.  This is
		 * because the register and the memory stack are not
		 * switched atomically.
		 */
		bsp = ia64_getreg(_IA64_REG_AR_BSP);
		sp = ia64_getreg(_IA64_REG_SP);

		if ((sp - bsp) < 1024) {
			static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);

			if (__ratelimit(&ratelimit)) {
				printk("ia64_handle_irq: DANGER: less than "
				       "1KB of free stack space!!\n"
				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
			}
		}
	}
#endif /* IRQ_DEBUG */

	/*
	 * Always set TPR to limit maximum interrupt nesting depth to
	 * 16 (without this, it would be ~240, which could easily lead
	 * to kernel stack overflows).
	 */
	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irq_this_cpu(irq);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			scheduler_ipi();
			kstat_incr_irq_this_cpu(irq);
		} else {
			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d is not mapped "
				       "to any IRQ!\n", __func__, vector,
				       smp_processor_id());
			} else
				generic_handle_irq(irq);

			/*
			 * Disable interrupts and send EOI:
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	/*
	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
	 * handler needs to be able to wait for further keyboard interrupts, which can't
	 * come through until ia64_eoi() has been done.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}

#ifdef CONFIG_HOTPLUG_CPU
/*
 * This function emulates a interrupt processing when a cpu is about to be
 * brought down.
 */
void ia64_process_pending_intr(void)
{
	ia64_vector vector;
	unsigned long saved_tpr;
	extern unsigned int vectors_in_migration[NR_IRQS];

	vector = ia64_get_ivr();

	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();

	 /*
	  * Perform normal interrupt style processing
	  */
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irq_this_cpu(irq);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			kstat_incr_irq_this_cpu(irq);
		} else {
			struct pt_regs *old_regs = set_irq_regs(NULL);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			/*
			 * Now try calling normal ia64_handle_irq as it would have got called
			 * from a real intr handler. Try passing null for pt_regs, hopefully
			 * it will work. I hope it works!.
			 * Probably could shared code.
			 */
			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d not being mapped "
				       "to any IRQ!!\n", __func__, vector,
				       smp_processor_id());
			} else {
				vectors_in_migration[irq]=0;
				generic_handle_irq(irq);
			}
			set_irq_regs(old_regs);

			/*
			 * Disable interrupts and send EOI
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	irq_exit();
}
#endif


#ifdef CONFIG_SMP

static irqreturn_t dummy_handler (int irq, void *dev_id)
{
	BUG();
	return IRQ_NONE;
}

static struct irqaction ipi_irqaction = {
	.handler =	handle_IPI,
	.name =		"IPI"
};

/*
 * KVM uses this interrupt to force a cpu out of guest mode
 */
static struct irqaction resched_irqaction = {
	.handler =	dummy_handler,
	.name =		"resched"
};

static struct irqaction tlb_irqaction = {
	.handler =	dummy_handler,
	.name =		"tlb_flush"
};

#endif

void
ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
	unsigned int irq;

	irq = vec;
	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
	irq_set_status_flags(irq, IRQ_PER_CPU);
	irq_set_chip(irq, &irq_type_ia64_lsapic);
	if (action)
		setup_irq(irq, action);
	irq_set_handler(irq, handle_percpu_irq);
}

void __init
ia64_native_register_ipi(void)
{
#ifdef CONFIG_SMP
	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
#endif
}

void __init
init_IRQ (void)
{
	acpi_boot_init();
	ia64_register_ipi();
	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
#ifdef CONFIG_SMP
	if (vector_domain_type != VECTOR_DOMAIN_NONE)
		register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
#endif
#ifdef CONFIG_PERFMON
	pfm_init_percpu();
#endif
}

void
ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
{
	void __iomem *ipi_addr;
	unsigned long ipi_data;
	unsigned long phys_cpu_id;

	phys_cpu_id = cpu_physical_id(cpu);

	/*
	 * cpu number is in 8bit ID and 8bit EID
	 */

	ipi_data = (delivery_mode << 8) | (vector & 0xff);
	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));

	writeq(ipi_data, ipi_addr);
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4	2	/*
f30c2269	3	* linux/arch/ia64/kernel/irq_ia64.c
1da177e4 LT	4	*
	5	* Copyright (C) 1998-2001 Hewlett-Packard Co
	6	* Stephane Eranian <eranian@hpl.hp.com>
	7	* David Mosberger-Tang <davidm@hpl.hp.com>
	8	*
	9	* 6/10/99: Updated to bring in sync with x86 version to facilitate
	10	* support for SMP and different interrupt controllers.
	11	*
	12	* 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
	13	* PCI to vector allocation routine.
	14	* 04/14/2004 Ashok Raj <ashok.raj@intel.com>
	15	* Added CPU Hotplug handling for IPF.
	16	*/
	17
1da177e4 LT	18	#include <linux/module.h>
	19
	20	#include <linux/jiffies.h>
	21	#include <linux/errno.h>
	22	#include <linux/init.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/kernel_stat.h>
1da177e4	26	#include <linux/ptrace.h>
1da177e4 LT	27	#include <linux/signal.h>
1da177e4 LT	28	#include <linux/smp.h>
1da177e4 LT	29	#include <linux/threads.h>
1da177e4 LT	30	#include <linux/bitops.h>
b6cf2583	31	#include <linux/irq.h>
7683a3f9	32	#include <linux/ratelimit.h>
4de0a759	33	#include <linux/acpi.h>
184748cc	34	#include <linux/sched.h>
1da177e4 LT	35
	36	#include <asm/delay.h>
	37	#include <asm/intrinsics.h>
	38	#include <asm/io.h>
	39	#include <asm/hw_irq.h>
1da177e4	40	#include <asm/pgtable.h>
3be44b9c	41	#include <asm/tlbflush.h>
1da177e4 LT	42
	43	#ifdef CONFIG_PERFMON
	44	# include <asm/perfmon.h>
	45	#endif
	46
	47	#define IRQ_DEBUG 0
	48
e1b30a39 YI	49	#define IRQ_VECTOR_UNASSIGNED (0)
	50
	51	#define IRQ_UNUSED (0)
	52	#define IRQ_USED (1)
	53	#define IRQ_RSVD (2)
	54
10083072 MM	55	int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
	56	int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
	57
1da177e4 LT	58	/* default base addr of IPI table */
	59	void __iomem ipi_base_addr = ((void __iomem )
	60	(__IA64_UNCACHED_OFFSET \| IA64_IPI_DEFAULT_BASE_ADDR));
	61
4994be1b YI	62	static cpumask_t vector_allocation_domain(int cpu);
4994be1b YI	63
1da177e4 LT	64	/*
	65	* Legacy IRQ to IA-64 vector translation table.
	66	*/
	67	__u8 isa_irq_to_vector_map[16] = {
	68	/* 8259 IRQ translation, first 16 entries */
	69	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	70	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
	71	};
	72	EXPORT_SYMBOL(isa_irq_to_vector_map);
	73
e1b30a39 YI	74	DEFINE_SPINLOCK(vector_lock);
	75
	76	struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
4994be1b YI	77	[0 ... NR_IRQS - 1] = {
	78	.vector = IRQ_VECTOR_UNASSIGNED,
	79	.domain = CPU_MASK_NONE
	80	}
e1b30a39 YI	81	};
	82
	83	DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
17764d24	84	[0 ... IA64_NUM_VECTORS - 1] = -1
e1b30a39 YI	85	};
e1b30a39 YI	86
6ffbc823 KK	87	static cpumask_t vector_table[IA64_NUM_VECTORS] = {
6ffbc823 KK	88	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
4994be1b YI	89	};
4994be1b YI	90
e1b30a39 YI	91	static int irq_status[NR_IRQS] = {
	92	[0 ... NR_IRQS -1] = IRQ_UNUSED
	93	};
	94
e1b30a39 YI	95	static inline int find_unassigned_irq(void)
	96	{
	97	int irq;
	98
	99	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
	100	if (irq_status[irq] == IRQ_UNUSED)
	101	return irq;
	102	return -ENOSPC;
	103	}
	104
4994be1b	105	static inline int find_unassigned_vector(cpumask_t domain)
e1b30a39	106	{
4994be1b	107	cpumask_t mask;
6ffbc823	108	int pos, vector;
4994be1b	109
7d7f9848	110	cpumask_and(&mask, &domain, cpu_online_mask);
5d2068da	111	if (cpumask_empty(&mask))
4994be1b	112	return -EINVAL;
e1b30a39	113
4994be1b	114	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
6ffbc823	115	vector = IA64_FIRST_DEVICE_VECTOR + pos;
5d2068da RR	116	cpumask_and(&mask, &domain, &vector_table[vector]);
5d2068da RR	117	if (!cpumask_empty(&mask))
4994be1b	118	continue;
6ffbc823	119	return vector;
4994be1b	120	}
e1b30a39 YI	121	return -ENOSPC;
	122	}
	123
4994be1b	124	static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39	125	{
4994be1b	126	cpumask_t mask;
6ffbc823	127	int cpu;
4994be1b	128	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	129
6bde71ec KK	130	BUG_ON((unsigned)irq >= NR_IRQS);
	131	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);
	132
7d7f9848	133	cpumask_and(&mask, &domain, cpu_online_mask);
5d2068da	134	if (cpumask_empty(&mask))
4994be1b	135	return -EINVAL;
5d2068da	136	if ((cfg->vector == vector) && cpumask_equal(&cfg->domain, &domain))
e1b30a39	137	return 0;
4994be1b	138	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
e1b30a39	139	return -EBUSY;
5d2068da	140	for_each_cpu(cpu, &mask)
e1b30a39	141	per_cpu(vector_irq, cpu)[vector] = irq;
4994be1b YI	142	cfg->vector = vector;
4994be1b YI	143	cfg->domain = domain;
e1b30a39	144	irq_status[irq] = IRQ_USED;
5d2068da	145	cpumask_or(&vector_table[vector], &vector_table[vector], &domain);
e1b30a39 YI	146	return 0;
	147	}
	148
4994be1b	149	int bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39 YI	150	{
	151	unsigned long flags;
	152	int ret;
	153
	154	spin_lock_irqsave(&vector_lock, flags);
4994be1b	155	ret = __bind_irq_vector(irq, vector, domain);
e1b30a39 YI	156	spin_unlock_irqrestore(&vector_lock, flags);
	157	return ret;
	158	}
	159
cd378f18	160	static void __clear_irq_vector(int irq)
e1b30a39	161	{
6ffbc823	162	int vector, cpu;
4994be1b YI	163	cpumask_t domain;
4994be1b YI	164	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	165
e1b30a39	166	BUG_ON((unsigned)irq >= NR_IRQS);
4994be1b YI	167	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	168	vector = cfg->vector;
	169	domain = cfg->domain;
51f7bd85	170	for_each_cpu_and(cpu, &cfg->domain, cpu_online_mask)
17764d24	171	per_cpu(vector_irq, cpu)[vector] = -1;
4994be1b YI	172	cfg->vector = IRQ_VECTOR_UNASSIGNED;
4994be1b YI	173	cfg->domain = CPU_MASK_NONE;
e1b30a39	174	irq_status[irq] = IRQ_UNUSED;
6a4bd8d1	175	cpumask_andnot(&vector_table[vector], &vector_table[vector], &domain);
cd378f18 YI	176	}
	177
	178	static void clear_irq_vector(int irq)
	179	{
	180	unsigned long flags;
	181
	182	spin_lock_irqsave(&vector_lock, flags);
	183	__clear_irq_vector(irq);
e1b30a39 YI	184	spin_unlock_irqrestore(&vector_lock, flags);
e1b30a39 YI	185	}
1da177e4 LT	186
1da177e4 LT	187	int
85cbc503	188	ia64_native_assign_irq_vector (int irq)
1da177e4	189	{
e1b30a39	190	unsigned long flags;
4994be1b	191	int vector, cpu;
373167e8	192	cpumask_t domain = CPU_MASK_NONE;
4994be1b YI	193
4994be1b YI	194	vector = -ENOSPC;
e1b30a39	195
4994be1b	196	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	197	for_each_online_cpu(cpu) {
	198	domain = vector_allocation_domain(cpu);
	199	vector = find_unassigned_vector(domain);
	200	if (vector >= 0)
	201	break;
	202	}
e1b30a39 YI	203	if (vector < 0)
e1b30a39 YI	204	goto out;
8f5ad1a8 YI	205	if (irq == AUTO_ASSIGN)
8f5ad1a8 YI	206	irq = vector;
4994be1b	207	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39	208	out:
4994be1b	209	spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 LT	210	return vector;
	211	}
	212
	213	void
85cbc503	214	ia64_native_free_irq_vector (int vector)
1da177e4	215	{
e1b30a39 YI	216	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
e1b30a39 YI	217	vector > IA64_LAST_DEVICE_VECTOR)
1da177e4	218	return;
e1b30a39	219	clear_irq_vector(vector);
1da177e4 LT	220	}
1da177e4 LT	221
10083072 MM	222	int
	223	reserve_irq_vector (int vector)
	224	{
10083072 MM	225	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
	226	vector > IA64_LAST_DEVICE_VECTOR)
	227	return -EINVAL;
4994be1b	228	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
e1b30a39	229	}
10083072	230
e1b30a39 YI	231	/*
	232	* Initialize vector_irq on a new cpu. This function must be called
	233	* with vector_lock held.
	234	*/
	235	void __setup_vector_irq(int cpu)
	236	{
	237	int irq, vector;
	238
	239	/* Clear vector_irq */
	240	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
17764d24	241	per_cpu(vector_irq, cpu)[vector] = -1;
e1b30a39 YI	242	/* Mark the inuse vectors */
e1b30a39 YI	243	for (irq = 0; irq < NR_IRQS; ++irq) {
5d2068da	244	if (!cpumask_test_cpu(cpu, &irq_cfg[irq].domain))
4994be1b YI	245	continue;
	246	vector = irq_to_vector(irq);
	247	per_cpu(vector_irq, cpu)[vector] = irq;
e1b30a39 YI	248	}
	249	}
	250
df41017e	251	#ifdef CONFIG_SMP
a6cd6322	252
d080d397 YI	253	static enum vector_domain_type {
	254	VECTOR_DOMAIN_NONE,
	255	VECTOR_DOMAIN_PERCPU
	256	} vector_domain_type = VECTOR_DOMAIN_NONE;
	257
4994be1b YI	258	static cpumask_t vector_allocation_domain(int cpu)
4994be1b YI	259	{
d080d397	260	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
6a4bd8d1	261	return *cpumask_of(cpu);
4994be1b YI	262	return CPU_MASK_ALL;
	263	}
	264
a6cd6322 KK	265	static int __irq_prepare_move(int irq, int cpu)
	266	{
	267	struct irq_cfg *cfg = &irq_cfg[irq];
	268	int vector;
	269	cpumask_t domain;
	270
	271	if (cfg->move_in_progress \|\| cfg->move_cleanup_count)
	272	return -EBUSY;
	273	if (cfg->vector == IRQ_VECTOR_UNASSIGNED \|\| !cpu_online(cpu))
	274	return -EINVAL;
5d2068da	275	if (cpumask_test_cpu(cpu, &cfg->domain))
a6cd6322 KK	276	return 0;
	277	domain = vector_allocation_domain(cpu);
	278	vector = find_unassigned_vector(domain);
	279	if (vector < 0)
	280	return -ENOSPC;
	281	cfg->move_in_progress = 1;
	282	cfg->old_domain = cfg->domain;
	283	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	284	cfg->domain = CPU_MASK_NONE;
	285	BUG_ON(__bind_irq_vector(irq, vector, domain));
	286	return 0;
	287	}
	288
	289	int irq_prepare_move(int irq, int cpu)
	290	{
	291	unsigned long flags;
	292	int ret;
	293
	294	spin_lock_irqsave(&vector_lock, flags);
	295	ret = __irq_prepare_move(irq, cpu);
	296	spin_unlock_irqrestore(&vector_lock, flags);
	297	return ret;
	298	}
	299
	300	void irq_complete_move(unsigned irq)
	301	{
	302	struct irq_cfg *cfg = &irq_cfg[irq];
	303	cpumask_t cleanup_mask;
	304	int i;
	305
	306	if (likely(!cfg->move_in_progress))
	307	return;
	308
5d2068da	309	if (unlikely(cpumask_test_cpu(smp_processor_id(), &cfg->old_domain)))
a6cd6322 KK	310	return;
a6cd6322 KK	311
7d7f9848	312	cpumask_and(&cleanup_mask, &cfg->old_domain, cpu_online_mask);
5d2068da RR	313	cfg->move_cleanup_count = cpumask_weight(&cleanup_mask);
5d2068da RR	314	for_each_cpu(i, &cleanup_mask)
05933aac	315	ia64_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
a6cd6322 KK	316	cfg->move_in_progress = 0;
	317	}
	318
	319	static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
	320	{
	321	int me = smp_processor_id();
	322	ia64_vector vector;
	323	unsigned long flags;
	324
	325	for (vector = IA64_FIRST_DEVICE_VECTOR;
	326	vector < IA64_LAST_DEVICE_VECTOR; vector++) {
	327	int irq;
	328	struct irq_desc *desc;
	329	struct irq_cfg *cfg;
6065a244	330	irq = __this_cpu_read(vector_irq[vector]);
a6cd6322 KK	331	if (irq < 0)
	332	continue;
	333
a2178334	334	desc = irq_to_desc(irq);
a6cd6322	335	cfg = irq_cfg + irq;
239007b8	336	raw_spin_lock(&desc->lock);
a6cd6322 KK	337	if (!cfg->move_cleanup_count)
	338	goto unlock;
	339
5d2068da	340	if (!cpumask_test_cpu(me, &cfg->old_domain))
a6cd6322 KK	341	goto unlock;
	342
	343	spin_lock_irqsave(&vector_lock, flags);
6065a244	344	__this_cpu_write(vector_irq[vector], -1);
5d2068da	345	cpumask_clear_cpu(me, &vector_table[vector]);
a6cd6322 KK	346	spin_unlock_irqrestore(&vector_lock, flags);
	347	cfg->move_cleanup_count--;
	348	unlock:
239007b8	349	raw_spin_unlock(&desc->lock);
a6cd6322 KK	350	}
	351	return IRQ_HANDLED;
	352	}
	353
	354	static struct irqaction irq_move_irqaction = {
	355	.handler = smp_irq_move_cleanup_interrupt,
a6cd6322 KK	356	.name = "irq_move"
	357	};
	358
d080d397 YI	359	static int __init parse_vector_domain(char *arg)
	360	{
	361	if (!arg)
	362	return -EINVAL;
	363	if (!strcmp(arg, "percpu")) {
	364	vector_domain_type = VECTOR_DOMAIN_PERCPU;
	365	no_int_routing = 1;
	366	}
074ff856	367	return 0;
d080d397 YI	368	}
	369	early_param("vector", parse_vector_domain);
	370	#else
	371	static cpumask_t vector_allocation_domain(int cpu)
	372	{
	373	return CPU_MASK_ALL;
	374	}
	375	#endif
	376
4994be1b	377
e1b30a39 YI	378	void destroy_and_reserve_irq(unsigned int irq)
e1b30a39 YI	379	{
216fcd29 KK	380	unsigned long flags;
216fcd29 KK	381
4debd723	382	irq_init_desc(irq);
216fcd29 KK	383	spin_lock_irqsave(&vector_lock, flags);
	384	__clear_irq_vector(irq);
	385	irq_status[irq] = IRQ_RSVD;
	386	spin_unlock_irqrestore(&vector_lock, flags);
10083072 MM	387	}
10083072 MM	388
b6cf2583 EB	389	/*
	390	* Dynamic irq allocate and deallocation for MSI
	391	*/
	392	int create_irq(void)
	393	{
e1b30a39	394	unsigned long flags;
4994be1b	395	int irq, vector, cpu;
373167e8	396	cpumask_t domain = CPU_MASK_NONE;
e1b30a39	397
4994be1b	398	irq = vector = -ENOSPC;
e1b30a39	399	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	400	for_each_online_cpu(cpu) {
	401	domain = vector_allocation_domain(cpu);
	402	vector = find_unassigned_vector(domain);
	403	if (vector >= 0)
	404	break;
	405	}
e1b30a39 YI	406	if (vector < 0)
	407	goto out;
	408	irq = find_unassigned_irq();
	409	if (irq < 0)
	410	goto out;
4994be1b	411	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39 YI	412	out:
	413	spin_unlock_irqrestore(&vector_lock, flags);
	414	if (irq >= 0)
4debd723	415	irq_init_desc(irq);
e1b30a39	416	return irq;
b6cf2583 EB	417	}
	418
	419	void destroy_irq(unsigned int irq)
	420	{
4debd723	421	irq_init_desc(irq);
e1b30a39	422	clear_irq_vector(irq);
b6cf2583 EB	423	}
b6cf2583 EB	424
1da177e4 LT	425	#ifdef CONFIG_SMP
1da177e4 LT	426	# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
3be44b9c	427	# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
1da177e4 LT	428	#else
1da177e4 LT	429	# define IS_RESCHEDULE(vec) (0)
3be44b9c	430	# define IS_LOCAL_TLB_FLUSH(vec) (0)
1da177e4 LT	431	#endif
	432	/*
	433	* That's where the IVT branches when we get an external
	434	* interrupt. This branches to the correct hardware IRQ handler via
	435	* function ptr.
	436	*/
	437	void
	438	ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
	439	{
7d12e780	440	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	441	unsigned long saved_tpr;
	442
	443	#if IRQ_DEBUG
	444	{
	445	unsigned long bsp, sp;
	446
	447	/*
	448	* Note: if the interrupt happened while executing in
	449	* the context switch routine (ia64_switch_to), we may
	450	* get a spurious stack overflow here. This is
	451	* because the register and the memory stack are not
	452	* switched atomically.
	453	*/
	454	bsp = ia64_getreg(_IA64_REG_AR_BSP);
	455	sp = ia64_getreg(_IA64_REG_SP);
	456
	457	if ((sp - bsp) < 1024) {
7683a3f9	458	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
1da177e4	459
7683a3f9	460	if (__ratelimit(&ratelimit)) {
1da177e4 LT	461	printk("ia64_handle_irq: DANGER: less than "
	462	"1KB of free stack space!!\n"
	463	"(bsp=0x%lx, sp=%lx)\n", bsp, sp);
	464	}
	465	}
	466	}
	467	#endif /* IRQ_DEBUG */
	468
	469	/*
	470	* Always set TPR to limit maximum interrupt nesting depth to
	471	* 16 (without this, it would be ~240, which could easily lead
	472	* to kernel stack overflows).
	473	*/
	474	irq_enter();
	475	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	476	ia64_srlz_d();
	477	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af JS	478	int irq = local_vector_to_irq(vector);
66f3e6af JS	479
3be44b9c JS	480	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	481	smp_local_flush_tlb();
3611587a	482	kstat_incr_irq_this_cpu(irq);
7c730ccd	483	} else if (unlikely(IS_RESCHEDULE(vector))) {
184748cc	484	scheduler_ipi();
3611587a	485	kstat_incr_irq_this_cpu(irq);
7c730ccd	486	} else {
1da177e4 LT	487	ia64_setreg(_IA64_REG_CR_TPR, vector);
	488	ia64_srlz_d();
	489
17764d24 KK	490	if (unlikely(irq < 0)) {
	491	printk(KERN_ERR "%s: Unexpected interrupt "
	492	"vector %d on CPU %d is not mapped "
d4ed8084	493	"to any IRQ!\n", __func__, vector,
17764d24 KK	494	smp_processor_id());
	495	} else
	496	generic_handle_irq(irq);
1da177e4 LT	497
	498	/*
	499	* Disable interrupts and send EOI:
	500	*/
	501	local_irq_disable();
	502	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	503	}
	504	ia64_eoi();
	505	vector = ia64_get_ivr();
	506	}
	507	/*
	508	* This must be done after the ia64_eoi(). For example, the keyboard softirq
	509	* handler needs to be able to wait for further keyboard interrupts, which can't
	510	* come through until ia64_eoi() has been done.
	511	*/
	512	irq_exit();
7d12e780	513	set_irq_regs(old_regs);
1da177e4 LT	514	}
	515
	516	#ifdef CONFIG_HOTPLUG_CPU
	517	/*
	518	* This function emulates a interrupt processing when a cpu is about to be
	519	* brought down.
	520	*/
	521	void ia64_process_pending_intr(void)
	522	{
	523	ia64_vector vector;
	524	unsigned long saved_tpr;
	525	extern unsigned int vectors_in_migration[NR_IRQS];
	526
	527	vector = ia64_get_ivr();
	528
66f3e6af JS	529	irq_enter();
	530	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	531	ia64_srlz_d();
1da177e4 LT	532
	533	/*
	534	* Perform normal interrupt style processing
	535	*/
	536	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af	537	int irq = local_vector_to_irq(vector);
66f3e6af	538
3be44b9c JS	539	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	540	smp_local_flush_tlb();
3611587a	541	kstat_incr_irq_this_cpu(irq);
7c730ccd	542	} else if (unlikely(IS_RESCHEDULE(vector))) {
3611587a	543	kstat_incr_irq_this_cpu(irq);
7c730ccd	544	} else {
8c1addbc TL	545	struct pt_regs *old_regs = set_irq_regs(NULL);
8c1addbc TL	546
1da177e4 LT	547	ia64_setreg(_IA64_REG_CR_TPR, vector);
	548	ia64_srlz_d();
	549
	550	/*
	551	* Now try calling normal ia64_handle_irq as it would have got called
	552	* from a real intr handler. Try passing null for pt_regs, hopefully
	553	* it will work. I hope it works!.
	554	* Probably could shared code.
	555	*/
17764d24 KK	556	if (unlikely(irq < 0)) {
	557	printk(KERN_ERR "%s: Unexpected interrupt "
	558	"vector %d on CPU %d not being mapped "
d4ed8084	559	"to any IRQ!!\n", __func__, vector,
17764d24 KK	560	smp_processor_id());
	561	} else {
	562	vectors_in_migration[irq]=0;
	563	generic_handle_irq(irq);
	564	}
8c1addbc	565	set_irq_regs(old_regs);
1da177e4 LT	566
	567	/*
	568	* Disable interrupts and send EOI
	569	*/
	570	local_irq_disable();
	571	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	572	}
	573	ia64_eoi();
	574	vector = ia64_get_ivr();
	575	}
	576	irq_exit();
	577	}
	578	#endif
	579
	580
	581	#ifdef CONFIG_SMP
1da177e4	582
9b3377f9 JS	583	static irqreturn_t dummy_handler (int irq, void *dev_id)
	584	{
	585	BUG();
722e6f50	586	return IRQ_NONE;
9b3377f9 JS	587	}
9b3377f9 JS	588
1da177e4 LT	589	static struct irqaction ipi_irqaction = {
1da177e4 LT	590	.handler = handle_IPI,
1da177e4 LT	591	.name = "IPI"
1da177e4 LT	592	};
9b3377f9	593
32f88400 MT	594	/*
	595	* KVM uses this interrupt to force a cpu out of guest mode
	596	*/
9b3377f9 JS	597	static struct irqaction resched_irqaction = {
9b3377f9 JS	598	.handler = dummy_handler,
9b3377f9 JS	599	.name = "resched"
9b3377f9 JS	600	};
3be44b9c JS	601
	602	static struct irqaction tlb_irqaction = {
	603	.handler = dummy_handler,
3be44b9c JS	604	.name = "tlb_flush"
	605	};
	606
1da177e4 LT	607	#endif
	608
	609	void
85cbc503	610	ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
1da177e4	611	{
1da177e4 LT	612	unsigned int irq;
1da177e4 LT	613
e1b30a39	614	irq = vec;
4994be1b	615	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
a2178334	616	irq_set_status_flags(irq, IRQ_PER_CPU);
53c909c9	617	irq_set_chip(irq, &irq_type_ia64_lsapic);
e1b30a39 YI	618	if (action)
e1b30a39 YI	619	setup_irq(irq, action);
53c909c9	620	irq_set_handler(irq, handle_percpu_irq);
1da177e4 LT	621	}
	622
	623	void __init
85cbc503	624	ia64_native_register_ipi(void)
1da177e4	625	{
1da177e4 LT	626	#ifdef CONFIG_SMP
1da177e4 LT	627	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
9b3377f9	628	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
3be44b9c	629	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
85cbc503 IY	630	#endif
	631	}
	632
	633	void __init
	634	init_IRQ (void)
	635	{
4de0a759	636	acpi_boot_init();
85cbc503 IY	637	ia64_register_ipi();
	638	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
	639	#ifdef CONFIG_SMP
09b366b7	640	if (vector_domain_type != VECTOR_DOMAIN_NONE)
a6cd6322	641	register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
a6cd6322	642	#endif
1da177e4 LT	643	#ifdef CONFIG_PERFMON
	644	pfm_init_percpu();
	645	#endif
1da177e4 LT	646	}
	647
	648	void
	649	ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
	650	{
	651	void __iomem *ipi_addr;
	652	unsigned long ipi_data;
	653	unsigned long phys_cpu_id;
	654
1da177e4	655	phys_cpu_id = cpu_physical_id(cpu);
1da177e4 LT	656
	657	/*
	658	* cpu number is in 8bit ID and 8bit EID
	659	*/
	660
	661	ipi_data = (delivery_mode << 8) \| (vector & 0xff);
	662	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) \| ((redirect & 1) << 3));
	663
	664	writeq(ipi_data, ipi_addr);
	665	}