[linux-2.6-block.git] / arch / ia64 / kernel / irq_ia64.c

/*
 * linux/arch/ia64/kernel/irq_ia64.c
 *
 * Copyright (C) 1998-2001 Hewlett-Packard Co
 *	Stephane Eranian <eranian@hpl.hp.com>
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 *  6/10/99: Updated to bring in sync with x86 version to facilitate
 *	     support for SMP and different interrupt controllers.
 *
 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
 *                      PCI to vector allocation routine.
 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
 *						Added CPU Hotplug handling for IPF.
 */

#include <linux/module.h>

#include <linux/jiffies.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>
#include <linux/ptrace.h>
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/ratelimit.h>
#include <linux/acpi.h>
#include <linux/sched.h>

#include <asm/delay.h>
#include <asm/intrinsics.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>

#ifdef CONFIG_PERFMON
# include <asm/perfmon.h>
#endif

#define IRQ_DEBUG	0

#define IRQ_VECTOR_UNASSIGNED	(0)

#define IRQ_UNUSED		(0)
#define IRQ_USED		(1)
#define IRQ_RSVD		(2)

/* These can be overridden in platform_irq_init */
int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;

/* default base addr of IPI table */
void __iomem *ipi_base_addr = ((void __iomem *)
			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));

static cpumask_t vector_allocation_domain(int cpu);

/*
 * Legacy IRQ to IA-64 vector translation table.
 */
__u8 isa_irq_to_vector_map[16] = {
	/* 8259 IRQ translation, first 16 entries */
	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
};
EXPORT_SYMBOL(isa_irq_to_vector_map);

DEFINE_SPINLOCK(vector_lock);

struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
	[0 ... NR_IRQS - 1] = {
		.vector = IRQ_VECTOR_UNASSIGNED,
		.domain = CPU_MASK_NONE
	}
};

DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	[0 ... IA64_NUM_VECTORS - 1] = -1
};

static cpumask_t vector_table[IA64_NUM_VECTORS] = {
	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
};

static int irq_status[NR_IRQS] = {
	[0 ... NR_IRQS -1] = IRQ_UNUSED
};

static inline int find_unassigned_irq(void)
{
	int irq;

	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
		if (irq_status[irq] == IRQ_UNUSED)
			return irq;
	return -ENOSPC;
}

static inline int find_unassigned_vector(cpumask_t domain)
{
	cpumask_t mask;
	int pos, vector;

	cpumask_and(&mask, &domain, cpu_online_mask);
	if (cpus_empty(mask))
		return -EINVAL;

	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
		vector = IA64_FIRST_DEVICE_VECTOR + pos;
		cpus_and(mask, domain, vector_table[vector]);
		if (!cpus_empty(mask))
			continue;
		return vector;
	}
	return -ENOSPC;
}

static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	cpumask_t mask;
	int cpu;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);

	cpumask_and(&mask, &domain, cpu_online_mask);
	if (cpus_empty(mask))
		return -EINVAL;
	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
		return 0;
	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
		return -EBUSY;
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = irq;
	cfg->vector = vector;
	cfg->domain = domain;
	irq_status[irq] = IRQ_USED;
	cpus_or(vector_table[vector], vector_table[vector], domain);
	return 0;
}

int bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __bind_irq_vector(irq, vector, domain);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

static void __clear_irq_vector(int irq)
{
	int vector, cpu;
	cpumask_t mask;
	cpumask_t domain;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	vector = cfg->vector;
	domain = cfg->domain;
	cpumask_and(&mask, &cfg->domain, cpu_online_mask);
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = -1;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	irq_status[irq] = IRQ_UNUSED;
	cpus_andnot(vector_table[vector], vector_table[vector], domain);
}

static void clear_irq_vector(int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	spin_unlock_irqrestore(&vector_lock, flags);
}

int
ia64_native_assign_irq_vector (int irq)
{
	unsigned long flags;
	int vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	vector = -ENOSPC;

	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	if (irq == AUTO_ASSIGN)
		irq = vector;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	return vector;
}

void
ia64_native_free_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return;
	clear_irq_vector(vector);
}

int
reserve_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return -EINVAL;
	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
}

/*
 * Initialize vector_irq on a new cpu. This function must be called
 * with vector_lock held.
 */
void __setup_vector_irq(int cpu)
{
	int irq, vector;

	/* Clear vector_irq */
	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
		per_cpu(vector_irq, cpu)[vector] = -1;
	/* Mark the inuse vectors */
	for (irq = 0; irq < NR_IRQS; ++irq) {
		if (!cpu_isset(cpu, irq_cfg[irq].domain))
			continue;
		vector = irq_to_vector(irq);
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
}

#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))

static enum vector_domain_type {
	VECTOR_DOMAIN_NONE,
	VECTOR_DOMAIN_PERCPU
} vector_domain_type = VECTOR_DOMAIN_NONE;

static cpumask_t vector_allocation_domain(int cpu)
{
	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
		return cpumask_of_cpu(cpu);
	return CPU_MASK_ALL;
}

static int __irq_prepare_move(int irq, int cpu)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	int vector;
	cpumask_t domain;

	if (cfg->move_in_progress || cfg->move_cleanup_count)
		return -EBUSY;
	if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
		return -EINVAL;
	if (cpu_isset(cpu, cfg->domain))
		return 0;
	domain = vector_allocation_domain(cpu);
	vector = find_unassigned_vector(domain);
	if (vector < 0)
		return -ENOSPC;
	cfg->move_in_progress = 1;
	cfg->old_domain = cfg->domain;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
	return 0;
}

int irq_prepare_move(int irq, int cpu)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __irq_prepare_move(irq, cpu);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

void irq_complete_move(unsigned irq)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	cpumask_t cleanup_mask;
	int i;

	if (likely(!cfg->move_in_progress))
		return;

	if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
		return;

	cpumask_and(&cleanup_mask, &cfg->old_domain, cpu_online_mask);
	cfg->move_cleanup_count = cpus_weight(cleanup_mask);
	for_each_cpu_mask(i, cleanup_mask)
		platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	cfg->move_in_progress = 0;
}

static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
{
	int me = smp_processor_id();
	ia64_vector vector;
	unsigned long flags;

	for (vector = IA64_FIRST_DEVICE_VECTOR;
	     vector < IA64_LAST_DEVICE_VECTOR; vector++) {
		int irq;
		struct irq_desc *desc;
		struct irq_cfg *cfg;
		irq = __get_cpu_var(vector_irq)[vector];
		if (irq < 0)
			continue;

		desc = irq_to_desc(irq);
		cfg = irq_cfg + irq;
		raw_spin_lock(&desc->lock);
		if (!cfg->move_cleanup_count)
			goto unlock;

		if (!cpu_isset(me, cfg->old_domain))
			goto unlock;

		spin_lock_irqsave(&vector_lock, flags);
		__get_cpu_var(vector_irq)[vector] = -1;
		cpu_clear(me, vector_table[vector]);
		spin_unlock_irqrestore(&vector_lock, flags);
		cfg->move_cleanup_count--;
	unlock:
		raw_spin_unlock(&desc->lock);
	}
	return IRQ_HANDLED;
}

static struct irqaction irq_move_irqaction = {
	.handler =	smp_irq_move_cleanup_interrupt,
	.name =		"irq_move"
};

static int __init parse_vector_domain(char *arg)
{
	if (!arg)
		return -EINVAL;
	if (!strcmp(arg, "percpu")) {
		vector_domain_type = VECTOR_DOMAIN_PERCPU;
		no_int_routing = 1;
	}
	return 0;
}
early_param("vector", parse_vector_domain);
#else
static cpumask_t vector_allocation_domain(int cpu)
{
	return CPU_MASK_ALL;
}
#endif


void destroy_and_reserve_irq(unsigned int irq)
{
	unsigned long flags;

	irq_init_desc(irq);
	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	irq_status[irq] = IRQ_RSVD;
	spin_unlock_irqrestore(&vector_lock, flags);
}

/*
 * Dynamic irq allocate and deallocation for MSI
 */
int create_irq(void)
{
	unsigned long flags;
	int irq, vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	irq = vector = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	irq = find_unassigned_irq();
	if (irq < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	if (irq >= 0)
		irq_init_desc(irq);
	return irq;
}

void destroy_irq(unsigned int irq)
{
	irq_init_desc(irq);
	clear_irq_vector(irq);
}

#ifdef CONFIG_SMP
#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
#	define IS_LOCAL_TLB_FLUSH(vec)	(vec == IA64_IPI_LOCAL_TLB_FLUSH)
#else
#	define IS_RESCHEDULE(vec)	(0)
#	define IS_LOCAL_TLB_FLUSH(vec)	(0)
#endif
/*
 * That's where the IVT branches when we get an external
 * interrupt. This branches to the correct hardware IRQ handler via
 * function ptr.
 */
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	unsigned long saved_tpr;

#if IRQ_DEBUG
	{
		unsigned long bsp, sp;

		/*
		 * Note: if the interrupt happened while executing in
		 * the context switch routine (ia64_switch_to), we may
		 * get a spurious stack overflow here.  This is
		 * because the register and the memory stack are not
		 * switched atomically.
		 */
		bsp = ia64_getreg(_IA64_REG_AR_BSP);
		sp = ia64_getreg(_IA64_REG_SP);

		if ((sp - bsp) < 1024) {
			static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);

			if (__ratelimit(&ratelimit)) {
				printk("ia64_handle_irq: DANGER: less than "
				       "1KB of free stack space!!\n"
				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
			}
		}
	}
#endif /* IRQ_DEBUG */

	/*
	 * Always set TPR to limit maximum interrupt nesting depth to
	 * 16 (without this, it would be ~240, which could easily lead
	 * to kernel stack overflows).
	 */
	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irq_this_cpu(irq);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			scheduler_ipi();
			kstat_incr_irq_this_cpu(irq);
		} else {
			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d is not mapped "
				       "to any IRQ!\n", __func__, vector,
				       smp_processor_id());
			} else
				generic_handle_irq(irq);

			/*
			 * Disable interrupts and send EOI:
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	/*
	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
	 * handler needs to be able to wait for further keyboard interrupts, which can't
	 * come through until ia64_eoi() has been done.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}

#ifdef CONFIG_HOTPLUG_CPU
/*
 * This function emulates a interrupt processing when a cpu is about to be
 * brought down.
 */
void ia64_process_pending_intr(void)
{
	ia64_vector vector;
	unsigned long saved_tpr;
	extern unsigned int vectors_in_migration[NR_IRQS];

	vector = ia64_get_ivr();

	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();

	 /*
	  * Perform normal interrupt style processing
	  */
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irq_this_cpu(irq);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			kstat_incr_irq_this_cpu(irq);
		} else {
			struct pt_regs *old_regs = set_irq_regs(NULL);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			/*
			 * Now try calling normal ia64_handle_irq as it would have got called
			 * from a real intr handler. Try passing null for pt_regs, hopefully
			 * it will work. I hope it works!.
			 * Probably could shared code.
			 */
			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d not being mapped "
				       "to any IRQ!!\n", __func__, vector,
				       smp_processor_id());
			} else {
				vectors_in_migration[irq]=0;
				generic_handle_irq(irq);
			}
			set_irq_regs(old_regs);

			/*
			 * Disable interrupts and send EOI
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	irq_exit();
}
#endif


#ifdef CONFIG_SMP

static irqreturn_t dummy_handler (int irq, void *dev_id)
{
	BUG();
}

static struct irqaction ipi_irqaction = {
	.handler =	handle_IPI,
	.name =		"IPI"
};

/*
 * KVM uses this interrupt to force a cpu out of guest mode
 */
static struct irqaction resched_irqaction = {
	.handler =	dummy_handler,
	.name =		"resched"
};

static struct irqaction tlb_irqaction = {
	.handler =	dummy_handler,
	.name =		"tlb_flush"
};

#endif

void
ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
	unsigned int irq;

	irq = vec;
	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
	irq_set_status_flags(irq, IRQ_PER_CPU);
	irq_set_chip(irq, &irq_type_ia64_lsapic);
	if (action)
		setup_irq(irq, action);
	irq_set_handler(irq, handle_percpu_irq);
}

void __init
ia64_native_register_ipi(void)
{
#ifdef CONFIG_SMP
	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
#endif
}

void __init
init_IRQ (void)
{
#ifdef CONFIG_ACPI
	acpi_boot_init();
#endif
	ia64_register_ipi();
	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
#ifdef CONFIG_SMP
#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)
	if (vector_domain_type != VECTOR_DOMAIN_NONE)
		register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
#endif
#endif
#ifdef CONFIG_PERFMON
	pfm_init_percpu();
#endif
	platform_irq_init();
}

void
ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
{
	void __iomem *ipi_addr;
	unsigned long ipi_data;
	unsigned long phys_cpu_id;

	phys_cpu_id = cpu_physical_id(cpu);

	/*
	 * cpu number is in 8bit ID and 8bit EID
	 */

	ipi_data = (delivery_mode << 8) | (vector & 0xff);
	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));

	writeq(ipi_data, ipi_addr);
}
Commit	Line	Data
1da177e4	1	/*
f30c2269	2	* linux/arch/ia64/kernel/irq_ia64.c
1da177e4 LT	3	*
	4	* Copyright (C) 1998-2001 Hewlett-Packard Co
	5	* Stephane Eranian <eranian@hpl.hp.com>
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*
	8	* 6/10/99: Updated to bring in sync with x86 version to facilitate
	9	* support for SMP and different interrupt controllers.
	10	*
	11	* 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
	12	* PCI to vector allocation routine.
	13	* 04/14/2004 Ashok Raj <ashok.raj@intel.com>
	14	* Added CPU Hotplug handling for IPF.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18
	19	#include <linux/jiffies.h>
	20	#include <linux/errno.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel_stat.h>
1da177e4	25	#include <linux/ptrace.h>
1da177e4 LT	26	#include <linux/signal.h>
1da177e4 LT	27	#include <linux/smp.h>
1da177e4 LT	28	#include <linux/threads.h>
1da177e4 LT	29	#include <linux/bitops.h>
b6cf2583	30	#include <linux/irq.h>
7683a3f9	31	#include <linux/ratelimit.h>
4de0a759	32	#include <linux/acpi.h>
184748cc	33	#include <linux/sched.h>
1da177e4 LT	34
	35	#include <asm/delay.h>
	36	#include <asm/intrinsics.h>
	37	#include <asm/io.h>
	38	#include <asm/hw_irq.h>
	39	#include <asm/machvec.h>
	40	#include <asm/pgtable.h>
3be44b9c	41	#include <asm/tlbflush.h>
1da177e4 LT	42
	43	#ifdef CONFIG_PERFMON
	44	# include <asm/perfmon.h>
	45	#endif
	46
	47	#define IRQ_DEBUG 0
	48
e1b30a39 YI	49	#define IRQ_VECTOR_UNASSIGNED (0)
	50
	51	#define IRQ_UNUSED (0)
	52	#define IRQ_USED (1)
	53	#define IRQ_RSVD (2)
	54
10083072 MM	55	/* These can be overridden in platform_irq_init */
	56	int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
	57	int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
	58
1da177e4 LT	59	/* default base addr of IPI table */
	60	void __iomem ipi_base_addr = ((void __iomem )
	61	(__IA64_UNCACHED_OFFSET \| IA64_IPI_DEFAULT_BASE_ADDR));
	62
4994be1b YI	63	static cpumask_t vector_allocation_domain(int cpu);
4994be1b YI	64
1da177e4 LT	65	/*
	66	* Legacy IRQ to IA-64 vector translation table.
	67	*/
	68	__u8 isa_irq_to_vector_map[16] = {
	69	/* 8259 IRQ translation, first 16 entries */
	70	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	71	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
	72	};
	73	EXPORT_SYMBOL(isa_irq_to_vector_map);
	74
e1b30a39 YI	75	DEFINE_SPINLOCK(vector_lock);
	76
	77	struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
4994be1b YI	78	[0 ... NR_IRQS - 1] = {
	79	.vector = IRQ_VECTOR_UNASSIGNED,
	80	.domain = CPU_MASK_NONE
	81	}
e1b30a39 YI	82	};
	83
	84	DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
17764d24	85	[0 ... IA64_NUM_VECTORS - 1] = -1
e1b30a39 YI	86	};
e1b30a39 YI	87
6ffbc823 KK	88	static cpumask_t vector_table[IA64_NUM_VECTORS] = {
6ffbc823 KK	89	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
4994be1b YI	90	};
4994be1b YI	91
e1b30a39 YI	92	static int irq_status[NR_IRQS] = {
	93	[0 ... NR_IRQS -1] = IRQ_UNUSED
	94	};
	95
e1b30a39 YI	96	static inline int find_unassigned_irq(void)
	97	{
	98	int irq;
	99
	100	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
	101	if (irq_status[irq] == IRQ_UNUSED)
	102	return irq;
	103	return -ENOSPC;
	104	}
	105
4994be1b	106	static inline int find_unassigned_vector(cpumask_t domain)
e1b30a39	107	{
4994be1b	108	cpumask_t mask;
6ffbc823	109	int pos, vector;
4994be1b	110
7d7f9848	111	cpumask_and(&mask, &domain, cpu_online_mask);
4994be1b YI	112	if (cpus_empty(mask))
4994be1b YI	113	return -EINVAL;
e1b30a39	114
4994be1b	115	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
6ffbc823 KK	116	vector = IA64_FIRST_DEVICE_VECTOR + pos;
6ffbc823 KK	117	cpus_and(mask, domain, vector_table[vector]);
4994be1b YI	118	if (!cpus_empty(mask))
4994be1b YI	119	continue;
6ffbc823	120	return vector;
4994be1b	121	}
e1b30a39 YI	122	return -ENOSPC;
	123	}
	124
4994be1b	125	static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39	126	{
4994be1b	127	cpumask_t mask;
6ffbc823	128	int cpu;
4994be1b	129	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	130
6bde71ec KK	131	BUG_ON((unsigned)irq >= NR_IRQS);
	132	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);
	133
7d7f9848	134	cpumask_and(&mask, &domain, cpu_online_mask);
4994be1b YI	135	if (cpus_empty(mask))
	136	return -EINVAL;
	137	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
e1b30a39	138	return 0;
4994be1b	139	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
e1b30a39	140	return -EBUSY;
4994be1b	141	for_each_cpu_mask(cpu, mask)
e1b30a39	142	per_cpu(vector_irq, cpu)[vector] = irq;
4994be1b YI	143	cfg->vector = vector;
4994be1b YI	144	cfg->domain = domain;
e1b30a39	145	irq_status[irq] = IRQ_USED;
6ffbc823	146	cpus_or(vector_table[vector], vector_table[vector], domain);
e1b30a39 YI	147	return 0;
	148	}
	149
4994be1b	150	int bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39 YI	151	{
	152	unsigned long flags;
	153	int ret;
	154
	155	spin_lock_irqsave(&vector_lock, flags);
4994be1b	156	ret = __bind_irq_vector(irq, vector, domain);
e1b30a39 YI	157	spin_unlock_irqrestore(&vector_lock, flags);
	158	return ret;
	159	}
	160
cd378f18	161	static void __clear_irq_vector(int irq)
e1b30a39	162	{
6ffbc823	163	int vector, cpu;
4994be1b YI	164	cpumask_t mask;
	165	cpumask_t domain;
	166	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	167
e1b30a39	168	BUG_ON((unsigned)irq >= NR_IRQS);
4994be1b YI	169	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	170	vector = cfg->vector;
	171	domain = cfg->domain;
7d7f9848	172	cpumask_and(&mask, &cfg->domain, cpu_online_mask);
4994be1b	173	for_each_cpu_mask(cpu, mask)
17764d24	174	per_cpu(vector_irq, cpu)[vector] = -1;
4994be1b YI	175	cfg->vector = IRQ_VECTOR_UNASSIGNED;
4994be1b YI	176	cfg->domain = CPU_MASK_NONE;
e1b30a39	177	irq_status[irq] = IRQ_UNUSED;
6ffbc823	178	cpus_andnot(vector_table[vector], vector_table[vector], domain);
cd378f18 YI	179	}
	180
	181	static void clear_irq_vector(int irq)
	182	{
	183	unsigned long flags;
	184
	185	spin_lock_irqsave(&vector_lock, flags);
	186	__clear_irq_vector(irq);
e1b30a39 YI	187	spin_unlock_irqrestore(&vector_lock, flags);
e1b30a39 YI	188	}
1da177e4 LT	189
1da177e4 LT	190	int
85cbc503	191	ia64_native_assign_irq_vector (int irq)
1da177e4	192	{
e1b30a39	193	unsigned long flags;
4994be1b	194	int vector, cpu;
373167e8	195	cpumask_t domain = CPU_MASK_NONE;
4994be1b YI	196
4994be1b YI	197	vector = -ENOSPC;
e1b30a39	198
4994be1b	199	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	200	for_each_online_cpu(cpu) {
	201	domain = vector_allocation_domain(cpu);
	202	vector = find_unassigned_vector(domain);
	203	if (vector >= 0)
	204	break;
	205	}
e1b30a39 YI	206	if (vector < 0)
e1b30a39 YI	207	goto out;
8f5ad1a8 YI	208	if (irq == AUTO_ASSIGN)
8f5ad1a8 YI	209	irq = vector;
4994be1b	210	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39	211	out:
4994be1b	212	spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 LT	213	return vector;
	214	}
	215
	216	void
85cbc503	217	ia64_native_free_irq_vector (int vector)
1da177e4	218	{
e1b30a39 YI	219	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
e1b30a39 YI	220	vector > IA64_LAST_DEVICE_VECTOR)
1da177e4	221	return;
e1b30a39	222	clear_irq_vector(vector);
1da177e4 LT	223	}
1da177e4 LT	224
10083072 MM	225	int
	226	reserve_irq_vector (int vector)
	227	{
10083072 MM	228	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
	229	vector > IA64_LAST_DEVICE_VECTOR)
	230	return -EINVAL;
4994be1b	231	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
e1b30a39	232	}
10083072	233
e1b30a39 YI	234	/*
	235	* Initialize vector_irq on a new cpu. This function must be called
	236	* with vector_lock held.
	237	*/
	238	void __setup_vector_irq(int cpu)
	239	{
	240	int irq, vector;
	241
	242	/* Clear vector_irq */
	243	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
17764d24	244	per_cpu(vector_irq, cpu)[vector] = -1;
e1b30a39 YI	245	/* Mark the inuse vectors */
e1b30a39 YI	246	for (irq = 0; irq < NR_IRQS; ++irq) {
4994be1b YI	247	if (!cpu_isset(cpu, irq_cfg[irq].domain))
	248	continue;
	249	vector = irq_to_vector(irq);
	250	per_cpu(vector_irq, cpu)[vector] = irq;
e1b30a39 YI	251	}
	252	}
	253
e5bd762b	254	#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG))
a6cd6322	255
d080d397 YI	256	static enum vector_domain_type {
	257	VECTOR_DOMAIN_NONE,
	258	VECTOR_DOMAIN_PERCPU
	259	} vector_domain_type = VECTOR_DOMAIN_NONE;
	260
4994be1b YI	261	static cpumask_t vector_allocation_domain(int cpu)
4994be1b YI	262	{
d080d397 YI	263	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
d080d397 YI	264	return cpumask_of_cpu(cpu);
4994be1b YI	265	return CPU_MASK_ALL;
	266	}
	267
a6cd6322 KK	268	static int __irq_prepare_move(int irq, int cpu)
	269	{
	270	struct irq_cfg *cfg = &irq_cfg[irq];
	271	int vector;
	272	cpumask_t domain;
	273
	274	if (cfg->move_in_progress \|\| cfg->move_cleanup_count)
	275	return -EBUSY;
	276	if (cfg->vector == IRQ_VECTOR_UNASSIGNED \|\| !cpu_online(cpu))
	277	return -EINVAL;
	278	if (cpu_isset(cpu, cfg->domain))
	279	return 0;
	280	domain = vector_allocation_domain(cpu);
	281	vector = find_unassigned_vector(domain);
	282	if (vector < 0)
	283	return -ENOSPC;
	284	cfg->move_in_progress = 1;
	285	cfg->old_domain = cfg->domain;
	286	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	287	cfg->domain = CPU_MASK_NONE;
	288	BUG_ON(__bind_irq_vector(irq, vector, domain));
	289	return 0;
	290	}
	291
	292	int irq_prepare_move(int irq, int cpu)
	293	{
	294	unsigned long flags;
	295	int ret;
	296
	297	spin_lock_irqsave(&vector_lock, flags);
	298	ret = __irq_prepare_move(irq, cpu);
	299	spin_unlock_irqrestore(&vector_lock, flags);
	300	return ret;
	301	}
	302
	303	void irq_complete_move(unsigned irq)
	304	{
	305	struct irq_cfg *cfg = &irq_cfg[irq];
	306	cpumask_t cleanup_mask;
	307	int i;
	308
	309	if (likely(!cfg->move_in_progress))
	310	return;
	311
	312	if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
	313	return;
	314
7d7f9848	315	cpumask_and(&cleanup_mask, &cfg->old_domain, cpu_online_mask);
a6cd6322 KK	316	cfg->move_cleanup_count = cpus_weight(cleanup_mask);
	317	for_each_cpu_mask(i, cleanup_mask)
	318	platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	319	cfg->move_in_progress = 0;
	320	}
	321
	322	static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
	323	{
	324	int me = smp_processor_id();
	325	ia64_vector vector;
	326	unsigned long flags;
	327
	328	for (vector = IA64_FIRST_DEVICE_VECTOR;
	329	vector < IA64_LAST_DEVICE_VECTOR; vector++) {
	330	int irq;
	331	struct irq_desc *desc;
	332	struct irq_cfg *cfg;
	333	irq = __get_cpu_var(vector_irq)[vector];
	334	if (irq < 0)
	335	continue;
	336
a2178334	337	desc = irq_to_desc(irq);
a6cd6322	338	cfg = irq_cfg + irq;
239007b8	339	raw_spin_lock(&desc->lock);
a6cd6322 KK	340	if (!cfg->move_cleanup_count)
	341	goto unlock;
	342
	343	if (!cpu_isset(me, cfg->old_domain))
	344	goto unlock;
	345
	346	spin_lock_irqsave(&vector_lock, flags);
	347	__get_cpu_var(vector_irq)[vector] = -1;
	348	cpu_clear(me, vector_table[vector]);
	349	spin_unlock_irqrestore(&vector_lock, flags);
	350	cfg->move_cleanup_count--;
	351	unlock:
239007b8	352	raw_spin_unlock(&desc->lock);
a6cd6322 KK	353	}
	354	return IRQ_HANDLED;
	355	}
	356
	357	static struct irqaction irq_move_irqaction = {
	358	.handler = smp_irq_move_cleanup_interrupt,
a6cd6322 KK	359	.name = "irq_move"
	360	};
	361
d080d397 YI	362	static int __init parse_vector_domain(char *arg)
	363	{
	364	if (!arg)
	365	return -EINVAL;
	366	if (!strcmp(arg, "percpu")) {
	367	vector_domain_type = VECTOR_DOMAIN_PERCPU;
	368	no_int_routing = 1;
	369	}
074ff856	370	return 0;
d080d397 YI	371	}
	372	early_param("vector", parse_vector_domain);
	373	#else
	374	static cpumask_t vector_allocation_domain(int cpu)
	375	{
	376	return CPU_MASK_ALL;
	377	}
	378	#endif
	379
4994be1b	380
e1b30a39 YI	381	void destroy_and_reserve_irq(unsigned int irq)
e1b30a39 YI	382	{
216fcd29 KK	383	unsigned long flags;
216fcd29 KK	384
4debd723	385	irq_init_desc(irq);
216fcd29 KK	386	spin_lock_irqsave(&vector_lock, flags);
	387	__clear_irq_vector(irq);
	388	irq_status[irq] = IRQ_RSVD;
	389	spin_unlock_irqrestore(&vector_lock, flags);
10083072 MM	390	}
10083072 MM	391
b6cf2583 EB	392	/*
	393	* Dynamic irq allocate and deallocation for MSI
	394	*/
	395	int create_irq(void)
	396	{
e1b30a39	397	unsigned long flags;
4994be1b	398	int irq, vector, cpu;
373167e8	399	cpumask_t domain = CPU_MASK_NONE;
e1b30a39	400
4994be1b	401	irq = vector = -ENOSPC;
e1b30a39	402	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	403	for_each_online_cpu(cpu) {
	404	domain = vector_allocation_domain(cpu);
	405	vector = find_unassigned_vector(domain);
	406	if (vector >= 0)
	407	break;
	408	}
e1b30a39 YI	409	if (vector < 0)
	410	goto out;
	411	irq = find_unassigned_irq();
	412	if (irq < 0)
	413	goto out;
4994be1b	414	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39 YI	415	out:
	416	spin_unlock_irqrestore(&vector_lock, flags);
	417	if (irq >= 0)
4debd723	418	irq_init_desc(irq);
e1b30a39	419	return irq;
b6cf2583 EB	420	}
	421
	422	void destroy_irq(unsigned int irq)
	423	{
4debd723	424	irq_init_desc(irq);
e1b30a39	425	clear_irq_vector(irq);
b6cf2583 EB	426	}
b6cf2583 EB	427
1da177e4 LT	428	#ifdef CONFIG_SMP
1da177e4 LT	429	# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
3be44b9c	430	# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
1da177e4 LT	431	#else
1da177e4 LT	432	# define IS_RESCHEDULE(vec) (0)
3be44b9c	433	# define IS_LOCAL_TLB_FLUSH(vec) (0)
1da177e4 LT	434	#endif
	435	/*
	436	* That's where the IVT branches when we get an external
	437	* interrupt. This branches to the correct hardware IRQ handler via
	438	* function ptr.
	439	*/
	440	void
	441	ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
	442	{
7d12e780	443	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	444	unsigned long saved_tpr;
	445
	446	#if IRQ_DEBUG
	447	{
	448	unsigned long bsp, sp;
	449
	450	/*
	451	* Note: if the interrupt happened while executing in
	452	* the context switch routine (ia64_switch_to), we may
	453	* get a spurious stack overflow here. This is
	454	* because the register and the memory stack are not
	455	* switched atomically.
	456	*/
	457	bsp = ia64_getreg(_IA64_REG_AR_BSP);
	458	sp = ia64_getreg(_IA64_REG_SP);
	459
	460	if ((sp - bsp) < 1024) {
7683a3f9	461	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
1da177e4	462
7683a3f9	463	if (__ratelimit(&ratelimit)) {
1da177e4 LT	464	printk("ia64_handle_irq: DANGER: less than "
	465	"1KB of free stack space!!\n"
	466	"(bsp=0x%lx, sp=%lx)\n", bsp, sp);
	467	}
	468	}
	469	}
	470	#endif /* IRQ_DEBUG */
	471
	472	/*
	473	* Always set TPR to limit maximum interrupt nesting depth to
	474	* 16 (without this, it would be ~240, which could easily lead
	475	* to kernel stack overflows).
	476	*/
	477	irq_enter();
	478	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	479	ia64_srlz_d();
	480	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af JS	481	int irq = local_vector_to_irq(vector);
66f3e6af JS	482
3be44b9c JS	483	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	484	smp_local_flush_tlb();
3611587a	485	kstat_incr_irq_this_cpu(irq);
7c730ccd	486	} else if (unlikely(IS_RESCHEDULE(vector))) {
184748cc	487	scheduler_ipi();
3611587a	488	kstat_incr_irq_this_cpu(irq);
7c730ccd	489	} else {
1da177e4 LT	490	ia64_setreg(_IA64_REG_CR_TPR, vector);
	491	ia64_srlz_d();
	492
17764d24 KK	493	if (unlikely(irq < 0)) {
	494	printk(KERN_ERR "%s: Unexpected interrupt "
	495	"vector %d on CPU %d is not mapped "
d4ed8084	496	"to any IRQ!\n", __func__, vector,
17764d24 KK	497	smp_processor_id());
	498	} else
	499	generic_handle_irq(irq);
1da177e4 LT	500
	501	/*
	502	* Disable interrupts and send EOI:
	503	*/
	504	local_irq_disable();
	505	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	506	}
	507	ia64_eoi();
	508	vector = ia64_get_ivr();
	509	}
	510	/*
	511	* This must be done after the ia64_eoi(). For example, the keyboard softirq
	512	* handler needs to be able to wait for further keyboard interrupts, which can't
	513	* come through until ia64_eoi() has been done.
	514	*/
	515	irq_exit();
7d12e780	516	set_irq_regs(old_regs);
1da177e4 LT	517	}
	518
	519	#ifdef CONFIG_HOTPLUG_CPU
	520	/*
	521	* This function emulates a interrupt processing when a cpu is about to be
	522	* brought down.
	523	*/
	524	void ia64_process_pending_intr(void)
	525	{
	526	ia64_vector vector;
	527	unsigned long saved_tpr;
	528	extern unsigned int vectors_in_migration[NR_IRQS];
	529
	530	vector = ia64_get_ivr();
	531
66f3e6af JS	532	irq_enter();
	533	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	534	ia64_srlz_d();
1da177e4 LT	535
	536	/*
	537	* Perform normal interrupt style processing
	538	*/
	539	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af	540	int irq = local_vector_to_irq(vector);
66f3e6af	541
3be44b9c JS	542	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	543	smp_local_flush_tlb();
3611587a	544	kstat_incr_irq_this_cpu(irq);
7c730ccd	545	} else if (unlikely(IS_RESCHEDULE(vector))) {
3611587a	546	kstat_incr_irq_this_cpu(irq);
7c730ccd	547	} else {
8c1addbc TL	548	struct pt_regs *old_regs = set_irq_regs(NULL);
8c1addbc TL	549
1da177e4 LT	550	ia64_setreg(_IA64_REG_CR_TPR, vector);
	551	ia64_srlz_d();
	552
	553	/*
	554	* Now try calling normal ia64_handle_irq as it would have got called
	555	* from a real intr handler. Try passing null for pt_regs, hopefully
	556	* it will work. I hope it works!.
	557	* Probably could shared code.
	558	*/
17764d24 KK	559	if (unlikely(irq < 0)) {
	560	printk(KERN_ERR "%s: Unexpected interrupt "
	561	"vector %d on CPU %d not being mapped "
d4ed8084	562	"to any IRQ!!\n", __func__, vector,
17764d24 KK	563	smp_processor_id());
	564	} else {
	565	vectors_in_migration[irq]=0;
	566	generic_handle_irq(irq);
	567	}
8c1addbc	568	set_irq_regs(old_regs);
1da177e4 LT	569
	570	/*
	571	* Disable interrupts and send EOI
	572	*/
	573	local_irq_disable();
	574	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	575	}
	576	ia64_eoi();
	577	vector = ia64_get_ivr();
	578	}
	579	irq_exit();
	580	}
	581	#endif
	582
	583
	584	#ifdef CONFIG_SMP
1da177e4	585
9b3377f9 JS	586	static irqreturn_t dummy_handler (int irq, void *dev_id)
	587	{
	588	BUG();
	589	}
	590
1da177e4 LT	591	static struct irqaction ipi_irqaction = {
1da177e4 LT	592	.handler = handle_IPI,
1da177e4 LT	593	.name = "IPI"
1da177e4 LT	594	};
9b3377f9	595
32f88400 MT	596	/*
	597	* KVM uses this interrupt to force a cpu out of guest mode
	598	*/
9b3377f9 JS	599	static struct irqaction resched_irqaction = {
9b3377f9 JS	600	.handler = dummy_handler,
9b3377f9 JS	601	.name = "resched"
9b3377f9 JS	602	};
3be44b9c JS	603
	604	static struct irqaction tlb_irqaction = {
	605	.handler = dummy_handler,
3be44b9c JS	606	.name = "tlb_flush"
	607	};
	608
1da177e4 LT	609	#endif
	610
	611	void
85cbc503	612	ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
1da177e4	613	{
1da177e4 LT	614	unsigned int irq;
1da177e4 LT	615
e1b30a39	616	irq = vec;
4994be1b	617	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
a2178334	618	irq_set_status_flags(irq, IRQ_PER_CPU);
53c909c9	619	irq_set_chip(irq, &irq_type_ia64_lsapic);
e1b30a39 YI	620	if (action)
e1b30a39 YI	621	setup_irq(irq, action);
53c909c9	622	irq_set_handler(irq, handle_percpu_irq);
1da177e4 LT	623	}
	624
	625	void __init
85cbc503	626	ia64_native_register_ipi(void)
1da177e4	627	{
1da177e4 LT	628	#ifdef CONFIG_SMP
1da177e4 LT	629	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
9b3377f9	630	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
3be44b9c	631	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
85cbc503 IY	632	#endif
	633	}
	634
	635	void __init
	636	init_IRQ (void)
	637	{
4de0a759 TL	638	#ifdef CONFIG_ACPI
	639	acpi_boot_init();
	640	#endif
85cbc503 IY	641	ia64_register_ipi();
	642	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
	643	#ifdef CONFIG_SMP
a6cd6322	644	#if defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG)
09b366b7	645	if (vector_domain_type != VECTOR_DOMAIN_NONE)
a6cd6322	646	register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
a6cd6322	647	#endif
1da177e4 LT	648	#endif
	649	#ifdef CONFIG_PERFMON
	650	pfm_init_percpu();
	651	#endif
	652	platform_irq_init();
	653	}
	654
	655	void
	656	ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
	657	{
	658	void __iomem *ipi_addr;
	659	unsigned long ipi_data;
	660	unsigned long phys_cpu_id;
	661
1da177e4	662	phys_cpu_id = cpu_physical_id(cpu);
1da177e4 LT	663
	664	/*
	665	* cpu number is in 8bit ID and 8bit EID
	666	*/
	667
	668	ipi_data = (delivery_mode << 8) \| (vector & 0xff);
	669	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) \| ((redirect & 1) << 3));
	670
	671	writeq(ipi_data, ipi_addr);
	672	}