ALSA: pcm: Move PCM_RUNTIME_CHECK() macro into local header
[linux-2.6-block.git] / arch / ia64 / kernel / irq.c
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b2441318 1// SPDX-License-Identifier: GPL-2.0
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2/*
3 * linux/arch/ia64/kernel/irq.c
4 *
5 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
6 *
7 * This file contains the code used by various IRQ handling routines:
72fdbdce 8 * asking for different IRQs should be done through these routines
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9 * instead of just grabbing them. Thus setups with different IRQ numbers
10 * shouldn't result in any weird surprises, and installing new handlers
11 * should be easier.
12 *
13 * Copyright (C) Ashok Raj<ashok.raj@intel.com>, Intel Corporation 2004
14 *
15 * 4/14/2004: Added code to handle cpu migration and do safe irq
72fdbdce 16 * migration without losing interrupts for iosapic
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17 * architecture.
18 */
19
20#include <asm/delay.h>
7c0f6ba6 21#include <linux/uaccess.h>
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22#include <linux/module.h>
23#include <linux/seq_file.h>
24#include <linux/interrupt.h>
25#include <linux/kernel_stat.h>
26
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27#include <asm/mca.h>
28
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29/*
30 * 'what should we do if we get a hw irq event on an illegal vector'.
31 * each architecture has to answer this themselves.
32 */
33void ack_bad_irq(unsigned int irq)
34{
35 printk(KERN_ERR "Unexpected irq vector 0x%x on CPU %u!\n", irq, smp_processor_id());
36}
37
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38/*
39 * Interrupt statistics:
40 */
41
42atomic_t irq_err_count;
43
44/*
45 * /proc/interrupts printing:
46 */
e3d78122 47int arch_show_interrupts(struct seq_file *p, int prec)
1da177e4 48{
e3d78122 49 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
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50 return 0;
51}
52
53#ifdef CONFIG_SMP
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54static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 };
55
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56void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
57{
1da177e4 58 if (irq < NR_IRQS) {
c42574ed 59 cpumask_copy(irq_get_affinity_mask(irq),
d3b66bf2 60 cpumask_of(cpu_logical_id(hwid)));
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61 irq_redir[irq] = (char) (redir & 0xff);
62 }
63}
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64#endif /* CONFIG_SMP */
65
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66int __init arch_early_irq_init(void)
67{
68 ia64_mca_irq_init();
69 return 0;
70}
71
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72#ifdef CONFIG_HOTPLUG_CPU
73unsigned int vectors_in_migration[NR_IRQS];
74
75/*
d3b66bf2 76 * Since cpu_online_mask is already updated, we just need to check for
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77 * affinity that has zeros
78 */
79static void migrate_irqs(void)
80{
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81 int irq, new_cpu;
82
83 for (irq=0; irq < NR_IRQS; irq++) {
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84 struct irq_desc *desc = irq_to_desc(irq);
85 struct irq_data *data = irq_desc_get_irq_data(desc);
86 struct irq_chip *chip = irq_data_get_irq_chip(data);
1da177e4 87
f5e5bf08 88 if (irqd_irq_disabled(data))
29a00277
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89 continue;
90
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91 /*
92 * No handling for now.
93 * TBD: Implement a disable function so we can now
94 * tell CPU not to respond to these local intr sources.
95 * such as ITV,CPEI,MCA etc.
96 */
428a40c5 97 if (irqd_is_per_cpu(data))
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98 continue;
99
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100 if (cpumask_any_and(irq_data_get_affinity_mask(data),
101 cpu_online_mask) >= nr_cpu_ids) {
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102 /*
103 * Save it for phase 2 processing
104 */
105 vectors_in_migration[irq] = irq;
106
d3b66bf2 107 new_cpu = cpumask_any(cpu_online_mask);
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108
109 /*
110 * Al three are essential, currently WARN_ON.. maybe panic?
111 */
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112 if (chip && chip->irq_disable &&
113 chip->irq_enable && chip->irq_set_affinity) {
114 chip->irq_disable(data);
115 chip->irq_set_affinity(data,
116 cpumask_of(new_cpu), false);
117 chip->irq_enable(data);
1da177e4 118 } else {
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119 WARN_ON((!chip || !chip->irq_disable ||
120 !chip->irq_enable ||
121 !chip->irq_set_affinity));
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122 }
123 }
124 }
125}
126
127void fixup_irqs(void)
128{
129 unsigned int irq;
130 extern void ia64_process_pending_intr(void);
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131 extern volatile int time_keeper_id;
132
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133 /* Mask ITV to disable timer */
134 ia64_set_itv(1 << 16);
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135
136 /*
137 * Find a new timesync master
138 */
139 if (smp_processor_id() == time_keeper_id) {
d3b66bf2 140 time_keeper_id = cpumask_first(cpu_online_mask);
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141 printk ("CPU %d is now promoted to time-keeper master\n", time_keeper_id);
142 }
1da177e4 143
1da177e4 144 /*
72fdbdce 145 * Phase 1: Locate IRQs bound to this cpu and
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146 * relocate them for cpu removal.
147 */
148 migrate_irqs();
149
150 /*
151 * Phase 2: Perform interrupt processing for all entries reported in
152 * local APIC.
153 */
154 ia64_process_pending_intr();
155
156 /*
157 * Phase 3: Now handle any interrupts not captured in local APIC.
158 * This is to account for cases that device interrupted during the time the
159 * rte was being disabled and re-programmed.
160 */
161 for (irq=0; irq < NR_IRQS; irq++) {
162 if (vectors_in_migration[irq]) {
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163 struct pt_regs *old_regs = set_irq_regs(NULL);
164
1da177e4 165 vectors_in_migration[irq]=0;
5fbb004a 166 generic_handle_irq(irq);
8c1addbc 167 set_irq_regs(old_regs);
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168 }
169 }
170
171 /*
172 * Now let processor die. We do irq disable and max_xtp() to
173 * ensure there is no more interrupts routed to this processor.
174 * But the local timer interrupt can have 1 pending which we
175 * take care in timer_interrupt().
176 */
177 max_xtp();
178 local_irq_disable();
179}
180#endif