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MIPS: Tracing: Reserve $12(t0) for mcount-ra-address of gcc 4.5
[linux-2.6-block.git] / arch / ia64 / kernel / entry.S
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1da177e4 1/*
f30c2269 2 * arch/ia64/kernel/entry.S
1da177e4
LT		 3 *
4 * Kernel entry points.
5 *
6 * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Copyright (C) 1999, 2002-2003
9 * Asit Mallick <Asit.K.Mallick@intel.com>
10 * Don Dugger <Don.Dugger@intel.com>
11 * Suresh Siddha <suresh.b.siddha@intel.com>
12 * Fenghua Yu <fenghua.yu@intel.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 */
16/*
17 * ia64_switch_to now places correct virtual mapping in in TR2 for
18 * kernel stack. This allows us to handle interrupts without changing
19 * to physical mode.
20 *
21 * Jonathan Nicklin <nicklin@missioncriticallinux.com>
22 * Patrick O'Rourke <orourke@missioncriticallinux.com>
23 * 11/07/2000
24 */
4df8d22b
IY		 25/*
26 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
27 * VA Linux Systems Japan K.K.
28 * pv_ops.
29 */
1da177e4
LT		 30/*
31 * Global (preserved) predicate usage on syscall entry/exit path:
32 *
33 * pKStk: See entry.h.
34 * pUStk: See entry.h.
35 * pSys: See entry.h.
36 * pNonSys: !pSys
37 */
38
1da177e4
LT		 39
40#include <asm/asmmacro.h>
41#include <asm/cache.h>
42#include <asm/errno.h>
43#include <asm/kregs.h>
39e01cb8 44#include <asm/asm-offsets.h>
1da177e4
LT		 45#include <asm/pgtable.h>
46#include <asm/percpu.h>
47#include <asm/processor.h>
48#include <asm/thread_info.h>
49#include <asm/unistd.h>
d3e75ff1 50#include <asm/ftrace.h>
1da177e4
LT		 51
52#include "minstate.h"
53
4df8d22b 54#ifdef __IA64_ASM_PARAVIRTUALIZED_NATIVE
1da177e4
LT		 55 /*
56 * execve() is special because in case of success, we need to
57 * setup a null register window frame.
58 */
59ENTRY(ia64_execve)
60 /*
61 * Allocate 8 input registers since ptrace() may clobber them
62 */
63 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
64 alloc loc1=ar.pfs,8,2,4,0
65 mov loc0=rp
66 .body
67 mov out0=in0 // filename
68 ;; // stop bit between alloc and call
69 mov out1=in1 // argv
70 mov out2=in2 // envp
71 add out3=16,sp // regs
72 br.call.sptk.many rp=sys_execve
73.ret0:
74#ifdef CONFIG_IA32_SUPPORT
75 /*
76 * Check if we're returning to ia32 mode. If so, we need to restore ia32 registers
77 * from pt_regs.
78 */
79 adds r16=PT(CR_IPSR)+16,sp
80 ;;
81 ld8 r16=[r16]
82#endif
83 cmp4.ge p6,p7=r8,r0
84 mov ar.pfs=loc1 // restore ar.pfs
85 sxt4 r8=r8 // return 64-bit result
86 ;;
87 stf.spill [sp]=f0
88(p6) cmp.ne pKStk,pUStk=r0,r0 // a successful execve() lands us in user-mode...
89 mov rp=loc0
90(p6) mov ar.pfs=r0 // clear ar.pfs on success
91(p7) br.ret.sptk.many rp
92
93 /*
94 * In theory, we'd have to zap this state only to prevent leaking of
95 * security sensitive state (e.g., if current->mm->dumpable is zero). However,
96 * this executes in less than 20 cycles even on Itanium, so it's not worth
97 * optimizing for...).
98 */
99 mov ar.unat=0; mov ar.lc=0
100 mov r4=0; mov f2=f0; mov b1=r0
101 mov r5=0; mov f3=f0; mov b2=r0
102 mov r6=0; mov f4=f0; mov b3=r0
103 mov r7=0; mov f5=f0; mov b4=r0
104 ldf.fill f12=[sp]; mov f13=f0; mov b5=r0
105 ldf.fill f14=[sp]; ldf.fill f15=[sp]; mov f16=f0
106 ldf.fill f17=[sp]; ldf.fill f18=[sp]; mov f19=f0
107 ldf.fill f20=[sp]; ldf.fill f21=[sp]; mov f22=f0
108 ldf.fill f23=[sp]; ldf.fill f24=[sp]; mov f25=f0
109 ldf.fill f26=[sp]; ldf.fill f27=[sp]; mov f28=f0
110 ldf.fill f29=[sp]; ldf.fill f30=[sp]; mov f31=f0
111#ifdef CONFIG_IA32_SUPPORT
112 tbit.nz p6,p0=r16, IA64_PSR_IS_BIT
113 movl loc0=ia64_ret_from_ia32_execve
114 ;;
115(p6) mov rp=loc0
116#endif
117 br.ret.sptk.many rp
118END(ia64_execve)
119
120/*
121 * sys_clone2(u64 flags, u64 ustack_base, u64 ustack_size, u64 parent_tidptr, u64 child_tidptr,
122 * u64 tls)
123 */
124GLOBAL_ENTRY(sys_clone2)
125 /*
126 * Allocate 8 input registers since ptrace() may clobber them
127 */
128 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
129 alloc r16=ar.pfs,8,2,6,0
130 DO_SAVE_SWITCH_STACK
131 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
132 mov loc0=rp
133 mov loc1=r16 // save ar.pfs across do_fork
134 .body
135 mov out1=in1
136 mov out3=in2
137 tbit.nz p6,p0=in0,CLONE_SETTLS_BIT
138 mov out4=in3 // parent_tidptr: valid only w/CLONE_PARENT_SETTID
139 ;;
140(p6) st8 [r2]=in5 // store TLS in r16 for copy_thread()
141 mov out5=in4 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID
142 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = &regs
143 mov out0=in0 // out0 = clone_flags
144 br.call.sptk.many rp=do_fork
145.ret1: .restore sp
146 adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack
147 mov ar.pfs=loc1
148 mov rp=loc0
149 br.ret.sptk.many rp
150END(sys_clone2)
151
152/*
153 * sys_clone(u64 flags, u64 ustack_base, u64 parent_tidptr, u64 child_tidptr, u64 tls)
154 * Deprecated. Use sys_clone2() instead.
155 */
156GLOBAL_ENTRY(sys_clone)
157 /*
158 * Allocate 8 input registers since ptrace() may clobber them
159 */
160 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
161 alloc r16=ar.pfs,8,2,6,0
162 DO_SAVE_SWITCH_STACK
163 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
164 mov loc0=rp
165 mov loc1=r16 // save ar.pfs across do_fork
166 .body
167 mov out1=in1
168 mov out3=16 // stacksize (compensates for 16-byte scratch area)
169 tbit.nz p6,p0=in0,CLONE_SETTLS_BIT
170 mov out4=in2 // parent_tidptr: valid only w/CLONE_PARENT_SETTID
171 ;;
172(p6) st8 [r2]=in4 // store TLS in r13 (tp)
173 mov out5=in3 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID
174 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = &regs
175 mov out0=in0 // out0 = clone_flags
176 br.call.sptk.many rp=do_fork
177.ret2: .restore sp
178 adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack
179 mov ar.pfs=loc1
180 mov rp=loc0
181 br.ret.sptk.many rp
182END(sys_clone)
4df8d22b 183#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
1da177e4
LT		 184
185/*
186 * prev_task <- ia64_switch_to(struct task_struct *next)
187 * With Ingo's new scheduler, interrupts are disabled when this routine gets
188 * called. The code starting at .map relies on this. The rest of the code
189 * doesn't care about the interrupt masking status.
190 */
4df8d22b 191GLOBAL_ENTRY(__paravirt_switch_to)
1da177e4
LT		 192 .prologue
193 alloc r16=ar.pfs,1,0,0,0
194 DO_SAVE_SWITCH_STACK
195 .body
196
197 adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13
198 movl r25=init_task
199 mov r27=IA64_KR(CURRENT_STACK)
200 adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0
201 dep r20=0,in0,61,3 // physical address of "next"
202 ;;
203 st8 [r22]=sp // save kernel stack pointer of old task
204 shr.u r26=r20,IA64_GRANULE_SHIFT
205 cmp.eq p7,p6=r25,in0
206 ;;
207 /*
208 * If we've already mapped this task's page, we can skip doing it again.
209 */
210(p6) cmp.eq p7,p6=r26,r27
211(p6) br.cond.dpnt .map
212 ;;
213.done:
1da177e4 214 ld8 sp=[r21] // load kernel stack pointer of new task
4df8d22b 215 MOV_TO_KR(CURRENT, in0, r8, r9) // update "current" application register
1da177e4
LT		 216 mov r8=r13 // return pointer to previously running task
217 mov r13=in0 // set "current" pointer
218 ;;
219 DO_LOAD_SWITCH_STACK
220
221#ifdef CONFIG_SMP
222 sync.i // ensure "fc"s done by this CPU are visible on other CPUs
223#endif
224 br.ret.sptk.many rp // boogie on out in new context
225
226.map:
4df8d22b 227 RSM_PSR_IC(r25) // interrupts (psr.i) are already disabled here
1da177e4
LT		 228 movl r25=PAGE_KERNEL
229 ;;
230 srlz.d
231 or r23=r25,r20 // construct PA | page properties
232 mov r25=IA64_GRANULE_SHIFT<<2
233 ;;
4df8d22b
IY		 234 MOV_TO_ITIR(p0, r25, r8)
235 MOV_TO_IFA(in0, r8) // VA of next task...
1da177e4
LT		 236 ;;
237 mov r25=IA64_TR_CURRENT_STACK
4df8d22b 238 MOV_TO_KR(CURRENT_STACK, r26, r8, r9) // remember last page we mapped...
1da177e4
LT		 239 ;;
240 itr.d dtr[r25]=r23 // wire in new mapping...
4df8d22b 241 SSM_PSR_IC_AND_SRLZ_D(r8, r9) // reenable the psr.ic bit
1da177e4 242 br.cond.sptk .done
4df8d22b 243END(__paravirt_switch_to)
1da177e4 244
4df8d22b 245#ifdef __IA64_ASM_PARAVIRTUALIZED_NATIVE
1da177e4
LT		 246/*
247 * Note that interrupts are enabled during save_switch_stack and load_switch_stack. This
248 * means that we may get an interrupt with "sp" pointing to the new kernel stack while
249 * ar.bspstore is still pointing to the old kernel backing store area. Since ar.rsc,
250 * ar.rnat, ar.bsp, and ar.bspstore are all preserved by interrupts, this is not a
251 * problem. Also, we don't need to specify unwind information for preserved registers
252 * that are not modified in save_switch_stack as the right unwind information is already
253 * specified at the call-site of save_switch_stack.
254 */
255
256/*
257 * save_switch_stack:
258 * - r16 holds ar.pfs
259 * - b7 holds address to return to
260 * - rp (b0) holds return address to save
261 */
262GLOBAL_ENTRY(save_switch_stack)
263 .prologue
264 .altrp b7
265 flushrs // flush dirty regs to backing store (must be first in insn group)
266 .save @priunat,r17
267 mov r17=ar.unat // preserve caller's
268 .body
269#ifdef CONFIG_ITANIUM
270 adds r2=16+128,sp
271 adds r3=16+64,sp
272 adds r14=SW(R4)+16,sp
273 ;;
274 st8.spill [r14]=r4,16 // spill r4
275 lfetch.fault.excl.nt1 [r3],128
276 ;;
277 lfetch.fault.excl.nt1 [r2],128
278 lfetch.fault.excl.nt1 [r3],128
279 ;;
280 lfetch.fault.excl [r2]
281 lfetch.fault.excl [r3]
282 adds r15=SW(R5)+16,sp
283#else
284 add r2=16+3*128,sp
285 add r3=16,sp
286 add r14=SW(R4)+16,sp
287 ;;
288 st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0
289 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x010
290 ;;
291 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x090
292 lfetch.fault.excl.nt1 [r2],128 // prefetch offset 0x190
293 ;;
294 lfetch.fault.excl.nt1 [r3] // prefetch offset 0x110
295 lfetch.fault.excl.nt1 [r2] // prefetch offset 0x210
296 adds r15=SW(R5)+16,sp
297#endif
298 ;;
299 st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5
300 mov.m ar.rsc=0 // put RSE in mode: enforced lazy, little endian, pl 0
301 add r2=SW(F2)+16,sp // r2 = &sw->f2
302 ;;
303 st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
304 mov.m r18=ar.fpsr // preserve fpsr
305 add r3=SW(F3)+16,sp // r3 = &sw->f3
306 ;;
307 stf.spill [r2]=f2,32
308 mov.m r19=ar.rnat
309 mov r21=b0
310
311 stf.spill [r3]=f3,32
312 st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7
313 mov r22=b1
314 ;;
315 // since we're done with the spills, read and save ar.unat:
316 mov.m r29=ar.unat
317 mov.m r20=ar.bspstore
318 mov r23=b2
319 stf.spill [r2]=f4,32
320 stf.spill [r3]=f5,32
321 mov r24=b3
322 ;;
323 st8 [r14]=r21,SW(B1)-SW(B0) // save b0
324 st8 [r15]=r23,SW(B3)-SW(B2) // save b2
325 mov r25=b4
326 mov r26=b5
327 ;;
328 st8 [r14]=r22,SW(B4)-SW(B1) // save b1
329 st8 [r15]=r24,SW(AR_PFS)-SW(B3) // save b3
330 mov r21=ar.lc // I-unit
331 stf.spill [r2]=f12,32
332 stf.spill [r3]=f13,32
333 ;;
334 st8 [r14]=r25,SW(B5)-SW(B4) // save b4
335 st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS) // save ar.pfs
336 stf.spill [r2]=f14,32
337 stf.spill [r3]=f15,32
338 ;;
339 st8 [r14]=r26 // save b5
340 st8 [r15]=r21 // save ar.lc
341 stf.spill [r2]=f16,32
342 stf.spill [r3]=f17,32
343 ;;
344 stf.spill [r2]=f18,32
345 stf.spill [r3]=f19,32
346 ;;
347 stf.spill [r2]=f20,32
348 stf.spill [r3]=f21,32
349 ;;
350 stf.spill [r2]=f22,32
351 stf.spill [r3]=f23,32
352 ;;
353 stf.spill [r2]=f24,32
354 stf.spill [r3]=f25,32
355 ;;
356 stf.spill [r2]=f26,32
357 stf.spill [r3]=f27,32
358 ;;
359 stf.spill [r2]=f28,32
360 stf.spill [r3]=f29,32
361 ;;
362 stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30)
363 stf.spill [r3]=f31,SW(PR)-SW(F31)
364 add r14=SW(CALLER_UNAT)+16,sp
365 ;;
366 st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT) // save ar.unat
367 st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat
368 mov r21=pr
369 ;;
370 st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat
371 st8 [r3]=r21 // save predicate registers
372 ;;
373 st8 [r2]=r20 // save ar.bspstore
374 st8 [r14]=r18 // save fpsr
375 mov ar.rsc=3 // put RSE back into eager mode, pl 0
376 br.cond.sptk.many b7
377END(save_switch_stack)
378
379/*
380 * load_switch_stack:
381 * - "invala" MUST be done at call site (normally in DO_LOAD_SWITCH_STACK)
382 * - b7 holds address to return to
383 * - must not touch r8-r11
384 */
4df8d22b 385GLOBAL_ENTRY(load_switch_stack)
1da177e4
LT		 386 .prologue
387 .altrp b7
388
389 .body
390 lfetch.fault.nt1 [sp]
391 adds r2=SW(AR_BSPSTORE)+16,sp
392 adds r3=SW(AR_UNAT)+16,sp
393 mov ar.rsc=0 // put RSE into enforced lazy mode
394 adds r14=SW(CALLER_UNAT)+16,sp
395 adds r15=SW(AR_FPSR)+16,sp
396 ;;
397 ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE)) // bspstore
398 ld8 r29=[r3],(SW(B1)-SW(AR_UNAT)) // unat
399 ;;
400 ld8 r21=[r2],16 // restore b0
401 ld8 r22=[r3],16 // restore b1
402 ;;
403 ld8 r23=[r2],16 // restore b2
404 ld8 r24=[r3],16 // restore b3
405 ;;
406 ld8 r25=[r2],16 // restore b4
407 ld8 r26=[r3],16 // restore b5
408 ;;
409 ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs
410 ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc
411 ;;
412 ld8 r28=[r2] // restore pr
413 ld8 r30=[r3] // restore rnat
414 ;;
415 ld8 r18=[r14],16 // restore caller's unat
416 ld8 r19=[r15],24 // restore fpsr
417 ;;
418 ldf.fill f2=[r14],32
419 ldf.fill f3=[r15],32
420 ;;
421 ldf.fill f4=[r14],32
422 ldf.fill f5=[r15],32
423 ;;
424 ldf.fill f12=[r14],32
425 ldf.fill f13=[r15],32
426 ;;
427 ldf.fill f14=[r14],32
428 ldf.fill f15=[r15],32
429 ;;
430 ldf.fill f16=[r14],32
431 ldf.fill f17=[r15],32
432 ;;
433 ldf.fill f18=[r14],32
434 ldf.fill f19=[r15],32
435 mov b0=r21
436 ;;
437 ldf.fill f20=[r14],32
438 ldf.fill f21=[r15],32
439 mov b1=r22
440 ;;
441 ldf.fill f22=[r14],32
442 ldf.fill f23=[r15],32
443 mov b2=r23
444 ;;
445 mov ar.bspstore=r27
446 mov ar.unat=r29 // establish unat holding the NaT bits for r4-r7
447 mov b3=r24
448 ;;
449 ldf.fill f24=[r14],32
450 ldf.fill f25=[r15],32
451 mov b4=r25
452 ;;
453 ldf.fill f26=[r14],32
454 ldf.fill f27=[r15],32
455 mov b5=r26
456 ;;
457 ldf.fill f28=[r14],32
458 ldf.fill f29=[r15],32
459 mov ar.pfs=r16
460 ;;
461 ldf.fill f30=[r14],32
462 ldf.fill f31=[r15],24
463 mov ar.lc=r17
464 ;;
465 ld8.fill r4=[r14],16
466 ld8.fill r5=[r15],16
467 mov pr=r28,-1
468 ;;
469 ld8.fill r6=[r14],16
470 ld8.fill r7=[r15],16
471
472 mov ar.unat=r18 // restore caller's unat
473 mov ar.rnat=r30 // must restore after bspstore but before rsc!
474 mov ar.fpsr=r19 // restore fpsr
475 mov ar.rsc=3 // put RSE back into eager mode, pl 0
476 br.cond.sptk.many b7
477END(load_switch_stack)
478
383f2835
CK		 479GLOBAL_ENTRY(prefetch_stack)
480 add r14 = -IA64_SWITCH_STACK_SIZE, sp
481 add r15 = IA64_TASK_THREAD_KSP_OFFSET, in0
482 ;;
483 ld8 r16 = [r15] // load next's stack pointer
484 lfetch.fault.excl [r14], 128
485 ;;
486 lfetch.fault.excl [r14], 128
487 lfetch.fault [r16], 128
488 ;;
489 lfetch.fault.excl [r14], 128
490 lfetch.fault [r16], 128
491 ;;
492 lfetch.fault.excl [r14], 128
493 lfetch.fault [r16], 128
494 ;;
495 lfetch.fault.excl [r14], 128
496 lfetch.fault [r16], 128
497 ;;
498 lfetch.fault [r16], 128
499 br.ret.sptk.many rp
24b8e0cc 500END(prefetch_stack)
383f2835 501
3db03b4a 502GLOBAL_ENTRY(kernel_execve)
b704882e 503 rum psr.ac
1da177e4
LT		 504 mov r15=__NR_execve // put syscall number in place
505 break __BREAK_SYSCALL
506 br.ret.sptk.many rp
3db03b4a 507END(kernel_execve)
1da177e4
LT		 508
509GLOBAL_ENTRY(clone)
510 mov r15=__NR_clone // put syscall number in place
511 break __BREAK_SYSCALL
512 br.ret.sptk.many rp
513END(clone)
514
515 /*
516 * Invoke a system call, but do some tracing before and after the call.
517 * We MUST preserve the current register frame throughout this routine
518 * because some system calls (such as ia64_execve) directly
519 * manipulate ar.pfs.
520 */
521GLOBAL_ENTRY(ia64_trace_syscall)
522 PT_REGS_UNWIND_INFO(0)
523 /*
524 * We need to preserve the scratch registers f6-f11 in case the system
525 * call is sigreturn.
526 */
527 adds r16=PT(F6)+16,sp
528 adds r17=PT(F7)+16,sp
529 ;;
530 stf.spill [r16]=f6,32
531 stf.spill [r17]=f7,32
532 ;;
533 stf.spill [r16]=f8,32
534 stf.spill [r17]=f9,32
535 ;;
536 stf.spill [r16]=f10
537 stf.spill [r17]=f11
538 br.call.sptk.many rp=syscall_trace_enter // give parent a chance to catch syscall args
f14488cc
SL		 539 cmp.lt p6,p0=r8,r0 // check tracehook
540 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
541 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
542 mov r10=0
543(p6) br.cond.sptk strace_error // syscall failed ->
1da177e4
LT		 544 adds r16=PT(F6)+16,sp
545 adds r17=PT(F7)+16,sp
546 ;;
547 ldf.fill f6=[r16],32
548 ldf.fill f7=[r17],32
549 ;;
550 ldf.fill f8=[r16],32
551 ldf.fill f9=[r17],32
552 ;;
553 ldf.fill f10=[r16]
554 ldf.fill f11=[r17]
555 // the syscall number may have changed, so re-load it and re-calculate the
556 // syscall entry-point:
557 adds r15=PT(R15)+16,sp // r15 = &pt_regs.r15 (syscall #)
558 ;;
559 ld8 r15=[r15]
560 mov r3=NR_syscalls - 1
561 ;;
562 adds r15=-1024,r15
563 movl r16=sys_call_table
564 ;;
565 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
566 cmp.leu p6,p7=r15,r3
567 ;;
568(p6) ld8 r20=[r20] // load address of syscall entry point
569(p7) movl r20=sys_ni_syscall
570 ;;
571 mov b6=r20
572 br.call.sptk.many rp=b6 // do the syscall
573.strace_check_retval:
574 cmp.lt p6,p0=r8,r0 // syscall failed?
575 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
576 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
577 mov r10=0
578(p6) br.cond.sptk strace_error // syscall failed ->
579 ;; // avoid RAW on r10
580.strace_save_retval:
581.mem.offset 0,0; st8.spill [r2]=r8 // store return value in slot for r8
582.mem.offset 8,0; st8.spill [r3]=r10 // clear error indication in slot for r10
583 br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
6f6d7582
JS		 584.ret3:
585(pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
38477ad7 586(pUStk) rsm psr.i // disable interrupts
4df8d22b 587 br.cond.sptk ia64_work_pending_syscall_end
1da177e4
LT		 588
589strace_error:
590 ld8 r3=[r2] // load pt_regs.r8
591 sub r9=0,r8 // negate return value to get errno value
592 ;;
593 cmp.ne p6,p0=r3,r0 // is pt_regs.r8!=0?
594 adds r3=16,r2 // r3=&pt_regs.r10
595 ;;
596(p6) mov r10=-1
597(p6) mov r8=r9
598 br.cond.sptk .strace_save_retval
599END(ia64_trace_syscall)
600
601 /*
602 * When traced and returning from sigreturn, we invoke syscall_trace but then
603 * go straight to ia64_leave_kernel rather than ia64_leave_syscall.
604 */
605GLOBAL_ENTRY(ia64_strace_leave_kernel)
606 PT_REGS_UNWIND_INFO(0)
607{ /*
608 * Some versions of gas generate bad unwind info if the first instruction of a
609 * procedure doesn't go into the first slot of a bundle. This is a workaround.
610 */
611 nop.m 0
612 nop.i 0
613 br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
614}
615.ret4: br.cond.sptk ia64_leave_kernel
616END(ia64_strace_leave_kernel)
617
618GLOBAL_ENTRY(ia64_ret_from_clone)
619 PT_REGS_UNWIND_INFO(0)
620{ /*
621 * Some versions of gas generate bad unwind info if the first instruction of a
622 * procedure doesn't go into the first slot of a bundle. This is a workaround.
623 */
624 nop.m 0
625 nop.i 0
626 /*
627 * We need to call schedule_tail() to complete the scheduling process.
628 * Called by ia64_switch_to() after do_fork()->copy_thread(). r8 contains the
629 * address of the previously executing task.
630 */
631 br.call.sptk.many rp=ia64_invoke_schedule_tail
632}
633.ret8:
634 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
635 ;;
636 ld4 r2=[r2]
637 ;;
638 mov r8=0
639 and r2=_TIF_SYSCALL_TRACEAUDIT,r2
640 ;;
641 cmp.ne p6,p0=r2,r0
642(p6) br.cond.spnt .strace_check_retval
643 ;; // added stop bits to prevent r8 dependency
644END(ia64_ret_from_clone)
645 // fall through
646GLOBAL_ENTRY(ia64_ret_from_syscall)
647 PT_REGS_UNWIND_INFO(0)
648 cmp.ge p6,p7=r8,r0 // syscall executed successfully?
649 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
650 mov r10=r0 // clear error indication in r10
651(p7) br.cond.spnt handle_syscall_error // handle potential syscall failure
4df8d22b
IY		 652#ifdef CONFIG_PARAVIRT
653 ;;
654 br.cond.sptk.few ia64_leave_syscall
655 ;;
656#endif /* CONFIG_PARAVIRT */
1da177e4 657END(ia64_ret_from_syscall)
4df8d22b 658#ifndef CONFIG_PARAVIRT
1da177e4 659 // fall through
4df8d22b
IY		 660#endif
661#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
662
1da177e4
LT		 663/*
664 * ia64_leave_syscall(): Same as ia64_leave_kernel, except that it doesn't
665 * need to switch to bank 0 and doesn't restore the scratch registers.
666 * To avoid leaking kernel bits, the scratch registers are set to
667 * the following known-to-be-safe values:
668 *
669 * r1: restored (global pointer)
670 * r2: cleared
671 * r3: 1 (when returning to user-level)
672 * r8-r11: restored (syscall return value(s))
673 * r12: restored (user-level stack pointer)
674 * r13: restored (user-level thread pointer)
c03f058f 675 * r14: set to __kernel_syscall_via_epc
1da177e4
LT		 676 * r15: restored (syscall #)
677 * r16-r17: cleared
678 * r18: user-level b6
679 * r19: cleared
680 * r20: user-level ar.fpsr
681 * r21: user-level b0
682 * r22: cleared
683 * r23: user-level ar.bspstore
684 * r24: user-level ar.rnat
685 * r25: user-level ar.unat
686 * r26: user-level ar.pfs
687 * r27: user-level ar.rsc
688 * r28: user-level ip
689 * r29: user-level psr
690 * r30: user-level cfm
691 * r31: user-level pr
692 * f6-f11: cleared
693 * pr: restored (user-level pr)
694 * b0: restored (user-level rp)
695 * b6: restored
c03f058f 696 * b7: set to __kernel_syscall_via_epc
1da177e4
LT		 697 * ar.unat: restored (user-level ar.unat)
698 * ar.pfs: restored (user-level ar.pfs)
699 * ar.rsc: restored (user-level ar.rsc)
700 * ar.rnat: restored (user-level ar.rnat)
701 * ar.bspstore: restored (user-level ar.bspstore)
702 * ar.fpsr: restored (user-level ar.fpsr)
703 * ar.ccv: cleared
704 * ar.csd: cleared
705 * ar.ssd: cleared
706 */
4df8d22b 707GLOBAL_ENTRY(__paravirt_leave_syscall)
1da177e4
LT		 708 PT_REGS_UNWIND_INFO(0)
709 /*
710 * work.need_resched etc. mustn't get changed by this CPU before it returns to
711 * user- or fsys-mode, hence we disable interrupts early on.
712 *
713 * p6 controls whether current_thread_info()->flags needs to be check for
714 * extra work. We always check for extra work when returning to user-level.
715 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count
716 * is 0. After extra work processing has been completed, execution
4df8d22b 717 * resumes at ia64_work_processed_syscall with p6 set to 1 if the extra-work-check
1da177e4
LT		 718 * needs to be redone.
719 */
720#ifdef CONFIG_PREEMPT
4df8d22b 721 RSM_PSR_I(p0, r2, r18) // disable interrupts
1da177e4
LT		 722 cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
723(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
724 ;;
725 .pred.rel.mutex pUStk,pKStk
726(pKStk) ld4 r21=[r20] // r21 <- preempt_count
727(pUStk) mov r21=0 // r21 <- 0
728 ;;
729 cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0)
730#else /* !CONFIG_PREEMPT */
4df8d22b 731 RSM_PSR_I(pUStk, r2, r18)
1da177e4
LT		 732 cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
733(pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
734#endif
4df8d22b
IY		 735.global __paravirt_work_processed_syscall;
736__paravirt_work_processed_syscall:
b64f34cd
HS		 737#ifdef CONFIG_VIRT_CPU_ACCOUNTING
738 adds r2=PT(LOADRS)+16,r12
94752a79 739 MOV_FROM_ITC(pUStk, p9, r22, r19) // fetch time at leave
b64f34cd
HS		 740 adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
741 ;;
742(p6) ld4 r31=[r18] // load current_thread_info()->flags
743 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
744 adds r3=PT(AR_BSPSTORE)+16,r12 // deferred
745 ;;
746#else
1da177e4
LT		 747 adds r2=PT(LOADRS)+16,r12
748 adds r3=PT(AR_BSPSTORE)+16,r12
749 adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
750 ;;
751(p6) ld4 r31=[r18] // load current_thread_info()->flags
752 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
96e01749 753 nop.i 0
1da177e4 754 ;;
b64f34cd 755#endif
87e522a0 756 mov r16=ar.bsp // M2 get existing backing store pointer
1da177e4
LT		 757 ld8 r18=[r2],PT(R9)-PT(B6) // load b6
758(p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
759 ;;
87e522a0 760 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
1da177e4
LT		 761(p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending?
762(p6) br.cond.spnt .work_pending_syscall
763 ;;
764 // start restoring the state saved on the kernel stack (struct pt_regs):
765 ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
766 ld8 r11=[r3],PT(CR_IIP)-PT(R11)
87e522a0 767(pNonSys) break 0 // bug check: we shouldn't be here if pNonSys is TRUE!
1da177e4
LT		 768 ;;
769 invala // M0|1 invalidate ALAT
4df8d22b 770 RSM_PSR_I_IC(r28, r29, r30) // M2 turn off interrupts and interruption collection
c03f058f 771 cmp.eq p9,p0=r0,r0 // A set p9 to indicate that we should restore cr.ifs
1da177e4 772
c03f058f
DMT		 773 ld8 r29=[r2],16 // M0|1 load cr.ipsr
774 ld8 r28=[r3],16 // M0|1 load cr.iip
b64f34cd
HS		 775#ifdef CONFIG_VIRT_CPU_ACCOUNTING
776(pUStk) add r14=TI_AC_LEAVE+IA64_TASK_SIZE,r13
777 ;;
778 ld8 r30=[r2],16 // M0|1 load cr.ifs
779 ld8 r25=[r3],16 // M0|1 load ar.unat
780(pUStk) add r15=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
781 ;;
782#else
c03f058f 783 mov r22=r0 // A clear r22
1da177e4
LT		 784 ;;
785 ld8 r30=[r2],16 // M0|1 load cr.ifs
1da177e4 786 ld8 r25=[r3],16 // M0|1 load ar.unat
87e522a0 787(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
1da177e4 788 ;;
b64f34cd 789#endif
1da177e4 790 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
4df8d22b 791 MOV_FROM_PSR(pKStk, r22, r21) // M2 read PSR now that interrupts are disabled
87e522a0 792 nop 0
1da177e4 793 ;;
c03f058f
DMT		 794 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0
795 ld8 r27=[r3],PT(PR)-PT(AR_RSC) // M0|1 load ar.rsc
796 mov f6=f0 // F clear f6
1da177e4 797 ;;
c03f058f
DMT		 798 ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // M0|1 load ar.rnat (may be garbage)
799 ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates
800 mov f7=f0 // F clear f7
1da177e4 801 ;;
c03f058f
DMT		 802 ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // M0|1 load ar.fpsr
803 ld8.fill r1=[r3],16 // M0|1 load r1
804(pUStk) mov r17=1 // A
1da177e4 805 ;;
b64f34cd
HS		 806#ifdef CONFIG_VIRT_CPU_ACCOUNTING
807(pUStk) st1 [r15]=r17 // M2|3
808#else
c03f058f 809(pUStk) st1 [r14]=r17 // M2|3
b64f34cd 810#endif
c03f058f
DMT		 811 ld8.fill r13=[r3],16 // M0|1
812 mov f8=f0 // F clear f8
1da177e4 813 ;;
c03f058f
DMT		 814 ld8.fill r12=[r2] // M0|1 restore r12 (sp)
815 ld8.fill r15=[r3] // M0|1 restore r15
816 mov b6=r18 // I0 restore b6
30325d17 817
a0776ec8 818 LOAD_PHYS_STACK_REG_SIZE(r17)
c03f058f
DMT		 819 mov f9=f0 // F clear f9
820(pKStk) br.cond.dpnt.many skip_rbs_switch // B
87e522a0 821
c03f058f
DMT		 822 srlz.d // M0 ensure interruption collection is off (for cover)
823 shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition
4df8d22b 824 COVER // B add current frame into dirty partition & set cr.ifs
1da177e4 825 ;;
b64f34cd
HS		 826#ifdef CONFIG_VIRT_CPU_ACCOUNTING
827 mov r19=ar.bsp // M2 get new backing store pointer
828 st8 [r14]=r22 // M save time at leave
829 mov f10=f0 // F clear f10
830
831 mov r22=r0 // A clear r22
832 movl r14=__kernel_syscall_via_epc // X
833 ;;
834#else
c03f058f
DMT		 835 mov r19=ar.bsp // M2 get new backing store pointer
836 mov f10=f0 // F clear f10
96e01749
DMT		 837
838 nop.m 0
c03f058f 839 movl r14=__kernel_syscall_via_epc // X
1da177e4 840 ;;
b64f34cd 841#endif
c03f058f
DMT		 842 mov.m ar.csd=r0 // M2 clear ar.csd
843 mov.m ar.ccv=r0 // M2 clear ar.ccv
844 mov b7=r14 // I0 clear b7 (hint with __kernel_syscall_via_epc)
1da177e4 845
c03f058f
DMT		 846 mov.m ar.ssd=r0 // M2 clear ar.ssd
847 mov f11=f0 // F clear f11
848 br.cond.sptk.many rbs_switch // B
4df8d22b 849END(__paravirt_leave_syscall)
1da177e4 850
4df8d22b 851#ifdef __IA64_ASM_PARAVIRTUALIZED_NATIVE
1da177e4
LT		 852#ifdef CONFIG_IA32_SUPPORT
853GLOBAL_ENTRY(ia64_ret_from_ia32_execve)
854 PT_REGS_UNWIND_INFO(0)
855 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
856 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
857 ;;
858 .mem.offset 0,0
859 st8.spill [r2]=r8 // store return value in slot for r8 and set unat bit
860 .mem.offset 8,0
861 st8.spill [r3]=r0 // clear error indication in slot for r10 and set unat bit
4df8d22b
IY		 862#ifdef CONFIG_PARAVIRT
863 ;;
864 // don't fall through, ia64_leave_kernel may be #define'd
865 br.cond.sptk.few ia64_leave_kernel
866 ;;
867#endif /* CONFIG_PARAVIRT */
9df6f705 868END(ia64_ret_from_ia32_execve)
4df8d22b 869#ifndef CONFIG_PARAVIRT
1da177e4 870 // fall through
4df8d22b 871#endif
1da177e4 872#endif /* CONFIG_IA32_SUPPORT */
4df8d22b
IY		 873#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
874
875GLOBAL_ENTRY(__paravirt_leave_kernel)
1da177e4
LT		 876 PT_REGS_UNWIND_INFO(0)
877 /*
878 * work.need_resched etc. mustn't get changed by this CPU before it returns to
879 * user- or fsys-mode, hence we disable interrupts early on.
880 *
881 * p6 controls whether current_thread_info()->flags needs to be check for
882 * extra work. We always check for extra work when returning to user-level.
883 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count
884 * is 0. After extra work processing has been completed, execution
885 * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check
886 * needs to be redone.
887 */
888#ifdef CONFIG_PREEMPT
4df8d22b 889 RSM_PSR_I(p0, r17, r31) // disable interrupts
1da177e4
LT		 890 cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
891(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
892 ;;
893 .pred.rel.mutex pUStk,pKStk
894(pKStk) ld4 r21=[r20] // r21 <- preempt_count
895(pUStk) mov r21=0 // r21 <- 0
896 ;;
897 cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0)
898#else
4df8d22b 899 RSM_PSR_I(pUStk, r17, r31)
1da177e4
LT		 900 cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
901(pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
902#endif
903.work_processed_kernel:
904 adds r17=TI_FLAGS+IA64_TASK_SIZE,r13
905 ;;
906(p6) ld4 r31=[r17] // load current_thread_info()->flags
907 adds r21=PT(PR)+16,r12
908 ;;
909
910 lfetch [r21],PT(CR_IPSR)-PT(PR)
911 adds r2=PT(B6)+16,r12
912 adds r3=PT(R16)+16,r12
913 ;;
914 lfetch [r21]
915 ld8 r28=[r2],8 // load b6
916 adds r29=PT(R24)+16,r12
917
918 ld8.fill r16=[r3],PT(AR_CSD)-PT(R16)
919 adds r30=PT(AR_CCV)+16,r12
920(p6) and r19=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
921 ;;
922 ld8.fill r24=[r29]
923 ld8 r15=[r30] // load ar.ccv
924(p6) cmp4.ne.unc p6,p0=r19, r0 // any special work pending?
925 ;;
926 ld8 r29=[r2],16 // load b7
927 ld8 r30=[r3],16 // load ar.csd
928(p6) br.cond.spnt .work_pending
929 ;;
930 ld8 r31=[r2],16 // load ar.ssd
931 ld8.fill r8=[r3],16
932 ;;
933 ld8.fill r9=[r2],16
934 ld8.fill r10=[r3],PT(R17)-PT(R10)
935 ;;
936 ld8.fill r11=[r2],PT(R18)-PT(R11)
937 ld8.fill r17=[r3],16
938 ;;
939 ld8.fill r18=[r2],16
940 ld8.fill r19=[r3],16
941 ;;
942 ld8.fill r20=[r2],16
943 ld8.fill r21=[r3],16
944 mov ar.csd=r30
945 mov ar.ssd=r31
946 ;;
4df8d22b 947 RSM_PSR_I_IC(r23, r22, r25) // initiate turning off of interrupt and interruption collection
1da177e4
LT		 948 invala // invalidate ALAT
949 ;;
950 ld8.fill r22=[r2],24
951 ld8.fill r23=[r3],24
952 mov b6=r28
953 ;;
954 ld8.fill r25=[r2],16
955 ld8.fill r26=[r3],16
956 mov b7=r29
957 ;;
958 ld8.fill r27=[r2],16
959 ld8.fill r28=[r3],16
960 ;;
961 ld8.fill r29=[r2],16
962 ld8.fill r30=[r3],24
963 ;;
964 ld8.fill r31=[r2],PT(F9)-PT(R31)
965 adds r3=PT(F10)-PT(F6),r3
966 ;;
967 ldf.fill f9=[r2],PT(F6)-PT(F9)
968 ldf.fill f10=[r3],PT(F8)-PT(F10)
969 ;;
970 ldf.fill f6=[r2],PT(F7)-PT(F6)
971 ;;
972 ldf.fill f7=[r2],PT(F11)-PT(F7)
973 ldf.fill f8=[r3],32
974 ;;
e7e965fa 975 srlz.d // ensure that inter. collection is off (VHPT is don't care, since text is pinned)
1da177e4
LT		 976 mov ar.ccv=r15
977 ;;
978 ldf.fill f11=[r2]
4df8d22b 979 BSW_0(r2, r3, r15) // switch back to bank 0 (no stop bit required beforehand...)
1da177e4
LT		 980 ;;
981(pUStk) mov r18=IA64_KR(CURRENT)// M2 (12 cycle read latency)
982 adds r16=PT(CR_IPSR)+16,r12
983 adds r17=PT(CR_IIP)+16,r12
984
b64f34cd
HS		 985#ifdef CONFIG_VIRT_CPU_ACCOUNTING
986 .pred.rel.mutex pUStk,pKStk
4df8d22b 987 MOV_FROM_PSR(pKStk, r22, r29) // M2 read PSR now that interrupts are disabled
94752a79 988 MOV_FROM_ITC(pUStk, p9, r22, r29) // M fetch time at leave
b64f34cd
HS		 989 nop.i 0
990 ;;
991#else
4df8d22b 992 MOV_FROM_PSR(pKStk, r22, r29) // M2 read PSR now that interrupts are disabled
1da177e4
LT		 993 nop.i 0
994 nop.i 0
995 ;;
b64f34cd 996#endif
1da177e4
LT		 997 ld8 r29=[r16],16 // load cr.ipsr
998 ld8 r28=[r17],16 // load cr.iip
999 ;;
1000 ld8 r30=[r16],16 // load cr.ifs
1001 ld8 r25=[r17],16 // load ar.unat
1002 ;;
1003 ld8 r26=[r16],16 // load ar.pfs
1004 ld8 r27=[r17],16 // load ar.rsc
1005 cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs
1006 ;;
1007 ld8 r24=[r16],16 // load ar.rnat (may be garbage)
1008 ld8 r23=[r17],16 // load ar.bspstore (may be garbage)
1009 ;;
1010 ld8 r31=[r16],16 // load predicates
1011 ld8 r21=[r17],16 // load b0
1012 ;;
1013 ld8 r19=[r16],16 // load ar.rsc value for "loadrs"
1014 ld8.fill r1=[r17],16 // load r1
1015 ;;
1016 ld8.fill r12=[r16],16
1017 ld8.fill r13=[r17],16
b64f34cd
HS		 1018#ifdef CONFIG_VIRT_CPU_ACCOUNTING
1019(pUStk) adds r3=TI_AC_LEAVE+IA64_TASK_SIZE,r18
1020#else
1da177e4 1021(pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18
b64f34cd 1022#endif
1da177e4
LT		 1023 ;;
1024 ld8 r20=[r16],16 // ar.fpsr
1025 ld8.fill r15=[r17],16
b64f34cd
HS		 1026#ifdef CONFIG_VIRT_CPU_ACCOUNTING
1027(pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18 // deferred
1028#endif
1da177e4
LT		 1029 ;;
1030 ld8.fill r14=[r16],16
1031 ld8.fill r2=[r17]
1032(pUStk) mov r17=1
1033 ;;
b64f34cd
HS		 1034#ifdef CONFIG_VIRT_CPU_ACCOUNTING
1035 // mmi_ : ld8 st1 shr;; mmi_ : st8 st1 shr;;
1036 // mib : mov add br -> mib : ld8 add br
1037 // bbb_ : br nop cover;; mbb_ : mov br cover;;
1038 //
1039 // no one require bsp in r16 if (pKStk) branch is selected.
1040(pUStk) st8 [r3]=r22 // save time at leave
1041(pUStk) st1 [r18]=r17 // restore current->thread.on_ustack
1042 shr.u r18=r19,16 // get byte size of existing "dirty" partition
1043 ;;
1044 ld8.fill r3=[r16] // deferred
1045 LOAD_PHYS_STACK_REG_SIZE(r17)
1046(pKStk) br.cond.dpnt skip_rbs_switch
1047 mov r16=ar.bsp // get existing backing store pointer
1048#else
1da177e4
LT		 1049 ld8.fill r3=[r16]
1050(pUStk) st1 [r18]=r17 // restore current->thread.on_ustack
1051 shr.u r18=r19,16 // get byte size of existing "dirty" partition
1052 ;;
1053 mov r16=ar.bsp // get existing backing store pointer
a0776ec8 1054 LOAD_PHYS_STACK_REG_SIZE(r17)
1da177e4 1055(pKStk) br.cond.dpnt skip_rbs_switch
b64f34cd 1056#endif
1da177e4
LT		 1057
1058 /*
1059 * Restore user backing store.
1060 *
1061 * NOTE: alloc, loadrs, and cover can't be predicated.
1062 */
1063(pNonSys) br.cond.dpnt dont_preserve_current_frame
4df8d22b 1064 COVER // add current frame into dirty partition and set cr.ifs
1da177e4
LT		 1065 ;;
1066 mov r19=ar.bsp // get new backing store pointer
87e522a0 1067rbs_switch:
1da177e4
LT		 1068 sub r16=r16,r18 // krbs = old bsp - size of dirty partition
1069 cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs
1070 ;;
1071 sub r19=r19,r16 // calculate total byte size of dirty partition
1072 add r18=64,r18 // don't force in0-in7 into memory...
1073 ;;
1074 shl r19=r19,16 // shift size of dirty partition into loadrs position
1075 ;;
1076dont_preserve_current_frame:
1077 /*
1078 * To prevent leaking bits between the kernel and user-space,
1079 * we must clear the stacked registers in the "invalid" partition here.
1080 * Not pretty, but at least it's fast (3.34 registers/cycle on Itanium,
1081 * 5 registers/cycle on McKinley).
1082 */
1083# define pRecurse p6
1084# define pReturn p7
1085#ifdef CONFIG_ITANIUM
1086# define Nregs 10
1087#else
1088# define Nregs 14
1089#endif
1090 alloc loc0=ar.pfs,2,Nregs-2,2,0
1091 shr.u loc1=r18,9 // RNaTslots <= floor(dirtySize / (64*8))
1092 sub r17=r17,r18 // r17 = (physStackedSize + 8) - dirtySize
1093 ;;
1094 mov ar.rsc=r19 // load ar.rsc to be used for "loadrs"
1095 shladd in0=loc1,3,r17
1096 mov in1=0
1097 ;;
1098 TEXT_ALIGN(32)
1099rse_clear_invalid:
1100#ifdef CONFIG_ITANIUM
1101 // cycle 0
1102 { .mii
1103 alloc loc0=ar.pfs,2,Nregs-2,2,0
1104 cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
1105 add out0=-Nregs*8,in0
1106}{ .mfb
1107 add out1=1,in1 // increment recursion count
1108 nop.f 0
1109 nop.b 0 // can't do br.call here because of alloc (WAW on CFM)
1110 ;;
1111}{ .mfi // cycle 1
1112 mov loc1=0
1113 nop.f 0
1114 mov loc2=0
1115}{ .mib
1116 mov loc3=0
1117 mov loc4=0
1118(pRecurse) br.call.sptk.many b0=rse_clear_invalid
1119
1120}{ .mfi // cycle 2
1121 mov loc5=0
1122 nop.f 0
1123 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
1124}{ .mib
1125 mov loc6=0
1126 mov loc7=0
1127(pReturn) br.ret.sptk.many b0
1128}
1129#else /* !CONFIG_ITANIUM */
1130 alloc loc0=ar.pfs,2,Nregs-2,2,0
1131 cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
1132 add out0=-Nregs*8,in0
1133 add out1=1,in1 // increment recursion count
1134 mov loc1=0
1135 mov loc2=0
1136 ;;
1137 mov loc3=0
1138 mov loc4=0
1139 mov loc5=0
1140 mov loc6=0
1141 mov loc7=0
9ec1a7ad 1142(pRecurse) br.call.dptk.few b0=rse_clear_invalid
1da177e4
LT		 1143 ;;
1144 mov loc8=0
1145 mov loc9=0
1146 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
1147 mov loc10=0
1148 mov loc11=0
9ec1a7ad 1149(pReturn) br.ret.dptk.many b0
1da177e4
LT		 1150#endif /* !CONFIG_ITANIUM */
1151# undef pRecurse
1152# undef pReturn
1153 ;;
1154 alloc r17=ar.pfs,0,0,0,0 // drop current register frame
1155 ;;
1156 loadrs
1157 ;;
1158skip_rbs_switch:
1159 mov ar.unat=r25 // M2
1160(pKStk) extr.u r22=r22,21,1 // I0 extract current value of psr.pp from r22
1161(pLvSys)mov r19=r0 // A clear r19 for leave_syscall, no-op otherwise
1162 ;;
1163(pUStk) mov ar.bspstore=r23 // M2
1164(pKStk) dep r29=r22,r29,21,1 // I0 update ipsr.pp with psr.pp
1165(pLvSys)mov r16=r0 // A clear r16 for leave_syscall, no-op otherwise
1166 ;;
4df8d22b 1167 MOV_TO_IPSR(p0, r29, r25) // M2
1da177e4
LT		 1168 mov ar.pfs=r26 // I0
1169(pLvSys)mov r17=r0 // A clear r17 for leave_syscall, no-op otherwise
1170
4df8d22b 1171 MOV_TO_IFS(p9, r30, r25)// M2
1da177e4
LT		 1172 mov b0=r21 // I0
1173(pLvSys)mov r18=r0 // A clear r18 for leave_syscall, no-op otherwise
1174
1175 mov ar.fpsr=r20 // M2
4df8d22b 1176 MOV_TO_IIP(r28, r25) // M2
1da177e4
LT		 1177 nop 0
1178 ;;
1179(pUStk) mov ar.rnat=r24 // M2 must happen with RSE in lazy mode
1180 nop 0
1181(pLvSys)mov r2=r0
1182
1183 mov ar.rsc=r27 // M2
1184 mov pr=r31,-1 // I0
4df8d22b 1185 RFI // B
1da177e4
LT		 1186
1187 /*
1188 * On entry:
1189 * r20 = &current->thread_info->pre_count (if CONFIG_PREEMPT)
1190 * r31 = current->thread_info->flags
1191 * On exit:
1192 * p6 = TRUE if work-pending-check needs to be redone
3633c730
HS		 1193 *
1194 * Interrupts are disabled on entry, reenabled depend on work, and
1195 * disabled on exit.
1da177e4
LT		 1196 */
1197.work_pending_syscall:
1198 add r2=-8,r2
1199 add r3=-8,r3
1200 ;;
1201 st8 [r2]=r8
1202 st8 [r3]=r10
1203.work_pending:
2e513fe4 1204 tbit.z p6,p0=r31,TIF_NEED_RESCHED // is resched not needed?
1da177e4
LT		 1205(p6) br.cond.sptk.few .notify
1206#ifdef CONFIG_PREEMPT
1207(pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1
1208 ;;
1209(pKStk) st4 [r20]=r21
1da177e4 1210#endif
4df8d22b 1211 SSM_PSR_I(p0, p6, r2) // enable interrupts
1da177e4 1212 br.call.spnt.many rp=schedule
2e513fe4 1213.ret9: cmp.eq p6,p0=r0,r0 // p6 <- 1 (re-check)
4df8d22b 1214 RSM_PSR_I(p0, r2, r20) // disable interrupts
1da177e4
LT		 1215 ;;
1216#ifdef CONFIG_PREEMPT
1217(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
1218 ;;
1219(pKStk) st4 [r20]=r0 // preempt_count() <- 0
1220#endif
4df8d22b 1221(pLvSys)br.cond.sptk.few __paravirt_pending_syscall_end
2e513fe4 1222 br.cond.sptk.many .work_processed_kernel
1da177e4
LT		 1223
1224.notify:
1225(pUStk) br.call.spnt.many rp=notify_resume_user
2e513fe4 1226.ret10: cmp.ne p6,p0=r0,r0 // p6 <- 0 (don't re-check)
4df8d22b 1227(pLvSys)br.cond.sptk.few __paravirt_pending_syscall_end
2e513fe4 1228 br.cond.sptk.many .work_processed_kernel
1da177e4 1229
4df8d22b
IY		 1230.global __paravirt_pending_syscall_end;
1231__paravirt_pending_syscall_end:
1da177e4
LT		 1232 adds r2=PT(R8)+16,r12
1233 adds r3=PT(R10)+16,r12
1234 ;;
1235 ld8 r8=[r2]
1236 ld8 r10=[r3]
4df8d22b
IY		 1237 br.cond.sptk.many __paravirt_work_processed_syscall_target
1238END(__paravirt_leave_kernel)
1da177e4 1239
4df8d22b 1240#ifdef __IA64_ASM_PARAVIRTUALIZED_NATIVE
1da177e4
LT		 1241ENTRY(handle_syscall_error)
1242 /*
1243 * Some system calls (e.g., ptrace, mmap) can return arbitrary values which could
1244 * lead us to mistake a negative return value as a failed syscall. Those syscall
1245 * must deposit a non-zero value in pt_regs.r8 to indicate an error. If
1246 * pt_regs.r8 is zero, we assume that the call completed successfully.
1247 */
1248 PT_REGS_UNWIND_INFO(0)
1249 ld8 r3=[r2] // load pt_regs.r8
1250 ;;
1251 cmp.eq p6,p7=r3,r0 // is pt_regs.r8==0?
1252 ;;
1253(p7) mov r10=-1
1254(p7) sub r8=0,r8 // negate return value to get errno
1255 br.cond.sptk ia64_leave_syscall
1256END(handle_syscall_error)
1257
1258 /*
1259 * Invoke schedule_tail(task) while preserving in0-in7, which may be needed
1260 * in case a system call gets restarted.
1261 */
1262GLOBAL_ENTRY(ia64_invoke_schedule_tail)
1263 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
1264 alloc loc1=ar.pfs,8,2,1,0
1265 mov loc0=rp
1266 mov out0=r8 // Address of previous task
1267 ;;
1268 br.call.sptk.many rp=schedule_tail
1269.ret11: mov ar.pfs=loc1
1270 mov rp=loc0
1271 br.ret.sptk.many rp
1272END(ia64_invoke_schedule_tail)
1273
1274 /*
3633c730
HS		 1275 * Setup stack and call do_notify_resume_user(), keeping interrupts
1276 * disabled.
1277 *
1278 * Note that pSys and pNonSys need to be set up by the caller.
1279 * We declare 8 input registers so the system call args get preserved,
1280 * in case we need to restart a system call.
1da177e4 1281 */
4df8d22b 1282GLOBAL_ENTRY(notify_resume_user)
1da177e4
LT		 1283 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
1284 alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
1285 mov r9=ar.unat
1286 mov loc0=rp // save return address
1287 mov out0=0 // there is no "oldset"
1288 adds out1=8,sp // out1=&sigscratch->ar_pfs
1289(pSys) mov out2=1 // out2==1 => we're in a syscall
1290 ;;
1291(pNonSys) mov out2=0 // out2==0 => not a syscall
1292 .fframe 16
bfd68594 1293 .spillsp ar.unat, 16
1da177e4
LT		 1294 st8 [sp]=r9,-16 // allocate space for ar.unat and save it
1295 st8 [out1]=loc1,-8 // save ar.pfs, out1=&sigscratch
1296 .body
1297 br.call.sptk.many rp=do_notify_resume_user
1298.ret15: .restore sp
1299 adds sp=16,sp // pop scratch stack space
1300 ;;
1301 ld8 r9=[sp] // load new unat from sigscratch->scratch_unat
1302 mov rp=loc0
1303 ;;
1304 mov ar.unat=r9
1305 mov ar.pfs=loc1
1306 br.ret.sptk.many rp
1307END(notify_resume_user)
1308
1da177e4
LT		 1309ENTRY(sys_rt_sigreturn)
1310 PT_REGS_UNWIND_INFO(0)
1311 /*
1312 * Allocate 8 input registers since ptrace() may clobber them
1313 */
1314 alloc r2=ar.pfs,8,0,1,0
1315 .prologue
1316 PT_REGS_SAVES(16)
1317 adds sp=-16,sp
1318 .body
1319 cmp.eq pNonSys,pSys=r0,r0 // sigreturn isn't a normal syscall...
1320 ;;
1321 /*
1322 * leave_kernel() restores f6-f11 from pt_regs, but since the streamlined
1323 * syscall-entry path does not save them we save them here instead. Note: we
1324 * don't need to save any other registers that are not saved by the stream-lined
1325 * syscall path, because restore_sigcontext() restores them.
1326 */
1327 adds r16=PT(F6)+32,sp
1328 adds r17=PT(F7)+32,sp
1329 ;;
1330 stf.spill [r16]=f6,32
1331 stf.spill [r17]=f7,32
1332 ;;
1333 stf.spill [r16]=f8,32
1334 stf.spill [r17]=f9,32
1335 ;;
1336 stf.spill [r16]=f10
1337 stf.spill [r17]=f11
1338 adds out0=16,sp // out0 = &sigscratch
1339 br.call.sptk.many rp=ia64_rt_sigreturn
763b3917 1340.ret19: .restore sp,0
1da177e4
LT		 1341 adds sp=16,sp
1342 ;;
1343 ld8 r9=[sp] // load new ar.unat
4df8d22b 1344 mov.sptk b7=r8,ia64_native_leave_kernel
1da177e4
LT		 1345 ;;
1346 mov ar.unat=r9
1347 br.many b7
1348END(sys_rt_sigreturn)
1349
1350GLOBAL_ENTRY(ia64_prepare_handle_unaligned)
1351 .prologue
1352 /*
1353 * r16 = fake ar.pfs, we simply need to make sure privilege is still 0
1354 */
1355 mov r16=r0
1356 DO_SAVE_SWITCH_STACK
1357 br.call.sptk.many rp=ia64_handle_unaligned // stack frame setup in ivt
1358.ret21: .body
1359 DO_LOAD_SWITCH_STACK
1360 br.cond.sptk.many rp // goes to ia64_leave_kernel
1361END(ia64_prepare_handle_unaligned)
1362
1363 //
1364 // unw_init_running(void (*callback)(info, arg), void *arg)
1365 //
1366# define EXTRA_FRAME_SIZE ((UNW_FRAME_INFO_SIZE+15)&~15)
1367
1368GLOBAL_ENTRY(unw_init_running)
1369 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
1370 alloc loc1=ar.pfs,2,3,3,0
1371 ;;
1372 ld8 loc2=[in0],8
1373 mov loc0=rp
1374 mov r16=loc1
1375 DO_SAVE_SWITCH_STACK
1376 .body
1377
1378 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
1379 .fframe IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE
1380 SWITCH_STACK_SAVES(EXTRA_FRAME_SIZE)
1381 adds sp=-EXTRA_FRAME_SIZE,sp
1382 .body
1383 ;;
1384 adds out0=16,sp // &info
1385 mov out1=r13 // current
1386 adds out2=16+EXTRA_FRAME_SIZE,sp // &switch_stack
1387 br.call.sptk.many rp=unw_init_frame_info
13881: adds out0=16,sp // &info
1389 mov b6=loc2
1390 mov loc2=gp // save gp across indirect function call
1391 ;;
1392 ld8 gp=[in0]
1393 mov out1=in1 // arg
1394 br.call.sptk.many rp=b6 // invoke the callback function
13951: mov gp=loc2 // restore gp
1396
1397 // For now, we don't allow changing registers from within
1398 // unw_init_running; if we ever want to allow that, we'd
1399 // have to do a load_switch_stack here:
1400 .restore sp
1401 adds sp=IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE,sp
1402
1403 mov ar.pfs=loc1
1404 mov rp=loc0
1405 br.ret.sptk.many rp
1406END(unw_init_running)
1407
d3e75ff1 1408#ifdef CONFIG_FUNCTION_TRACER
a14a07b8
SL		 1409#ifdef CONFIG_DYNAMIC_FTRACE
1410GLOBAL_ENTRY(_mcount)
1411 br ftrace_stub
1412END(_mcount)
1413
1414.here:
1415 br.ret.sptk.many b0
1416
1417GLOBAL_ENTRY(ftrace_caller)
1418 alloc out0 = ar.pfs, 8, 0, 4, 0
1419 mov out3 = r0
1420 ;;
1421 mov out2 = b0
1422 add r3 = 0x20, r3
1423 mov out1 = r1;
1424 br.call.sptk.many b0 = ftrace_patch_gp
1425 //this might be called from module, so we must patch gp
1426ftrace_patch_gp:
1427 movl gp=__gp
1428 mov b0 = r3
1429 ;;
1430.global ftrace_call;
1431ftrace_call:
1432{
1433 .mlx
1434 nop.m 0x0
1435 movl r3 = .here;;
1436}
1437 alloc loc0 = ar.pfs, 4, 4, 2, 0
1438 ;;
1439 mov loc1 = b0
1440 mov out0 = b0
1441 mov loc2 = r8
1442 mov loc3 = r15
1443 ;;
1444 adds out0 = -MCOUNT_INSN_SIZE, out0
1445 mov out1 = in2
1446 mov b6 = r3
1447
1448 br.call.sptk.many b0 = b6
1449 ;;
1450 mov ar.pfs = loc0
1451 mov b0 = loc1
1452 mov r8 = loc2
1453 mov r15 = loc3
1454 br ftrace_stub
1455 ;;
1456END(ftrace_caller)
1457
1458#else
d3e75ff1
SL		 1459GLOBAL_ENTRY(_mcount)
1460 movl r2 = ftrace_stub
1461 movl r3 = ftrace_trace_function;;
1462 ld8 r3 = [r3];;
1463 ld8 r3 = [r3];;
1464 cmp.eq p7,p0 = r2, r3
1465(p7) br.sptk.many ftrace_stub
1466 ;;
1467
1468 alloc loc0 = ar.pfs, 4, 4, 2, 0
1469 ;;
1470 mov loc1 = b0
1471 mov out0 = b0
1472 mov loc2 = r8
1473 mov loc3 = r15
1474 ;;
1475 adds out0 = -MCOUNT_INSN_SIZE, out0
1476 mov out1 = in2
1477 mov b6 = r3
1478
1479 br.call.sptk.many b0 = b6
1480 ;;
1481 mov ar.pfs = loc0
1482 mov b0 = loc1
1483 mov r8 = loc2
1484 mov r15 = loc3
1485 br ftrace_stub
1486 ;;
1487END(_mcount)
a14a07b8 1488#endif
d3e75ff1
SL		 1489
1490GLOBAL_ENTRY(ftrace_stub)
1491 mov r3 = b0
1492 movl r2 = _mcount_ret_helper
1493 ;;
1494 mov b6 = r2
1495 mov b7 = r3
1496 br.ret.sptk.many b6
1497
1498_mcount_ret_helper:
1499 mov b0 = r42
1500 mov r1 = r41
1501 mov ar.pfs = r40
1502 br b7
1503END(ftrace_stub)
1504
1505#endif /* CONFIG_FUNCTION_TRACER */
1506
1da177e4
LT		 1507 .rodata
1508 .align 8
1509 .globl sys_call_table
1510sys_call_table:
1511 data8 sys_ni_syscall // This must be sys_ni_syscall! See ivt.S.
1512 data8 sys_exit // 1025
1513 data8 sys_read
1514 data8 sys_write
1515 data8 sys_open
1516 data8 sys_close
1517 data8 sys_creat // 1030
1518 data8 sys_link
1519 data8 sys_unlink
1520 data8 ia64_execve
1521 data8 sys_chdir
1522 data8 sys_fchdir // 1035
1523 data8 sys_utimes
1524 data8 sys_mknod
1525 data8 sys_chmod
1526 data8 sys_chown
1527 data8 sys_lseek // 1040
1528 data8 sys_getpid
1529 data8 sys_getppid
1530 data8 sys_mount
1531 data8 sys_umount
1532 data8 sys_setuid // 1045
1533 data8 sys_getuid
1534 data8 sys_geteuid
1535 data8 sys_ptrace
1536 data8 sys_access
1537 data8 sys_sync // 1050
1538 data8 sys_fsync
1539 data8 sys_fdatasync
1540 data8 sys_kill
1541 data8 sys_rename
1542 data8 sys_mkdir // 1055
1543 data8 sys_rmdir
1544 data8 sys_dup
1134723e 1545 data8 sys_ia64_pipe
1da177e4
LT		 1546 data8 sys_times
1547 data8 ia64_brk // 1060
1548 data8 sys_setgid
1549 data8 sys_getgid
1550 data8 sys_getegid
1551 data8 sys_acct
1552 data8 sys_ioctl // 1065
1553 data8 sys_fcntl
1554 data8 sys_umask
1555 data8 sys_chroot
1556 data8 sys_ustat
1557 data8 sys_dup2 // 1070
1558 data8 sys_setreuid
1559 data8 sys_setregid
1560 data8 sys_getresuid
1561 data8 sys_setresuid
1562 data8 sys_getresgid // 1075
1563 data8 sys_setresgid
1564 data8 sys_getgroups
1565 data8 sys_setgroups
1566 data8 sys_getpgid
1567 data8 sys_setpgid // 1080
1568 data8 sys_setsid
1569 data8 sys_getsid
1570 data8 sys_sethostname
1571 data8 sys_setrlimit
1572 data8 sys_getrlimit // 1085
1573 data8 sys_getrusage
1574 data8 sys_gettimeofday
1575 data8 sys_settimeofday
1576 data8 sys_select
1577 data8 sys_poll // 1090
1578 data8 sys_symlink
1579 data8 sys_readlink
1580 data8 sys_uselib
1581 data8 sys_swapon
1582 data8 sys_swapoff // 1095
1583 data8 sys_reboot
1584 data8 sys_truncate
1585 data8 sys_ftruncate
1586 data8 sys_fchmod
1587 data8 sys_fchown // 1100
1588 data8 ia64_getpriority
1589 data8 sys_setpriority
1590 data8 sys_statfs
1591 data8 sys_fstatfs
1592 data8 sys_gettid // 1105
1593 data8 sys_semget
1594 data8 sys_semop
1595 data8 sys_semctl
1596 data8 sys_msgget
1597 data8 sys_msgsnd // 1110
1598 data8 sys_msgrcv
1599 data8 sys_msgctl
1600 data8 sys_shmget
7d87e14c 1601 data8 sys_shmat
1da177e4
LT		 1602 data8 sys_shmdt // 1115
1603 data8 sys_shmctl
1604 data8 sys_syslog
1605 data8 sys_setitimer
1606 data8 sys_getitimer
1607 data8 sys_ni_syscall // 1120 /* was: ia64_oldstat */
1608 data8 sys_ni_syscall /* was: ia64_oldlstat */
1609 data8 sys_ni_syscall /* was: ia64_oldfstat */
1610 data8 sys_vhangup
1611 data8 sys_lchown
1612 data8 sys_remap_file_pages // 1125
1613 data8 sys_wait4
1614 data8 sys_sysinfo
1615 data8 sys_clone
1616 data8 sys_setdomainname
1617 data8 sys_newuname // 1130
1618 data8 sys_adjtimex
1619 data8 sys_ni_syscall /* was: ia64_create_module */
1620 data8 sys_init_module
1621 data8 sys_delete_module
1622 data8 sys_ni_syscall // 1135 /* was: sys_get_kernel_syms */
1623 data8 sys_ni_syscall /* was: sys_query_module */
1624 data8 sys_quotactl
1625 data8 sys_bdflush
1626 data8 sys_sysfs
1627 data8 sys_personality // 1140
1628 data8 sys_ni_syscall // sys_afs_syscall
1629 data8 sys_setfsuid
1630 data8 sys_setfsgid
1631 data8 sys_getdents
1632 data8 sys_flock // 1145
1633 data8 sys_readv
1634 data8 sys_writev
1635 data8 sys_pread64
1636 data8 sys_pwrite64
1637 data8 sys_sysctl // 1150
1638 data8 sys_mmap
1639 data8 sys_munmap
1640 data8 sys_mlock
1641 data8 sys_mlockall
1642 data8 sys_mprotect // 1155
1643 data8 ia64_mremap
1644 data8 sys_msync
1645 data8 sys_munlock
1646 data8 sys_munlockall
1647 data8 sys_sched_getparam // 1160
1648 data8 sys_sched_setparam
1649 data8 sys_sched_getscheduler
1650 data8 sys_sched_setscheduler
1651 data8 sys_sched_yield
1652 data8 sys_sched_get_priority_max // 1165
1653 data8 sys_sched_get_priority_min
1654 data8 sys_sched_rr_get_interval
1655 data8 sys_nanosleep
1656 data8 sys_nfsservctl
1657 data8 sys_prctl // 1170
1658 data8 sys_getpagesize
1659 data8 sys_mmap2
1660 data8 sys_pciconfig_read
1661 data8 sys_pciconfig_write
1662 data8 sys_perfmonctl // 1175
1663 data8 sys_sigaltstack
1664 data8 sys_rt_sigaction
1665 data8 sys_rt_sigpending
1666 data8 sys_rt_sigprocmask
1667 data8 sys_rt_sigqueueinfo // 1180
1668 data8 sys_rt_sigreturn
1669 data8 sys_rt_sigsuspend
1670 data8 sys_rt_sigtimedwait
1671 data8 sys_getcwd
1672 data8 sys_capget // 1185
1673 data8 sys_capset
1674 data8 sys_sendfile64
1675 data8 sys_ni_syscall // sys_getpmsg (STREAMS)
1676 data8 sys_ni_syscall // sys_putpmsg (STREAMS)
1677 data8 sys_socket // 1190
1678 data8 sys_bind
1679 data8 sys_connect
1680 data8 sys_listen
1681 data8 sys_accept
1682 data8 sys_getsockname // 1195
1683 data8 sys_getpeername
1684 data8 sys_socketpair
1685 data8 sys_send
1686 data8 sys_sendto
1687 data8 sys_recv // 1200
1688 data8 sys_recvfrom
1689 data8 sys_shutdown
1690 data8 sys_setsockopt
1691 data8 sys_getsockopt
1692 data8 sys_sendmsg // 1205
1693 data8 sys_recvmsg
1694 data8 sys_pivot_root
1695 data8 sys_mincore
1696 data8 sys_madvise
1697 data8 sys_newstat // 1210
1698 data8 sys_newlstat
1699 data8 sys_newfstat
1700 data8 sys_clone2
1701 data8 sys_getdents64
1702 data8 sys_getunwind // 1215
1703 data8 sys_readahead
1704 data8 sys_setxattr
1705 data8 sys_lsetxattr
1706 data8 sys_fsetxattr
1707 data8 sys_getxattr // 1220
1708 data8 sys_lgetxattr
1709 data8 sys_fgetxattr
1710 data8 sys_listxattr
1711 data8 sys_llistxattr
1712 data8 sys_flistxattr // 1225
1713 data8 sys_removexattr
1714 data8 sys_lremovexattr
1715 data8 sys_fremovexattr
1716 data8 sys_tkill
1717 data8 sys_futex // 1230
1718 data8 sys_sched_setaffinity
1719 data8 sys_sched_getaffinity
1720 data8 sys_set_tid_address
1721 data8 sys_fadvise64_64
1722 data8 sys_tgkill // 1235
1723 data8 sys_exit_group
1724 data8 sys_lookup_dcookie
1725 data8 sys_io_setup
1726 data8 sys_io_destroy
1727 data8 sys_io_getevents // 1240
1728 data8 sys_io_submit
1729 data8 sys_io_cancel
1730 data8 sys_epoll_create
1731 data8 sys_epoll_ctl
1732 data8 sys_epoll_wait // 1245
1733 data8 sys_restart_syscall
1734 data8 sys_semtimedop
1735 data8 sys_timer_create
1736 data8 sys_timer_settime
1737 data8 sys_timer_gettime // 1250
1738 data8 sys_timer_getoverrun
1739 data8 sys_timer_delete
1740 data8 sys_clock_settime
1741 data8 sys_clock_gettime
1742 data8 sys_clock_getres // 1255
1743 data8 sys_clock_nanosleep
1744 data8 sys_fstatfs64
1745 data8 sys_statfs64
1746 data8 sys_mbind
1747 data8 sys_get_mempolicy // 1260
1748 data8 sys_set_mempolicy
1749 data8 sys_mq_open
1750 data8 sys_mq_unlink
1751 data8 sys_mq_timedsend
1752 data8 sys_mq_timedreceive // 1265
1753 data8 sys_mq_notify
1754 data8 sys_mq_getsetattr
a7956113 1755 data8 sys_kexec_load
1da177e4
LT		 1756 data8 sys_ni_syscall // reserved for vserver
1757 data8 sys_waitid // 1270
1758 data8 sys_add_key
1759 data8 sys_request_key
1760 data8 sys_keyctl
22e2c507
JA		 1761 data8 sys_ioprio_set
1762 data8 sys_ioprio_get // 1275
742755a1 1763 data8 sys_move_pages
d108919b
RL		 1764 data8 sys_inotify_init
1765 data8 sys_inotify_add_watch
1766 data8 sys_inotify_rm_watch
39743889 1767 data8 sys_migrate_pages // 1280
9ed2ad86
CK		 1768 data8 sys_openat
1769 data8 sys_mkdirat
1770 data8 sys_mknodat
1771 data8 sys_fchownat
1772 data8 sys_futimesat // 1285
1773 data8 sys_newfstatat
1774 data8 sys_unlinkat
1775 data8 sys_renameat
1776 data8 sys_linkat
1777 data8 sys_symlinkat // 1290
1778 data8 sys_readlinkat
1779 data8 sys_fchmodat
1780 data8 sys_faccessat
e180583b 1781 data8 sys_pselect6
ad9e39c7 1782 data8 sys_ppoll // 1295
9621a4ef 1783 data8 sys_unshare
5274f052 1784 data8 sys_splice
5c55cd63
TL		 1785 data8 sys_set_robust_list
1786 data8 sys_get_robust_list
d905b00b 1787 data8 sys_sync_file_range // 1300
70524490 1788 data8 sys_tee
912d35f8 1789 data8 sys_vmsplice
3d7559e6 1790 data8 sys_fallocate
86afa9eb 1791 data8 sys_getcpu
472118e6
TL		 1792 data8 sys_epoll_pwait // 1305
1793 data8 sys_utimensat
ae67e498 1794 data8 sys_signalfd
4d672e7a 1795 data8 sys_ni_syscall
ae67e498 1796 data8 sys_eventfd
ad9e39c7
TL		 1797 data8 sys_timerfd_create // 1310
1798 data8 sys_timerfd_settime
1799 data8 sys_timerfd_gettime
3e4d0cab
TL		 1800 data8 sys_signalfd4
1801 data8 sys_eventfd2
1802 data8 sys_epoll_create1 // 1315
1803 data8 sys_dup3
1804 data8 sys_pipe2
1805 data8 sys_inotify_init1
8851d371
TL		 1806 data8 sys_preadv
1807 data8 sys_pwritev // 1320
97de6ad1 1808 data8 sys_rt_tgsigqueueinfo
a2e27255 1809 data8 sys_recvmmsg
1da177e4
LT		 1810
1811 .org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls
4df8d22b 1812#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
Linux 6.x block layer and io_uring tree(s)