[linux-2.6-block.git] / arch / ia64 / include / asm / topology.h

/*
 * Copyright (C) 2002, Erich Focht, NEC
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#ifndef _ASM_IA64_TOPOLOGY_H
#define _ASM_IA64_TOPOLOGY_H

#include <asm/acpi.h>
#include <asm/numa.h>
#include <asm/smp.h>

#ifdef CONFIG_NUMA

/* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
#define PENALTY_FOR_NODE_WITH_CPUS 255

/*
 * Distance above which we begin to use zone reclaim
 */
#define RECLAIM_DISTANCE 15

/*
 * Returns the number of the node containing CPU 'cpu'
 */
#define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])

/*
 * Returns a bitmask of CPUs on Node 'node'.
 */
#define node_to_cpumask(node) (node_to_cpu_mask[node])
#define cpumask_of_node(node) (&node_to_cpu_mask[node])

/*
 * Returns the number of the node containing Node 'nid'.
 * Not implemented here. Multi-level hierarchies detected with
 * the help of node_distance().
 */
#define parent_node(nid) (nid)

/*
 * Returns the number of the first CPU on Node 'node'.
 */
#define node_to_first_cpu(node) (cpumask_first(cpumask_of_node(node)))

/*
 * Determines the node for a given pci bus
 */
#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node

void build_cpu_to_node_map(void);

#define SD_CPU_INIT (struct sched_domain) {		\
	.parent			= NULL,			\
	.child			= NULL,			\
	.groups			= NULL,			\
	.min_interval		= 1,			\
	.max_interval		= 4,			\
	.busy_factor		= 64,			\
	.imbalance_pct		= 125,			\
	.cache_nice_tries	= 2,			\
	.busy_idx		= 2,			\
	.idle_idx		= 1,			\
	.newidle_idx		= 2,			\
	.wake_idx		= 1,			\
	.forkexec_idx		= 1,			\
	.flags			= SD_LOAD_BALANCE	\
				| SD_BALANCE_NEWIDLE	\
				| SD_BALANCE_EXEC	\
				| SD_WAKE_AFFINE,	\
	.last_balance		= jiffies,		\
	.balance_interval	= 1,			\
	.nr_balance_failed	= 0,			\
}

/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
#define SD_NODE_INIT (struct sched_domain) {		\
	.parent			= NULL,			\
	.child			= NULL,			\
	.groups			= NULL,			\
	.min_interval		= 8,			\
	.max_interval		= 8*(min(num_online_cpus(), 32)), \
	.busy_factor		= 64,			\
	.imbalance_pct		= 125,			\
	.cache_nice_tries	= 2,			\
	.busy_idx		= 3,			\
	.idle_idx		= 2,			\
	.newidle_idx		= 2,			\
	.wake_idx		= 1,			\
	.forkexec_idx		= 1,			\
	.flags			= SD_LOAD_BALANCE	\
				| SD_BALANCE_EXEC	\
				| SD_BALANCE_FORK	\
				| SD_SERIALIZE		\
				| SD_WAKE_BALANCE,	\
	.last_balance		= jiffies,		\
	.balance_interval	= 64,			\
	.nr_balance_failed	= 0,			\
}

#endif /* CONFIG_NUMA */

#ifdef CONFIG_SMP
#define topology_physical_package_id(cpu)	(cpu_data(cpu)->socket_id)
#define topology_core_id(cpu)			(cpu_data(cpu)->core_id)
#define topology_core_siblings(cpu)		(cpu_core_map[cpu])
#define topology_thread_siblings(cpu)		(per_cpu(cpu_sibling_map, cpu))
#define topology_core_cpumask(cpu)		(&cpu_core_map[cpu])
#define topology_thread_cpumask(cpu)		(&per_cpu(cpu_sibling_map, cpu))
#define smt_capable() 				(smp_num_siblings > 1)
#endif

extern void arch_fix_phys_package_id(int num, u32 slot);

#define pcibus_to_cpumask(bus)	(pcibus_to_node(bus) == -1 ? \
					CPU_MASK_ALL : \
					node_to_cpumask(pcibus_to_node(bus)) \
				)

#define cpumask_of_pcibus(bus)	(pcibus_to_node(bus) == -1 ?		\
				 cpu_all_mask :				\
				 cpumask_from_node(pcibus_to_node(bus)))

#include <asm-generic/topology.h>

#endif /* _ASM_IA64_TOPOLOGY_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 2002, Erich Focht, NEC
	3	*
	4	* All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11	#ifndef _ASM_IA64_TOPOLOGY_H
	12	#define _ASM_IA64_TOPOLOGY_H
	13
	14	#include <asm/acpi.h>
	15	#include <asm/numa.h>
	16	#include <asm/smp.h>
	17
	18	#ifdef CONFIG_NUMA
8d08aed8 JS	19
	20	/* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
	21	#define PENALTY_FOR_NODE_WITH_CPUS 255
	22
e5ecc192 CL	23	/*
	24	* Distance above which we begin to use zone reclaim
	25	*/
	26	#define RECLAIM_DISTANCE 15
	27
1da177e4 LT	28	/*
	29	* Returns the number of the node containing CPU 'cpu'
	30	*/
	31	#define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])
	32
	33	/*
	34	* Returns a bitmask of CPUs on Node 'node'.
	35	*/
	36	#define node_to_cpumask(node) (node_to_cpu_mask[node])
fbb776c3	37	#define cpumask_of_node(node) (&node_to_cpu_mask[node])
1da177e4 LT	38
	39	/*
	40	* Returns the number of the node containing Node 'nid'.
	41	* Not implemented here. Multi-level hierarchies detected with
	42	* the help of node_distance().
	43	*/
	44	#define parent_node(nid) (nid)
	45
	46	/*
	47	* Returns the number of the first CPU on Node 'node'.
	48	*/
fbb776c3	49	#define node_to_first_cpu(node) (cpumask_first(cpumask_of_node(node)))
1da177e4	50
514604c6 CL	51	/*
	52	* Determines the node for a given pci bus
	53	*/
	54	#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
	55
1da177e4 LT	56	void build_cpu_to_node_map(void);
1da177e4 LT	57
687f1661	58	#define SD_CPU_INIT (struct sched_domain) { \
687f1661	59	.parent = NULL, \
1a848870	60	.child = NULL, \
687f1661 NP	61	.groups = NULL, \
	62	.min_interval = 1, \
	63	.max_interval = 4, \
	64	.busy_factor = 64, \
	65	.imbalance_pct = 125, \
687f1661 NP	66	.cache_nice_tries = 2, \
	67	.busy_idx = 2, \
	68	.idle_idx = 1, \
	69	.newidle_idx = 2, \
	70	.wake_idx = 1, \
	71	.forkexec_idx = 1, \
	72	.flags = SD_LOAD_BALANCE \
	73	\| SD_BALANCE_NEWIDLE \
	74	\| SD_BALANCE_EXEC \
	75	\| SD_WAKE_AFFINE, \
	76	.last_balance = jiffies, \
	77	.balance_interval = 1, \
	78	.nr_balance_failed = 0, \
	79	}
	80
1da177e4 LT	81	/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
1da177e4 LT	82	#define SD_NODE_INIT (struct sched_domain) { \
1da177e4	83	.parent = NULL, \
1a848870	84	.child = NULL, \
1da177e4	85	.groups = NULL, \
687f1661 NP	86	.min_interval = 8, \
	87	.max_interval = 8*(min(num_online_cpus(), 32)), \
	88	.busy_factor = 64, \
1da177e4	89	.imbalance_pct = 125, \
687f1661 NP	90	.cache_nice_tries = 2, \
	91	.busy_idx = 3, \
	92	.idle_idx = 2, \
1d3504fc	93	.newidle_idx = 2, \
687f1661 NP	94	.wake_idx = 1, \
687f1661 NP	95	.forkexec_idx = 1, \
1da177e4 LT	96	.flags = SD_LOAD_BALANCE \
1da177e4 LT	97	\| SD_BALANCE_EXEC \
687f1661	98	\| SD_BALANCE_FORK \
08c183f3	99	\| SD_SERIALIZE \
1da177e4 LT	100	\| SD_WAKE_BALANCE, \
1da177e4 LT	101	.last_balance = jiffies, \
687f1661	102	.balance_interval = 64, \
1da177e4 LT	103	.nr_balance_failed = 0, \
	104	}
	105
1da177e4 LT	106	#endif /* CONFIG_NUMA */
1da177e4 LT	107
69dcc991 ZY	108	#ifdef CONFIG_SMP
	109	#define topology_physical_package_id(cpu) (cpu_data(cpu)->socket_id)
	110	#define topology_core_id(cpu) (cpu_data(cpu)->core_id)
	111	#define topology_core_siblings(cpu) (cpu_core_map[cpu])
d5a7430d	112	#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
333af153 RR	113	#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
333af153 RR	114	#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu))
5c45bf27	115	#define smt_capable() (smp_num_siblings > 1)
69dcc991 ZY	116	#endif
69dcc991 ZY	117
fe086a7b AC	118	extern void arch_fix_phys_package_id(int num, u32 slot);
fe086a7b AC	119
aa6b5446 MT	120	#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
	121	CPU_MASK_ALL : \
	122	node_to_cpumask(pcibus_to_node(bus)) \
	123	)
	124
fbb776c3 RR	125	#define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? \
	126	cpu_all_mask : \
	127	cpumask_from_node(pcibus_to_node(bus)))
	128
1da177e4 LT	129	#include <asm-generic/topology.h>
	130
	131	#endif /* _ASM_IA64_TOPOLOGY_H */