[linux-block.git] / arch / ia64 / include / asm / processor.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_IA64_PROCESSOR_H
#define _ASM_IA64_PROCESSOR_H

/*
 * Copyright (C) 1998-2004 Hewlett-Packard Co
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *	Stephane Eranian <eranian@hpl.hp.com>
 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
 *
 * 11/24/98	S.Eranian	added ia64_set_iva()
 * 12/03/99	D. Mosberger	implement thread_saved_pc() via kernel unwind API
 * 06/16/00	A. Mallick	added csd/ssd/tssd for ia32 support
 */


#include <asm/intrinsics.h>
#include <asm/kregs.h>
#include <asm/ptrace.h>
#include <asm/ustack.h>

#define IA64_NUM_PHYS_STACK_REG	96
#define IA64_NUM_DBG_REGS	8

#define DEFAULT_MAP_BASE	__IA64_UL_CONST(0x2000000000000000)
#define DEFAULT_TASK_SIZE	__IA64_UL_CONST(0xa000000000000000)

/*
 * TASK_SIZE really is a mis-named.  It really is the maximum user
 * space address (plus one).  On IA-64, there are five regions of 2TB
 * each (assuming 8KB page size), for a total of 8TB of user virtual
 * address space.
 */
#define TASK_SIZE       	DEFAULT_TASK_SIZE

/*
 * This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE	(current->thread.map_base)

#define IA64_THREAD_FPH_VALID	(__IA64_UL(1) << 0)	/* floating-point high state valid? */
#define IA64_THREAD_DBG_VALID	(__IA64_UL(1) << 1)	/* debug registers valid? */
#define IA64_THREAD_PM_VALID	(__IA64_UL(1) << 2)	/* performance registers valid? */
#define IA64_THREAD_UAC_NOPRINT	(__IA64_UL(1) << 3)	/* don't log unaligned accesses */
#define IA64_THREAD_UAC_SIGBUS	(__IA64_UL(1) << 4)	/* generate SIGBUS on unaligned acc. */
#define IA64_THREAD_MIGRATION	(__IA64_UL(1) << 5)	/* require migration
							   sync at ctx sw */
#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)	/* don't log any fpswa faults */
#define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)	/* send a SIGFPE for fpswa faults */

#define IA64_THREAD_UAC_SHIFT	3
#define IA64_THREAD_UAC_MASK	(IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
#define IA64_THREAD_FPEMU_SHIFT	6
#define IA64_THREAD_FPEMU_MASK	(IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)


/*
 * This shift should be large enough to be able to represent 1000000000/itc_freq with good
 * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
 * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
 */
#define IA64_NSEC_PER_CYC_SHIFT	30

#ifndef __ASSEMBLY__

#include <linux/cache.h>
#include <linux/compiler.h>
#include <linux/threads.h>
#include <linux/types.h>
#include <linux/bitops.h>

#include <asm/fpu.h>
#include <asm/page.h>
#include <asm/percpu.h>
#include <asm/rse.h>
#include <asm/unwind.h>
#include <linux/atomic.h>
#ifdef CONFIG_NUMA
#include <asm/nodedata.h>
#endif

/* like above but expressed as bitfields for more efficient access: */
struct ia64_psr {
	__u64 reserved0 : 1;
	__u64 be : 1;
	__u64 up : 1;
	__u64 ac : 1;
	__u64 mfl : 1;
	__u64 mfh : 1;
	__u64 reserved1 : 7;
	__u64 ic : 1;
	__u64 i : 1;
	__u64 pk : 1;
	__u64 reserved2 : 1;
	__u64 dt : 1;
	__u64 dfl : 1;
	__u64 dfh : 1;
	__u64 sp : 1;
	__u64 pp : 1;
	__u64 di : 1;
	__u64 si : 1;
	__u64 db : 1;
	__u64 lp : 1;
	__u64 tb : 1;
	__u64 rt : 1;
	__u64 reserved3 : 4;
	__u64 cpl : 2;
	__u64 is : 1;
	__u64 mc : 1;
	__u64 it : 1;
	__u64 id : 1;
	__u64 da : 1;
	__u64 dd : 1;
	__u64 ss : 1;
	__u64 ri : 2;
	__u64 ed : 1;
	__u64 bn : 1;
	__u64 reserved4 : 19;
};

union ia64_isr {
	__u64  val;
	struct {
		__u64 code : 16;
		__u64 vector : 8;
		__u64 reserved1 : 8;
		__u64 x : 1;
		__u64 w : 1;
		__u64 r : 1;
		__u64 na : 1;
		__u64 sp : 1;
		__u64 rs : 1;
		__u64 ir : 1;
		__u64 ni : 1;
		__u64 so : 1;
		__u64 ei : 2;
		__u64 ed : 1;
		__u64 reserved2 : 20;
	};
};

union ia64_lid {
	__u64 val;
	struct {
		__u64  rv  : 16;
		__u64  eid : 8;
		__u64  id  : 8;
		__u64  ig  : 32;
	};
};

union ia64_tpr {
	__u64 val;
	struct {
		__u64 ig0 : 4;
		__u64 mic : 4;
		__u64 rsv : 8;
		__u64 mmi : 1;
		__u64 ig1 : 47;
	};
};

union ia64_itir {
	__u64 val;
	struct {
		__u64 rv3  :  2; /* 0-1 */
		__u64 ps   :  6; /* 2-7 */
		__u64 key  : 24; /* 8-31 */
		__u64 rv4  : 32; /* 32-63 */
	};
};

union  ia64_rr {
	__u64 val;
	struct {
		__u64  ve	:  1;  /* enable hw walker */
		__u64  reserved0:  1;  /* reserved */
		__u64  ps	:  6;  /* log page size */
		__u64  rid	: 24;  /* region id */
		__u64  reserved1: 32;  /* reserved */
	};
};

/*
 * CPU type, hardware bug flags, and per-CPU state.  Frequently used
 * state comes earlier:
 */
struct cpuinfo_ia64 {
	unsigned int softirq_pending;
	unsigned long itm_delta;	/* # of clock cycles between clock ticks */
	unsigned long itm_next;		/* interval timer mask value to use for next clock tick */
	unsigned long nsec_per_cyc;	/* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
	unsigned long unimpl_va_mask;	/* mask of unimplemented virtual address bits (from PAL) */
	unsigned long unimpl_pa_mask;	/* mask of unimplemented physical address bits (from PAL) */
	unsigned long itc_freq;		/* frequency of ITC counter */
	unsigned long proc_freq;	/* frequency of processor */
	unsigned long cyc_per_usec;	/* itc_freq/1000000 */
	unsigned long ptce_base;
	unsigned int ptce_count[2];
	unsigned int ptce_stride[2];
	struct task_struct *ksoftirqd;	/* kernel softirq daemon for this CPU */

#ifdef CONFIG_SMP
	unsigned long loops_per_jiffy;
	int cpu;
	unsigned int socket_id;	/* physical processor socket id */
	unsigned short core_id;	/* core id */
	unsigned short thread_id; /* thread id */
	unsigned short num_log;	/* Total number of logical processors on
				 * this socket that were successfully booted */
	unsigned char cores_per_socket;	/* Cores per processor socket */
	unsigned char threads_per_core;	/* Threads per core */
#endif

	/* CPUID-derived information: */
	unsigned long ppn;
	unsigned long features;
	unsigned char number;
	unsigned char revision;
	unsigned char model;
	unsigned char family;
	unsigned char archrev;
	char vendor[16];
	char *model_name;

#ifdef CONFIG_NUMA
	struct ia64_node_data *node_data;
#endif
};

DECLARE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info);

/*
 * The "local" data variable.  It refers to the per-CPU data of the currently executing
 * CPU, much like "current" points to the per-task data of the currently executing task.
 * Do not use the address of local_cpu_data, since it will be different from
 * cpu_data(smp_processor_id())!
 */
#define local_cpu_data		(&__ia64_per_cpu_var(ia64_cpu_info))
#define cpu_data(cpu)		(&per_cpu(ia64_cpu_info, cpu))

extern void print_cpu_info (struct cpuinfo_ia64 *);

typedef struct {
	unsigned long seg;
} mm_segment_t;

#define SET_UNALIGN_CTL(task,value)								\
({												\
	(task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK)			\
				| (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK));	\
	0;											\
})
#define GET_UNALIGN_CTL(task,addr)								\
({												\
	put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT,	\
		 (int __user *) (addr));							\
})

#define SET_FPEMU_CTL(task,value)								\
({												\
	(task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK)		\
			  | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK));	\
	0;											\
})
#define GET_FPEMU_CTL(task,addr)								\
({												\
	put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT,	\
		 (int __user *) (addr));							\
})

struct thread_struct {
	__u32 flags;			/* various thread flags (see IA64_THREAD_*) */
	/* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
	__u8 on_ustack;			/* executing on user-stacks? */
	__u8 pad[3];
	__u64 ksp;			/* kernel stack pointer */
	__u64 map_base;			/* base address for get_unmapped_area() */
	__u64 rbs_bot;			/* the base address for the RBS */
	int last_fph_cpu;		/* CPU that may hold the contents of f32-f127 */

#ifdef CONFIG_PERFMON
	void *pfm_context;		     /* pointer to detailed PMU context */
	unsigned long pfm_needs_checking;    /* when >0, pending perfmon work on kernel exit */
# define INIT_THREAD_PM		.pfm_context =		NULL,     \
				.pfm_needs_checking =	0UL,
#else
# define INIT_THREAD_PM
#endif
	unsigned long dbr[IA64_NUM_DBG_REGS];
	unsigned long ibr[IA64_NUM_DBG_REGS];
	struct ia64_fpreg fph[96];	/* saved/loaded on demand */
};

#define INIT_THREAD {						\
	.flags =	0,					\
	.on_ustack =	0,					\
	.ksp =		0,					\
	.map_base =	DEFAULT_MAP_BASE,			\
	.rbs_bot =	STACK_TOP - DEFAULT_USER_STACK_SIZE,	\
	.last_fph_cpu =  -1,					\
	INIT_THREAD_PM						\
	.dbr =		{0, },					\
	.ibr =		{0, },					\
	.fph =		{{{{0}}}, }				\
}

#define start_thread(regs,new_ip,new_sp) do {							\
	regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL))		\
			 & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS));		\
	regs->cr_iip = new_ip;									\
	regs->ar_rsc = 0xf;		/* eager mode, privilege level 3 */			\
	regs->ar_rnat = 0;									\
	regs->ar_bspstore = current->thread.rbs_bot;						\
	regs->ar_fpsr = FPSR_DEFAULT;								\
	regs->loadrs = 0;									\
	regs->r8 = get_dumpable(current->mm);	/* set "don't zap registers" flag */		\
	regs->r12 = new_sp - 16;	/* allocate 16 byte scratch area */			\
	if (unlikely(get_dumpable(current->mm) != SUID_DUMP_USER)) {	\
		/*										\
		 * Zap scratch regs to avoid leaking bits between processes with different	\
		 * uid/privileges.								\
		 */										\
		regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0;					\
		regs->r1 = 0; regs->r9  = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0;	\
	}											\
} while (0)

/* Forward declarations, a strange C thing... */
struct mm_struct;
struct task_struct;

/*
 * Free all resources held by a thread. This is called after the
 * parent of DEAD_TASK has collected the exit status of the task via
 * wait().
 */
#define release_thread(dead_task)

/* Get wait channel for task P.  */
extern unsigned long get_wchan (struct task_struct *p);

/* Return instruction pointer of blocked task TSK.  */
#define KSTK_EIP(tsk)					\
  ({							\
	struct pt_regs *_regs = task_pt_regs(tsk);	\
	_regs->cr_iip + ia64_psr(_regs)->ri;		\
  })

/* Return stack pointer of blocked task TSK.  */
#define KSTK_ESP(tsk)  ((tsk)->thread.ksp)

extern void ia64_getreg_unknown_kr (void);
extern void ia64_setreg_unknown_kr (void);

#define ia64_get_kr(regnum)					\
({								\
	unsigned long r = 0;					\
								\
	switch (regnum) {					\
	    case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break;	\
	    case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break;	\
	    case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break;	\
	    case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break;	\
	    case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break;	\
	    case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break;	\
	    case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break;	\
	    case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break;	\
	    default: ia64_getreg_unknown_kr(); break;		\
	}							\
	r;							\
})

#define ia64_set_kr(regnum, r) 					\
({								\
	switch (regnum) {					\
	    case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break;	\
	    case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break;	\
	    case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break;	\
	    case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break;	\
	    case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break;	\
	    case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break;	\
	    case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break;	\
	    case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break;	\
	    default: ia64_setreg_unknown_kr(); break;		\
	}							\
})

/*
 * The following three macros can't be inline functions because we don't have struct
 * task_struct at this point.
 */

/*
 * Return TRUE if task T owns the fph partition of the CPU we're running on.
 * Must be called from code that has preemption disabled.
 */
#define ia64_is_local_fpu_owner(t)								\
({												\
	struct task_struct *__ia64_islfo_task = (t);						\
	(__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id()				\
	 && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER));	\
})

/*
 * Mark task T as owning the fph partition of the CPU we're running on.
 * Must be called from code that has preemption disabled.
 */
#define ia64_set_local_fpu_owner(t) do {						\
	struct task_struct *__ia64_slfo_task = (t);					\
	__ia64_slfo_task->thread.last_fph_cpu = smp_processor_id();			\
	ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task);		\
} while (0)

/* Mark the fph partition of task T as being invalid on all CPUs.  */
#define ia64_drop_fpu(t)	((t)->thread.last_fph_cpu = -1)

extern void __ia64_init_fpu (void);
extern void __ia64_save_fpu (struct ia64_fpreg *fph);
extern void __ia64_load_fpu (struct ia64_fpreg *fph);
extern void ia64_save_debug_regs (unsigned long *save_area);
extern void ia64_load_debug_regs (unsigned long *save_area);

#define ia64_fph_enable()	do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
#define ia64_fph_disable()	do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)

/* load fp 0.0 into fph */
static inline void
ia64_init_fpu (void) {
	ia64_fph_enable();
	__ia64_init_fpu();
	ia64_fph_disable();
}

/* save f32-f127 at FPH */
static inline void
ia64_save_fpu (struct ia64_fpreg *fph) {
	ia64_fph_enable();
	__ia64_save_fpu(fph);
	ia64_fph_disable();
}

/* load f32-f127 from FPH */
static inline void
ia64_load_fpu (struct ia64_fpreg *fph) {
	ia64_fph_enable();
	__ia64_load_fpu(fph);
	ia64_fph_disable();
}

static inline __u64
ia64_clear_ic (void)
{
	__u64 psr;
	psr = ia64_getreg(_IA64_REG_PSR);
	ia64_stop();
	ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
	ia64_srlz_i();
	return psr;
}

/*
 * Restore the psr.
 */
static inline void
ia64_set_psr (__u64 psr)
{
	ia64_stop();
	ia64_setreg(_IA64_REG_PSR_L, psr);
	ia64_srlz_i();
}

/*
 * Insert a translation into an instruction and/or data translation
 * register.
 */
static inline void
ia64_itr (__u64 target_mask, __u64 tr_num,
	  __u64 vmaddr, __u64 pte,
	  __u64 log_page_size)
{
	ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
	ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
	ia64_stop();
	if (target_mask & 0x1)
		ia64_itri(tr_num, pte);
	if (target_mask & 0x2)
		ia64_itrd(tr_num, pte);
}

/*
 * Insert a translation into the instruction and/or data translation
 * cache.
 */
static inline void
ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
	  __u64 log_page_size)
{
	ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
	ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
	ia64_stop();
	/* as per EAS2.6, itc must be the last instruction in an instruction group */
	if (target_mask & 0x1)
		ia64_itci(pte);
	if (target_mask & 0x2)
		ia64_itcd(pte);
}

/*
 * Purge a range of addresses from instruction and/or data translation
 * register(s).
 */
static inline void
ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
{
	if (target_mask & 0x1)
		ia64_ptri(vmaddr, (log_size << 2));
	if (target_mask & 0x2)
		ia64_ptrd(vmaddr, (log_size << 2));
}

/* Set the interrupt vector address.  The address must be suitably aligned (32KB).  */
static inline void
ia64_set_iva (void *ivt_addr)
{
	ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
	ia64_srlz_i();
}

/* Set the page table address and control bits.  */
static inline void
ia64_set_pta (__u64 pta)
{
	/* Note: srlz.i implies srlz.d */
	ia64_setreg(_IA64_REG_CR_PTA, pta);
	ia64_srlz_i();
}

static inline void
ia64_eoi (void)
{
	ia64_setreg(_IA64_REG_CR_EOI, 0);
	ia64_srlz_d();
}

#define cpu_relax()	ia64_hint(ia64_hint_pause)

static inline int
ia64_get_irr(unsigned int vector)
{
	unsigned int reg = vector / 64;
	unsigned int bit = vector % 64;
	u64 irr;

	switch (reg) {
	case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
	case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
	case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
	case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
	}

	return test_bit(bit, &irr);
}

static inline void
ia64_set_lrr0 (unsigned long val)
{
	ia64_setreg(_IA64_REG_CR_LRR0, val);
	ia64_srlz_d();
}

static inline void
ia64_set_lrr1 (unsigned long val)
{
	ia64_setreg(_IA64_REG_CR_LRR1, val);
	ia64_srlz_d();
}


/*
 * Given the address to which a spill occurred, return the unat bit
 * number that corresponds to this address.
 */
static inline __u64
ia64_unat_pos (void *spill_addr)
{
	return ((__u64) spill_addr >> 3) & 0x3f;
}

/*
 * Set the NaT bit of an integer register which was spilled at address
 * SPILL_ADDR.  UNAT is the mask to be updated.
 */
static inline void
ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
{
	__u64 bit = ia64_unat_pos(spill_addr);
	__u64 mask = 1UL << bit;

	*unat = (*unat & ~mask) | (nat << bit);
}

/*
 * Get the current instruction/program counter value.
 */
#define current_text_addr() \
	({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })

static inline __u64
ia64_get_ivr (void)
{
	__u64 r;
	ia64_srlz_d();
	r = ia64_getreg(_IA64_REG_CR_IVR);
	ia64_srlz_d();
	return r;
}

static inline void
ia64_set_dbr (__u64 regnum, __u64 value)
{
	__ia64_set_dbr(regnum, value);
#ifdef CONFIG_ITANIUM
	ia64_srlz_d();
#endif
}

static inline __u64
ia64_get_dbr (__u64 regnum)
{
	__u64 retval;

	retval = __ia64_get_dbr(regnum);
#ifdef CONFIG_ITANIUM
	ia64_srlz_d();
#endif
	return retval;
}

static inline __u64
ia64_rotr (__u64 w, __u64 n)
{
	return (w >> n) | (w << (64 - n));
}

#define ia64_rotl(w,n)	ia64_rotr((w), (64) - (n))

/*
 * Take a mapped kernel address and return the equivalent address
 * in the region 7 identity mapped virtual area.
 */
static inline void *
ia64_imva (void *addr)
{
	void *result;
	result = (void *) ia64_tpa(addr);
	return __va(result);
}

#define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH
#define PREFETCH_STRIDE			L1_CACHE_BYTES

static inline void
prefetch (const void *x)
{
	 ia64_lfetch(ia64_lfhint_none, x);
}

static inline void
prefetchw (const void *x)
{
	ia64_lfetch_excl(ia64_lfhint_none, x);
}

#define spin_lock_prefetch(x)	prefetchw(x)

extern unsigned long boot_option_idle_override;

enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
			 IDLE_NOMWAIT, IDLE_POLL};

void default_idle(void);

#define ia64_platform_is(x) (strcmp(x, ia64_platform_name) == 0)

#endif /* !__ASSEMBLY__ */

#endif /* _ASM_IA64_PROCESSOR_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 LT	2	#ifndef _ASM_IA64_PROCESSOR_H
	3	#define _ASM_IA64_PROCESSOR_H
	4
	5	/*
	6	* Copyright (C) 1998-2004 Hewlett-Packard Co
	7	* David Mosberger-Tang <davidm@hpl.hp.com>
	8	* Stephane Eranian <eranian@hpl.hp.com>
	9	* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
	10	* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
	11	*
	12	* 11/24/98 S.Eranian added ia64_set_iva()
	13	* 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
	14	* 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
	15	*/
	16
1da177e4 LT	17
	18	#include <asm/intrinsics.h>
	19	#include <asm/kregs.h>
	20	#include <asm/ptrace.h>
	21	#include <asm/ustack.h>
	22
a0776ec8	23	#define IA64_NUM_PHYS_STACK_REG 96
1da177e4	24	#define IA64_NUM_DBG_REGS 8
1da177e4 LT	25
	26	#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
	27	#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
	28
	29	/*
	30	* TASK_SIZE really is a mis-named. It really is the maximum user
	31	* space address (plus one). On IA-64, there are five regions of 2TB
	32	* each (assuming 8KB page size), for a total of 8TB of user virtual
	33	* address space.
	34	*/
c7173271	35	#define TASK_SIZE DEFAULT_TASK_SIZE
1da177e4	36
1da177e4 LT	37	/*
	38	* This decides where the kernel will search for a free chunk of vm
	39	* space during mmap's.
	40	*/
	41	#define TASK_UNMAPPED_BASE (current->thread.map_base)
	42
	43	#define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
	44	#define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
	45	#define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
	46	#define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
	47	#define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
e08e6c52 BC	48	#define IA64_THREAD_MIGRATION (__IA64_UL(1) << 5) /* require migration
e08e6c52 BC	49	sync at ctx sw */
1da177e4 LT	50	#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */
	51	#define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
	52
	53	#define IA64_THREAD_UAC_SHIFT 3
	54	#define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT \| IA64_THREAD_UAC_SIGBUS)
	55	#define IA64_THREAD_FPEMU_SHIFT 6
	56	#define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT \| IA64_THREAD_FPEMU_SIGFPE)
	57
	58
	59	/*
	60	* This shift should be large enough to be able to represent 1000000000/itc_freq with good
	61	* accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
	62	* (this will give enough slack to represent 10 seconds worth of time as a scaled number).
	63	*/
	64	#define IA64_NSEC_PER_CYC_SHIFT 30
	65
	66	#ifndef __ASSEMBLY__
	67
	68	#include <linux/cache.h>
	69	#include <linux/compiler.h>
	70	#include <linux/threads.h>
	71	#include <linux/types.h>
c28aa1f0	72	#include <linux/bitops.h>
1da177e4 LT	73
	74	#include <asm/fpu.h>
	75	#include <asm/page.h>
	76	#include <asm/percpu.h>
	77	#include <asm/rse.h>
	78	#include <asm/unwind.h>
60063497	79	#include <linux/atomic.h>
1da177e4 LT	80	#ifdef CONFIG_NUMA
	81	#include <asm/nodedata.h>
	82	#endif
	83
	84	/* like above but expressed as bitfields for more efficient access: */
	85	struct ia64_psr {
	86	__u64 reserved0 : 1;
	87	__u64 be : 1;
	88	__u64 up : 1;
	89	__u64 ac : 1;
	90	__u64 mfl : 1;
	91	__u64 mfh : 1;
	92	__u64 reserved1 : 7;
	93	__u64 ic : 1;
	94	__u64 i : 1;
	95	__u64 pk : 1;
	96	__u64 reserved2 : 1;
	97	__u64 dt : 1;
	98	__u64 dfl : 1;
	99	__u64 dfh : 1;
	100	__u64 sp : 1;
	101	__u64 pp : 1;
	102	__u64 di : 1;
	103	__u64 si : 1;
	104	__u64 db : 1;
	105	__u64 lp : 1;
	106	__u64 tb : 1;
	107	__u64 rt : 1;
	108	__u64 reserved3 : 4;
	109	__u64 cpl : 2;
	110	__u64 is : 1;
	111	__u64 mc : 1;
	112	__u64 it : 1;
	113	__u64 id : 1;
	114	__u64 da : 1;
	115	__u64 dd : 1;
	116	__u64 ss : 1;
	117	__u64 ri : 2;
	118	__u64 ed : 1;
	119	__u64 bn : 1;
	120	__u64 reserved4 : 19;
	121	};
	122
e235f345 XZ	123	union ia64_isr {
	124	__u64 val;
	125	struct {
	126	__u64 code : 16;
	127	__u64 vector : 8;
	128	__u64 reserved1 : 8;
	129	__u64 x : 1;
	130	__u64 w : 1;
	131	__u64 r : 1;
	132	__u64 na : 1;
	133	__u64 sp : 1;
	134	__u64 rs : 1;
	135	__u64 ir : 1;
	136	__u64 ni : 1;
	137	__u64 so : 1;
	138	__u64 ei : 2;
	139	__u64 ed : 1;
	140	__u64 reserved2 : 20;
	141	};
	142	};
	143
	144	union ia64_lid {
	145	__u64 val;
	146	struct {
	147	__u64 rv : 16;
	148	__u64 eid : 8;
	149	__u64 id : 8;
	150	__u64 ig : 32;
	151	};
	152	};
	153
	154	union ia64_tpr {
	155	__u64 val;
	156	struct {
	157	__u64 ig0 : 4;
	158	__u64 mic : 4;
	159	__u64 rsv : 8;
	160	__u64 mmi : 1;
	161	__u64 ig1 : 47;
	162	};
	163	};
	164
	165	union ia64_itir {
	166	__u64 val;
	167	struct {
	168	__u64 rv3 : 2; /* 0-1 */
	169	__u64 ps : 6; /* 2-7 */
	170	__u64 key : 24; /* 8-31 */
	171	__u64 rv4 : 32; /* 32-63 */
	172	};
	173	};
	174
	175	union ia64_rr {
	176	__u64 val;
	177	struct {
	178	__u64 ve : 1; /* enable hw walker */
	179	__u64 reserved0: 1; /* reserved */
	180	__u64 ps : 6; /* log page size */
	181	__u64 rid : 24; /* region id */
	182	__u64 reserved1: 32; /* reserved */
	183	};
	184	};
	185
1da177e4 LT	186	/*
	187	* CPU type, hardware bug flags, and per-CPU state. Frequently used
	188	* state comes earlier:
	189	*/
	190	struct cpuinfo_ia64 {
e088a4ad MW	191	unsigned int softirq_pending;
	192	unsigned long itm_delta; /* # of clock cycles between clock ticks */
	193	unsigned long itm_next; /* interval timer mask value to use for next clock tick */
	194	unsigned long nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
	195	unsigned long unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
	196	unsigned long unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
	197	unsigned long itc_freq; /* frequency of ITC counter */
	198	unsigned long proc_freq; /* frequency of processor */
	199	unsigned long cyc_per_usec; /* itc_freq/1000000 */
	200	unsigned long ptce_base;
	201	unsigned int ptce_count[2];
	202	unsigned int ptce_stride[2];
1da177e4 LT	203	struct task_struct ksoftirqd; / kernel softirq daemon for this CPU */
	204
	205	#ifdef CONFIG_SMP
e088a4ad	206	unsigned long loops_per_jiffy;
1da177e4	207	int cpu;
e088a4ad MW	208	unsigned int socket_id; /* physical processor socket id */
	209	unsigned short core_id; /* core id */
	210	unsigned short thread_id; /* thread id */
	211	unsigned short num_log; /* Total number of logical processors on
e927ecb0	212	* this socket that were successfully booted */
e088a4ad MW	213	unsigned char cores_per_socket; /* Cores per processor socket */
e088a4ad MW	214	unsigned char threads_per_core; /* Threads per core */
1da177e4 LT	215	#endif
	216
	217	/* CPUID-derived information: */
e088a4ad MW	218	unsigned long ppn;
	219	unsigned long features;
	220	unsigned char number;
	221	unsigned char revision;
	222	unsigned char model;
	223	unsigned char family;
	224	unsigned char archrev;
1da177e4	225	char vendor[16];
76d08bb3	226	char *model_name;
1da177e4 LT	227
	228	#ifdef CONFIG_NUMA
	229	struct ia64_node_data *node_data;
	230	#endif
	231	};
	232
877105cc	233	DECLARE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info);
1da177e4 LT	234
	235	/*
	236	* The "local" data variable. It refers to the per-CPU data of the currently executing
	237	* CPU, much like "current" points to the per-task data of the currently executing task.
	238	* Do not use the address of local_cpu_data, since it will be different from
	239	* cpu_data(smp_processor_id())!
	240	*/
877105cc TH	241	#define local_cpu_data (&__ia64_per_cpu_var(ia64_cpu_info))
877105cc TH	242	#define cpu_data(cpu) (&per_cpu(ia64_cpu_info, cpu))
1da177e4	243
1da177e4 LT	244	extern void print_cpu_info (struct cpuinfo_ia64 *);
	245
	246	typedef struct {
	247	unsigned long seg;
	248	} mm_segment_t;
	249
	250	#define SET_UNALIGN_CTL(task,value) \
	251	({ \
	252	(task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
	253	\| (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
	254	0; \
	255	})
	256	#define GET_UNALIGN_CTL(task,addr) \
	257	({ \
	258	put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
	259	(int __user *) (addr)); \
	260	})
	261
	262	#define SET_FPEMU_CTL(task,value) \
	263	({ \
	264	(task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \
	265	\| (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \
	266	0; \
	267	})
	268	#define GET_FPEMU_CTL(task,addr) \
	269	({ \
	270	put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \
	271	(int __user *) (addr)); \
	272	})
	273
1da177e4 LT	274	struct thread_struct {
	275	__u32 flags; /* various thread flags (see IA64_THREAD_) /
	276	/* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
	277	__u8 on_ustack; /* executing on user-stacks? */
	278	__u8 pad[3];
	279	__u64 ksp; /* kernel stack pointer */
	280	__u64 map_base; /* base address for get_unmapped_area() */
1da177e4 LT	281	__u64 rbs_bot; /* the base address for the RBS */
	282	int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */
	283
1da177e4	284	#ifdef CONFIG_PERFMON
1da177e4 LT	285	void pfm_context; / pointer to detailed PMU context */
1da177e4 LT	286	unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */
35589a8f	287	# define INIT_THREAD_PM .pfm_context = NULL, \
1da177e4 LT	288	.pfm_needs_checking = 0UL,
	289	#else
	290	# define INIT_THREAD_PM
	291	#endif
e088a4ad MW	292	unsigned long dbr[IA64_NUM_DBG_REGS];
e088a4ad MW	293	unsigned long ibr[IA64_NUM_DBG_REGS];
1da177e4 LT	294	struct ia64_fpreg fph[96]; /* saved/loaded on demand */
	295	};
	296
	297	#define INIT_THREAD { \
	298	.flags = 0, \
	299	.on_ustack = 0, \
	300	.ksp = 0, \
	301	.map_base = DEFAULT_MAP_BASE, \
	302	.rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \
1da177e4	303	.last_fph_cpu = -1, \
1da177e4 LT	304	INIT_THREAD_PM \
	305	.dbr = {0, }, \
	306	.ibr = {0, }, \
	307	.fph = {{{{0}}}, } \
	308	}
	309
	310	#define start_thread(regs,new_ip,new_sp) do { \
1da177e4 LT	311	regs->cr_ipsr = ((regs->cr_ipsr \| (IA64_PSR_BITS_TO_SET \| IA64_PSR_CPL)) \
	312	& ~(IA64_PSR_BITS_TO_CLEAR \| IA64_PSR_RI \| IA64_PSR_IS)); \
	313	regs->cr_iip = new_ip; \
	314	regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
	315	regs->ar_rnat = 0; \
	316	regs->ar_bspstore = current->thread.rbs_bot; \
	317	regs->ar_fpsr = FPSR_DEFAULT; \
	318	regs->loadrs = 0; \
6c5d5238	319	regs->r8 = get_dumpable(current->mm); /* set "don't zap registers" flag */ \
1da177e4	320	regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
d049f74f	321	if (unlikely(get_dumpable(current->mm) != SUID_DUMP_USER)) { \
1da177e4 LT	322	/* \
	323	* Zap scratch regs to avoid leaking bits between processes with different \
	324	* uid/privileges. \
	325	*/ \
	326	regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \
	327	regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \
	328	} \
	329	} while (0)
	330
	331	/* Forward declarations, a strange C thing... */
	332	struct mm_struct;
	333	struct task_struct;
	334
	335	/*
	336	* Free all resources held by a thread. This is called after the
	337	* parent of DEAD_TASK has collected the exit status of the task via
	338	* wait().
	339	*/
	340	#define release_thread(dead_task)
	341
1da177e4 LT	342	/* Get wait channel for task P. */
	343	extern unsigned long get_wchan (struct task_struct *p);
	344
	345	/* Return instruction pointer of blocked task TSK. */
	346	#define KSTK_EIP(tsk) \
	347	({ \
6450578f	348	struct pt_regs *_regs = task_pt_regs(tsk); \
1da177e4 LT	349	_regs->cr_iip + ia64_psr(_regs)->ri; \
	350	})
	351
	352	/* Return stack pointer of blocked task TSK. */
	353	#define KSTK_ESP(tsk) ((tsk)->thread.ksp)
	354
	355	extern void ia64_getreg_unknown_kr (void);
	356	extern void ia64_setreg_unknown_kr (void);
	357
	358	#define ia64_get_kr(regnum) \
	359	({ \
	360	unsigned long r = 0; \
	361	\
	362	switch (regnum) { \
	363	case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \
	364	case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \
	365	case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \
	366	case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \
	367	case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \
	368	case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \
	369	case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \
	370	case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \
	371	default: ia64_getreg_unknown_kr(); break; \
	372	} \
	373	r; \
	374	})
	375
	376	#define ia64_set_kr(regnum, r) \
	377	({ \
	378	switch (regnum) { \
	379	case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \
	380	case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \
	381	case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \
	382	case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \
	383	case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \
	384	case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \
	385	case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \
	386	case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \
	387	default: ia64_setreg_unknown_kr(); break; \
	388	} \
	389	})
	390
	391	/*
	392	* The following three macros can't be inline functions because we don't have struct
	393	* task_struct at this point.
	394	*/
	395
05062d96 PC	396	/*
	397	* Return TRUE if task T owns the fph partition of the CPU we're running on.
	398	* Must be called from code that has preemption disabled.
	399	*/
1da177e4 LT	400	#define ia64_is_local_fpu_owner(t) \
	401	({ \
	402	struct task_struct *__ia64_islfo_task = (t); \
	403	(__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \
	404	&& __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \
	405	})
	406
05062d96 PC	407	/*
	408	* Mark task T as owning the fph partition of the CPU we're running on.
	409	* Must be called from code that has preemption disabled.
	410	*/
1da177e4 LT	411	#define ia64_set_local_fpu_owner(t) do { \
	412	struct task_struct *__ia64_slfo_task = (t); \
	413	__ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \
	414	ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \
	415	} while (0)
	416
	417	/* Mark the fph partition of task T as being invalid on all CPUs. */
	418	#define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1)
	419
	420	extern void __ia64_init_fpu (void);
	421	extern void __ia64_save_fpu (struct ia64_fpreg *fph);
	422	extern void __ia64_load_fpu (struct ia64_fpreg *fph);
	423	extern void ia64_save_debug_regs (unsigned long *save_area);
	424	extern void ia64_load_debug_regs (unsigned long *save_area);
	425
1da177e4 LT	426	#define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
	427	#define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
	428
	429	/* load fp 0.0 into fph */
	430	static inline void
	431	ia64_init_fpu (void) {
	432	ia64_fph_enable();
	433	__ia64_init_fpu();
	434	ia64_fph_disable();
	435	}
	436
	437	/* save f32-f127 at FPH */
	438	static inline void
	439	ia64_save_fpu (struct ia64_fpreg *fph) {
	440	ia64_fph_enable();
	441	__ia64_save_fpu(fph);
	442	ia64_fph_disable();
	443	}
	444
	445	/* load f32-f127 from FPH */
	446	static inline void
	447	ia64_load_fpu (struct ia64_fpreg *fph) {
	448	ia64_fph_enable();
	449	__ia64_load_fpu(fph);
	450	ia64_fph_disable();
	451	}
	452
	453	static inline __u64
	454	ia64_clear_ic (void)
	455	{
	456	__u64 psr;
	457	psr = ia64_getreg(_IA64_REG_PSR);
	458	ia64_stop();
	459	ia64_rsm(IA64_PSR_I \| IA64_PSR_IC);
	460	ia64_srlz_i();
	461	return psr;
	462	}
	463
	464	/*
	465	* Restore the psr.
	466	*/
	467	static inline void
	468	ia64_set_psr (__u64 psr)
	469	{
	470	ia64_stop();
	471	ia64_setreg(_IA64_REG_PSR_L, psr);
f00c2d36	472	ia64_srlz_i();
1da177e4 LT	473	}
	474
	475	/*
	476	* Insert a translation into an instruction and/or data translation
	477	* register.
	478	*/
	479	static inline void
	480	ia64_itr (__u64 target_mask, __u64 tr_num,
	481	__u64 vmaddr, __u64 pte,
	482	__u64 log_page_size)
	483	{
	484	ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
	485	ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
	486	ia64_stop();
	487	if (target_mask & 0x1)
	488	ia64_itri(tr_num, pte);
	489	if (target_mask & 0x2)
	490	ia64_itrd(tr_num, pte);
	491	}
	492
	493	/*
	494	* Insert a translation into the instruction and/or data translation
	495	* cache.
	496	*/
	497	static inline void
	498	ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
	499	__u64 log_page_size)
	500	{
	501	ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
	502	ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
	503	ia64_stop();
	504	/* as per EAS2.6, itc must be the last instruction in an instruction group */
	505	if (target_mask & 0x1)
	506	ia64_itci(pte);
	507	if (target_mask & 0x2)
	508	ia64_itcd(pte);
	509	}
	510
	511	/*
	512	* Purge a range of addresses from instruction and/or data translation
	513	* register(s).
	514	*/
	515	static inline void
	516	ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
	517	{
	518	if (target_mask & 0x1)
	519	ia64_ptri(vmaddr, (log_size << 2));
	520	if (target_mask & 0x2)
	521	ia64_ptrd(vmaddr, (log_size << 2));
	522	}
	523
	524	/* Set the interrupt vector address. The address must be suitably aligned (32KB). */
	525	static inline void
	526	ia64_set_iva (void *ivt_addr)
	527	{
	528	ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
	529	ia64_srlz_i();
	530	}
	531
	532	/* Set the page table address and control bits. */
	533	static inline void
	534	ia64_set_pta (__u64 pta)
	535	{
	536	/* Note: srlz.i implies srlz.d */
537	ia64_setreg(_IA64_REG_CR_PTA, pta);
538	ia64_srlz_i();
539	}
540
541	static inline void
542	ia64_eoi (void)
543	{
544	ia64_setreg(_IA64_REG_CR_EOI, 0);
545	ia64_srlz_d();
546	}
547
548	#define cpu_relax() ia64_hint(ia64_hint_pause)
549
a5878691 BH	550	static inline int
	551	ia64_get_irr(unsigned int vector)
	552	{
	553	unsigned int reg = vector / 64;
	554	unsigned int bit = vector % 64;
	555	u64 irr;
	556
	557	switch (reg) {
	558	case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
	559	case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
	560	case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
	561	case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
	562	}
	563
	564	return test_bit(bit, &irr);
	565	}
	566
1da177e4 LT	567	static inline void
	568	ia64_set_lrr0 (unsigned long val)
	569	{
	570	ia64_setreg(_IA64_REG_CR_LRR0, val);
	571	ia64_srlz_d();
	572	}
	573
	574	static inline void
	575	ia64_set_lrr1 (unsigned long val)
	576	{
	577	ia64_setreg(_IA64_REG_CR_LRR1, val);
	578	ia64_srlz_d();
	579	}
	580
	581
	582	/*
	583	* Given the address to which a spill occurred, return the unat bit
	584	* number that corresponds to this address.
	585	*/
	586	static inline __u64
	587	ia64_unat_pos (void *spill_addr)
	588	{
	589	return ((__u64) spill_addr >> 3) & 0x3f;
	590	}
	591
	592	/*
	593	* Set the NaT bit of an integer register which was spilled at address
	594	* SPILL_ADDR. UNAT is the mask to be updated.
	595	*/
	596	static inline void
	597	ia64_set_unat (__u64 unat, void spill_addr, unsigned long nat)
	598	{
	599	__u64 bit = ia64_unat_pos(spill_addr);
	600	__u64 mask = 1UL << bit;
	601
	602	unat = (unat & ~mask) \| (nat << bit);
	603	}
	604
1da177e4 LT	605	/*
	606	* Get the current instruction/program counter value.
	607	*/
	608	#define current_text_addr() \
	609	({ void _pc; _pc = (void )ia64_getreg(_IA64_REG_IP); _pc; })
	610
	611	static inline __u64
	612	ia64_get_ivr (void)
	613	{
	614	__u64 r;
	615	ia64_srlz_d();
	616	r = ia64_getreg(_IA64_REG_CR_IVR);
	617	ia64_srlz_d();
	618	return r;
	619	}
	620
	621	static inline void
	622	ia64_set_dbr (__u64 regnum, __u64 value)
	623	{
	624	__ia64_set_dbr(regnum, value);
	625	#ifdef CONFIG_ITANIUM
	626	ia64_srlz_d();
	627	#endif
	628	}
	629
	630	static inline __u64
	631	ia64_get_dbr (__u64 regnum)
	632	{
	633	__u64 retval;
	634
	635	retval = __ia64_get_dbr(regnum);
	636	#ifdef CONFIG_ITANIUM
	637	ia64_srlz_d();
	638	#endif
	639	return retval;
	640	}
	641
	642	static inline __u64
	643	ia64_rotr (__u64 w, __u64 n)
	644	{
	645	return (w >> n) \| (w << (64 - n));
	646	}
	647
	648	#define ia64_rotl(w,n) ia64_rotr((w), (64) - (n))
	649
	650	/*
	651	* Take a mapped kernel address and return the equivalent address
	652	* in the region 7 identity mapped virtual area.
	653	*/
	654	static inline void *
	655	ia64_imva (void *addr)
	656	{
	657	void *result;
	658	result = (void *) ia64_tpa(addr);
	659	return __va(result);
	660	}
	661
	662	#define ARCH_HAS_PREFETCH
	663	#define ARCH_HAS_PREFETCHW
	664	#define ARCH_HAS_SPINLOCK_PREFETCH
	665	#define PREFETCH_STRIDE L1_CACHE_BYTES
	666
	667	static inline void
	668	prefetch (const void *x)
669	{
670	ia64_lfetch(ia64_lfhint_none, x);
671	}
672
673	static inline void
674	prefetchw (const void *x)
675	{
676	ia64_lfetch_excl(ia64_lfhint_none, x);
677	}
678
679	#define spin_lock_prefetch(x) prefetchw(x)
680
681	extern unsigned long boot_option_idle_override;
d1896049 TR	682
	683	enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
	684	IDLE_NOMWAIT, IDLE_POLL};
1da177e4	685
c140d879 DH	686	void default_idle(void);
c140d879 DH	687
f9445a38	688	#define ia64_platform_is(x) (strcmp(x, ia64_platform_name) == 0)
c140d879	689
1da177e4 LT	690	#endif /* !__ASSEMBLY__ */
	691
	692	#endif /* _ASM_IA64_PROCESSOR_H */