[linux-2.6-block.git] / arch / i386 / pci / mmconfig.c

/*
 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
 * Copyright (C) 2004 Intel Corp.
 *
 * This code is released under the GNU General Public License version 2.
 */

/*
 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <asm/e820.h>
#include "pci.h"

/* aperture is up to 256MB but BIOS may reserve less */
#define MMCONFIG_APER_MIN	(2 * 1024*1024)
#define MMCONFIG_APER_MAX	(256 * 1024*1024)

/* Assume systems with more busses have correct MCFG */
#define MAX_CHECK_BUS 16

#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))

/* The base address of the last MMCONFIG device accessed */
static u32 mmcfg_last_accessed_device;
static int mmcfg_last_accessed_cpu;

static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32);

/*
 * Functions for accessing PCI configuration space with MMCONFIG accesses
 */
static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
{
	int cfg_num = -1;
	struct acpi_mcfg_allocation *cfg;

	if (seg == 0 && bus < MAX_CHECK_BUS &&
	    test_bit(PCI_SLOT(devfn) + 32*bus, fallback_slots))
		return 0;

	while (1) {
		++cfg_num;
		if (cfg_num >= pci_mmcfg_config_num) {
			break;
		}
		cfg = &pci_mmcfg_config[cfg_num];
		if (cfg->pci_segment != seg)
			continue;
		if ((cfg->start_bus_number <= bus) &&
		    (cfg->end_bus_number >= bus))
			return cfg->address;
	}

	/* Handle more broken MCFG tables on Asus etc.
	   They only contain a single entry for bus 0-0. Assume
 	   this applies to all busses. */
	cfg = &pci_mmcfg_config[0];
	if (pci_mmcfg_config_num == 1 &&
		cfg->pci_segment == 0 &&
		(cfg->start_bus_number | cfg->end_bus_number) == 0)
		return cfg->address;

	/* Fall back to type 0 */
	return 0;
}

/*
 * This is always called under pci_config_lock
 */
static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
{
	u32 dev_base = base | (bus << 20) | (devfn << 12);
	int cpu = smp_processor_id();
	if (dev_base != mmcfg_last_accessed_device ||
	    cpu != mmcfg_last_accessed_cpu) {
		mmcfg_last_accessed_device = dev_base;
		mmcfg_last_accessed_cpu = cpu;
		set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
	}
}

static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	unsigned long flags;
	u32 base;

	if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
		*value = -1;
		return -EINVAL;
	}

	base = get_base_addr(seg, bus, devfn);
	if (!base)
		return pci_conf1_read(seg,bus,devfn,reg,len,value);

	spin_lock_irqsave(&pci_config_lock, flags);

	pci_exp_set_dev_base(base, bus, devfn);

	switch (len) {
	case 1:
		*value = readb(mmcfg_virt_addr + reg);
		break;
	case 2:
		*value = readw(mmcfg_virt_addr + reg);
		break;
	case 4:
		*value = readl(mmcfg_virt_addr + reg);
		break;
	}

	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	unsigned long flags;
	u32 base;

	if ((bus > 255) || (devfn > 255) || (reg > 4095))
		return -EINVAL;

	base = get_base_addr(seg, bus, devfn);
	if (!base)
		return pci_conf1_write(seg,bus,devfn,reg,len,value);

	spin_lock_irqsave(&pci_config_lock, flags);

	pci_exp_set_dev_base(base, bus, devfn);

	switch (len) {
	case 1:
		writeb(value, mmcfg_virt_addr + reg);
		break;
	case 2:
		writew(value, mmcfg_virt_addr + reg);
		break;
	case 4:
		writel(value, mmcfg_virt_addr + reg);
		break;
	}

	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

static struct pci_raw_ops pci_mmcfg = {
	.read =		pci_mmcfg_read,
	.write =	pci_mmcfg_write,
};

/* K8 systems have some devices (typically in the builtin northbridge)
   that are only accessible using type1
   Normally this can be expressed in the MCFG by not listing them
   and assigning suitable _SEGs, but this isn't implemented in some BIOS.
   Instead try to discover all devices on bus 0 that are unreachable using MM
   and fallback for them. */
static __init void unreachable_devices(void)
{
	int i, k;
	unsigned long flags;

	for (k = 0; k < MAX_CHECK_BUS; k++) {
		for (i = 0; i < 32; i++) {
			u32 val1;
			u32 addr;

			pci_conf1_read(0, k, PCI_DEVFN(i, 0), 0, 4, &val1);
			if (val1 == 0xffffffff)
				continue;

			/* Locking probably not needed, but safer */
			spin_lock_irqsave(&pci_config_lock, flags);
			addr = get_base_addr(0, k, PCI_DEVFN(i, 0));
			if (addr != 0)
				pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0));
			if (addr == 0 ||
			    readl((u32 __iomem *)mmcfg_virt_addr) != val1) {
				set_bit(i + 32*k, fallback_slots);
				printk(KERN_NOTICE
			"PCI: No mmconfig possible on %x:%x\n", k, i);
			}
			spin_unlock_irqrestore(&pci_config_lock, flags);
		}
	}
}

void __init pci_mmcfg_init(int type)
{
	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
		return;

	acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	/* Only do this check when type 1 works. If it doesn't work
	   assume we run on a Mac and always use MCFG */
	if (type == 1 && !e820_all_mapped(pci_mmcfg_config[0].address,
			pci_mmcfg_config[0].address + MMCONFIG_APER_MIN,
			E820_RESERVED)) {
		printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %lx is not E820-reserved\n",
				(unsigned long)pci_mmcfg_config[0].address);
		printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
		return;
	}

	printk(KERN_INFO "PCI: Using MMCONFIG\n");
	raw_pci_ops = &pci_mmcfg;
	pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;

	unreachable_devices();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
	3	* Copyright (C) 2004 Intel Corp.
	4	*
	5	* This code is released under the GNU General Public License version 2.
	6	*/
	7
	8	/*
	9	* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
	10	*/
	11
	12	#include <linux/pci.h>
	13	#include <linux/init.h>
54549391	14	#include <linux/acpi.h>
946f2ee5	15	#include <asm/e820.h>
1da177e4 LT	16	#include "pci.h"
1da177e4 LT	17
ead2bfeb CE	18	/* aperture is up to 256MB but BIOS may reserve less */
	19	#define MMCONFIG_APER_MIN (2 * 1024*1024)
	20	#define MMCONFIG_APER_MAX (256 * 1024*1024)
946f2ee5	21
8c30b1a7 AK	22	/* Assume systems with more busses have correct MCFG */
	23	#define MAX_CHECK_BUS 16
	24
1da177e4 LT	25	#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
	26
	27	/* The base address of the last MMCONFIG device accessed */
	28	static u32 mmcfg_last_accessed_device;
8d1c4819	29	static int mmcfg_last_accessed_cpu;
1da177e4	30
8c30b1a7	31	static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32);
d6ece549	32
1da177e4 LT	33	/*
	34	* Functions for accessing PCI configuration space with MMCONFIG accesses
	35	*/
d6ece549	36	static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
d57e26ce GKH	37	{
d57e26ce GKH	38	int cfg_num = -1;
15a58ed1	39	struct acpi_mcfg_allocation *cfg;
d57e26ce	40
8c30b1a7 AK	41	if (seg == 0 && bus < MAX_CHECK_BUS &&
8c30b1a7 AK	42	test_bit(PCI_SLOT(devfn) + 32*bus, fallback_slots))
d6ece549 AK	43	return 0;
d6ece549 AK	44
d57e26ce GKH	45	while (1) {
	46	++cfg_num;
	47	if (cfg_num >= pci_mmcfg_config_num) {
3103039c	48	break;
d57e26ce GKH	49	}
d57e26ce GKH	50	cfg = &pci_mmcfg_config[cfg_num];
15a58ed1	51	if (cfg->pci_segment != seg)
d57e26ce GKH	52	continue;
	53	if ((cfg->start_bus_number <= bus) &&
	54	(cfg->end_bus_number >= bus))
15a58ed1	55	return cfg->address;
d57e26ce	56	}
3103039c AK	57
	58	/* Handle more broken MCFG tables on Asus etc.
	59	They only contain a single entry for bus 0-0. Assume
	60	this applies to all busses. */
	61	cfg = &pci_mmcfg_config[0];
	62	if (pci_mmcfg_config_num == 1 &&
15a58ed1	63	cfg->pci_segment == 0 &&
3103039c	64	(cfg->start_bus_number \| cfg->end_bus_number) == 0)
15a58ed1	65	return cfg->address;
3103039c AK	66
	67	/* Fall back to type 0 */
	68	return 0;
d57e26ce	69	}
1da177e4	70
be5b7a89 AM	71	/*
	72	* This is always called under pci_config_lock
	73	*/
	74	static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
1da177e4	75	{
928cf8c6	76	u32 dev_base = base \| (bus << 20) \| (devfn << 12);
8d1c4819 OH	77	int cpu = smp_processor_id();
	78	if (dev_base != mmcfg_last_accessed_device \|\|
	79	cpu != mmcfg_last_accessed_cpu) {
1da177e4	80	mmcfg_last_accessed_device = dev_base;
8d1c4819	81	mmcfg_last_accessed_cpu = cpu;
1da177e4 LT	82	set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
	83	}
	84	}
	85
	86	static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
	87	unsigned int devfn, int reg, int len, u32 *value)
	88	{
	89	unsigned long flags;
928cf8c6	90	u32 base;
1da177e4	91
ecc16ba9	92	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)) {
49c93e84	93	*value = -1;
1da177e4	94	return -EINVAL;
49c93e84	95	}
1da177e4	96
d6ece549	97	base = get_base_addr(seg, bus, devfn);
928cf8c6 AK	98	if (!base)
	99	return pci_conf1_read(seg,bus,devfn,reg,len,value);
	100
1da177e4 LT	101	spin_lock_irqsave(&pci_config_lock, flags);
1da177e4 LT	102
928cf8c6	103	pci_exp_set_dev_base(base, bus, devfn);
1da177e4 LT	104
	105	switch (len) {
	106	case 1:
	107	*value = readb(mmcfg_virt_addr + reg);
	108	break;
	109	case 2:
	110	*value = readw(mmcfg_virt_addr + reg);
	111	break;
	112	case 4:
	113	*value = readl(mmcfg_virt_addr + reg);
	114	break;
	115	}
	116
	117	spin_unlock_irqrestore(&pci_config_lock, flags);
	118
	119	return 0;
	120	}
	121
	122	static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
	123	unsigned int devfn, int reg, int len, u32 value)
	124	{
	125	unsigned long flags;
928cf8c6	126	u32 base;
1da177e4	127
15a58ed1	128	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095))
1da177e4 LT	129	return -EINVAL;
1da177e4 LT	130
d6ece549	131	base = get_base_addr(seg, bus, devfn);
928cf8c6 AK	132	if (!base)
	133	return pci_conf1_write(seg,bus,devfn,reg,len,value);
	134
1da177e4 LT	135	spin_lock_irqsave(&pci_config_lock, flags);
1da177e4 LT	136
928cf8c6	137	pci_exp_set_dev_base(base, bus, devfn);
1da177e4 LT	138
	139	switch (len) {
	140	case 1:
	141	writeb(value, mmcfg_virt_addr + reg);
	142	break;
	143	case 2:
	144	writew(value, mmcfg_virt_addr + reg);
	145	break;
	146	case 4:
	147	writel(value, mmcfg_virt_addr + reg);
	148	break;
	149	}
	150
	151	spin_unlock_irqrestore(&pci_config_lock, flags);
	152
	153	return 0;
	154	}
	155
	156	static struct pci_raw_ops pci_mmcfg = {
	157	.read = pci_mmcfg_read,
	158	.write = pci_mmcfg_write,
	159	};
	160
d6ece549 AK	161	/* K8 systems have some devices (typically in the builtin northbridge)
	162	that are only accessible using type1
	163	Normally this can be expressed in the MCFG by not listing them
	164	and assigning suitable _SEGs, but this isn't implemented in some BIOS.
	165	Instead try to discover all devices on bus 0 that are unreachable using MM
8c30b1a7	166	and fallback for them. */
d6ece549 AK	167	static __init void unreachable_devices(void)
d6ece549 AK	168	{
8c30b1a7	169	int i, k;
d6ece549 AK	170	unsigned long flags;
d6ece549 AK	171
8c30b1a7 AK	172	for (k = 0; k < MAX_CHECK_BUS; k++) {
	173	for (i = 0; i < 32; i++) {
	174	u32 val1;
	175	u32 addr;
	176
	177	pci_conf1_read(0, k, PCI_DEVFN(i, 0), 0, 4, &val1);
	178	if (val1 == 0xffffffff)
	179	continue;
	180
	181	/* Locking probably not needed, but safer */
	182	spin_lock_irqsave(&pci_config_lock, flags);
	183	addr = get_base_addr(0, k, PCI_DEVFN(i, 0));
	184	if (addr != 0)
	185	pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0));
	186	if (addr == 0 \|\|
	187	readl((u32 __iomem *)mmcfg_virt_addr) != val1) {
fd4dc27c	188	set_bit(i + 32*k, fallback_slots);
8c30b1a7 AK	189	printk(KERN_NOTICE
	190	"PCI: No mmconfig possible on %x:%x\n", k, i);
	191	}
	192	spin_unlock_irqrestore(&pci_config_lock, flags);
	193	}
d6ece549 AK	194	}
	195	}
	196
5e544d61	197	void __init pci_mmcfg_init(int type)
1da177e4	198	{
79e453d4	199	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
92c05fc1	200	return;
54549391	201
15a58ed1	202	acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
54549391 GKH	203	if ((pci_mmcfg_config_num == 0) \|\|
54549391 GKH	204	(pci_mmcfg_config == NULL) \|\|
15a58ed1	205	(pci_mmcfg_config[0].address == 0))
92c05fc1	206	return;
1da177e4	207
9abd7928 AK	208	/* Only do this check when type 1 works. If it doesn't work
9abd7928 AK	209	assume we run on a Mac and always use MCFG */
15a58ed1 AS	210	if (type == 1 && !e820_all_mapped(pci_mmcfg_config[0].address,
15a58ed1 AS	211	pci_mmcfg_config[0].address + MMCONFIG_APER_MIN,
79e453d4	212	E820_RESERVED)) {
15a58ed1 AS	213	printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %lx is not E820-reserved\n",
15a58ed1 AS	214	(unsigned long)pci_mmcfg_config[0].address);
79e453d4 LT	215	printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
	216	return;
	217	}
	218
1da177e4 LT	219	printk(KERN_INFO "PCI: Using MMCONFIG\n");
	220	raw_pci_ops = &pci_mmcfg;
	221	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
	222
d6ece549	223	unreachable_devices();
1da177e4	224	}