projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] x86: avoid wasting IRQs for PCI devices
[linux-2.6-block.git] / arch / i386 / pci / irq.c
CommitLineData
1da177e4
LT		 1/*
2 * Low-Level PCI Support for PC -- Routing of Interrupts
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
6
7#include <linux/config.h>
8#include <linux/types.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12#include <linux/slab.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/dmi.h>
16#include <asm/io.h>
17#include <asm/smp.h>
18#include <asm/io_apic.h>
19#include <asm/hw_irq.h>
20#include <linux/acpi.h>
21
22#include "pci.h"
23
24#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
25#define PIRQ_VERSION 0x0100
26
27static int broken_hp_bios_irq9;
28static int acer_tm360_irqrouting;
29
30static struct irq_routing_table *pirq_table;
31
32static int pirq_enable_irq(struct pci_dev *dev);
33
34/*
35 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
36 * Avoid using: 13, 14 and 15 (FP error and IDE).
37 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
38 */
39unsigned int pcibios_irq_mask = 0xfff8;
40
41static int pirq_penalty[16] = {
42 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
43 0, 0, 0, 0, 1000, 100000, 100000, 100000
44};
45
46struct irq_router {
47 char *name;
48 u16 vendor, device;
49 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
50 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
51};
52
53struct irq_router_handler {
54 u16 vendor;
55 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
56};
57
58int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
59
60/*
61 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
62 */
63
64static struct irq_routing_table * __init pirq_find_routing_table(void)
65{
66 u8 *addr;
67 struct irq_routing_table *rt;
68 int i;
69 u8 sum;
70
71 for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
72 rt = (struct irq_routing_table *) addr;
73 if (rt->signature != PIRQ_SIGNATURE ||
74 rt->version != PIRQ_VERSION ||
75 rt->size % 16 ||
76 rt->size < sizeof(struct irq_routing_table))
77 continue;
78 sum = 0;
79 for(i=0; i<rt->size; i++)
80 sum += addr[i];
81 if (!sum) {
82 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
83 return rt;
84 }
85 }
86 return NULL;
87}
88
89/*
90 * If we have a IRQ routing table, use it to search for peer host
91 * bridges. It's a gross hack, but since there are no other known
92 * ways how to get a list of buses, we have to go this way.
93 */
94
95static void __init pirq_peer_trick(void)
96{
97 struct irq_routing_table *rt = pirq_table;
98 u8 busmap[256];
99 int i;
100 struct irq_info *e;
101
102 memset(busmap, 0, sizeof(busmap));
103 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
104 e = &rt->slots[i];
105#ifdef DEBUG
106 {
107 int j;
108 DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
109 for(j=0; j<4; j++)
110 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
111 DBG("\n");
112 }
113#endif
114 busmap[e->bus] = 1;
115 }
116 for(i = 1; i < 256; i++) {
117 if (!busmap[i] || pci_find_bus(0, i))
118 continue;
119 if (pci_scan_bus(i, &pci_root_ops, NULL))
120 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
121 }
122 pcibios_last_bus = -1;
123}
124
125/*
126 * Code for querying and setting of IRQ routes on various interrupt routers.
127 */
128
129void eisa_set_level_irq(unsigned int irq)
130{
131 unsigned char mask = 1 << (irq & 7);
132 unsigned int port = 0x4d0 + (irq >> 3);
133 unsigned char val;
134 static u16 eisa_irq_mask;
135
136 if (irq >= 16 || (1 << irq) & eisa_irq_mask)
137 return;
138
139 eisa_irq_mask |= (1 << irq);
140 printk("PCI: setting IRQ %u as level-triggered\n", irq);
141 val = inb(port);
142 if (!(val & mask)) {
143 DBG(" -> edge");
144 outb(val | mask, port);
145 }
146}
147
148/*
149 * Common IRQ routing practice: nybbles in config space,
150 * offset by some magic constant.
151 */
152static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
153{
154 u8 x;
155 unsigned reg = offset + (nr >> 1);
156
157 pci_read_config_byte(router, reg, &x);
158 return (nr & 1) ? (x >> 4) : (x & 0xf);
159}
160
161static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
162{
163 u8 x;
164 unsigned reg = offset + (nr >> 1);
165
166 pci_read_config_byte(router, reg, &x);
167 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
168 pci_write_config_byte(router, reg, x);
169}
170
171/*
172 * ALI pirq entries are damn ugly, and completely undocumented.
173 * This has been figured out from pirq tables, and it's not a pretty
174 * picture.
175 */
176static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
177{
178 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
179
180 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
181}
182
183static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
184{
185 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
186 unsigned int val = irqmap[irq];
187
188 if (val) {
189 write_config_nybble(router, 0x48, pirq-1, val);
190 return 1;
191 }
192 return 0;
193}
194
195/*
196 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
197 * just a pointer to the config space.
198 */
199static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
200{
201 u8 x;
202
203 pci_read_config_byte(router, pirq, &x);
204 return (x < 16) ? x : 0;
205}
206
207static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
208{
209 pci_write_config_byte(router, pirq, irq);
210 return 1;
211}
212
213/*
214 * The VIA pirq rules are nibble-based, like ALI,
215 * but without the ugly irq number munging.
216 * However, PIRQD is in the upper instead of lower 4 bits.
217 */
218static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
219{
220 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
221}
222
223static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
224{
225 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
226 return 1;
227}
228
229/*
230 * ITE 8330G pirq rules are nibble-based
231 * FIXME: pirqmap may be { 1, 0, 3, 2 },
232 * 2+3 are both mapped to irq 9 on my system
233 */
234static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
235{
236 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
237 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
238}
239
240static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
241{
242 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
243 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
244 return 1;
245}
246
247/*
248 * OPTI: high four bits are nibble pointer..
249 * I wonder what the low bits do?
250 */
251static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
252{
253 return read_config_nybble(router, 0xb8, pirq >> 4);
254}
255
256static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
257{
258 write_config_nybble(router, 0xb8, pirq >> 4, irq);
259 return 1;
260}
261
262/*
263 * Cyrix: nibble offset 0x5C
264 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
265 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
266 */
267static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
268{
269 return read_config_nybble(router, 0x5C, (pirq-1)^1);
270}
271
272static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
273{
274 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
275 return 1;
276}
277
278/*
279 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
280 * We have to deal with the following issues here:
281 * - vendors have different ideas about the meaning of link values
282 * - some onboard devices (integrated in the chipset) have special
283 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
284 * - different revision of the router have a different layout for
285 * the routing registers, particularly for the onchip devices
286 *
287 * For all routing registers the common thing is we have one byte
288 * per routeable link which is defined as:
289 * bit 7 IRQ mapping enabled (0) or disabled (1)
290 * bits [6:4] reserved (sometimes used for onchip devices)
291 * bits [3:0] IRQ to map to
292 * allowed: 3-7, 9-12, 14-15
293 * reserved: 0, 1, 2, 8, 13
294 *
295 * The config-space registers located at 0x41/0x42/0x43/0x44 are
296 * always used to route the normal PCI INT A/B/C/D respectively.
297 * Apparently there are systems implementing PCI routing table using
298 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
299 * We try our best to handle both link mappings.
300 *
301 * Currently (2003-05-21) it appears most SiS chipsets follow the
302 * definition of routing registers from the SiS-5595 southbridge.
303 * According to the SiS 5595 datasheets the revision id's of the
304 * router (ISA-bridge) should be 0x01 or 0xb0.
305 *
306 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
307 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
308 * They seem to work with the current routing code. However there is
309 * some concern because of the two USB-OHCI HCs (original SiS 5595
310 * had only one). YMMV.
311 *
312 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
313 *
314 * 0x61: IDEIRQ:
315 * bits [6:5] must be written 01
316 * bit 4 channel-select primary (0), secondary (1)
317 *
318 * 0x62: USBIRQ:
319 * bit 6 OHCI function disabled (0), enabled (1)
320 *
321 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
322 *
323 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
324 *
325 * We support USBIRQ (in addition to INTA-INTD) and keep the
326 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
327 *
328 * Currently the only reported exception is the new SiS 65x chipset
329 * which includes the SiS 69x southbridge. Here we have the 85C503
330 * router revision 0x04 and there are changes in the register layout
331 * mostly related to the different USB HCs with USB 2.0 support.
332 *
333 * Onchip routing for router rev-id 0x04 (try-and-error observation)
334 *
335 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
336 * bit 6-4 are probably unused, not like 5595
337 */
338
339#define PIRQ_SIS_IRQ_MASK 0x0f
340#define PIRQ_SIS_IRQ_DISABLE 0x80
341#define PIRQ_SIS_USB_ENABLE 0x40
342
343static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
344{
345 u8 x;
346 int reg;
347
348 reg = pirq;
349 if (reg >= 0x01 && reg <= 0x04)
350 reg += 0x40;
351 pci_read_config_byte(router, reg, &x);
352 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
353}
354
355static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
356{
357 u8 x;
358 int reg;
359
360 reg = pirq;
361 if (reg >= 0x01 && reg <= 0x04)
362 reg += 0x40;
363 pci_read_config_byte(router, reg, &x);
364 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
365 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
366 pci_write_config_byte(router, reg, x);
367 return 1;
368}
369
370
371/*
372 * VLSI: nibble offset 0x74 - educated guess due to routing table and
373 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
374 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
375 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
376 * for the busbridge to the docking station.
377 */
378
379static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
380{
381 if (pirq > 8) {
382 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
383 return 0;
384 }
385 return read_config_nybble(router, 0x74, pirq-1);
386}
387
388static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
389{
390 if (pirq > 8) {
391 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
392 return 0;
393 }
394 write_config_nybble(router, 0x74, pirq-1, irq);
395 return 1;
396}
397
398/*
399 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
400 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
401 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
402 * register is a straight binary coding of desired PIC IRQ (low nibble).
403 *
404 * The 'link' value in the PIRQ table is already in the correct format
405 * for the Index register. There are some special index values:
406 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
407 * and 0x03 for SMBus.
408 */
409static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
410{
411 outb_p(pirq, 0xc00);
412 return inb(0xc01) & 0xf;
413}
414
415static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
416{
417 outb_p(pirq, 0xc00);
418 outb_p(irq, 0xc01);
419 return 1;
420}
421
422/* Support for AMD756 PCI IRQ Routing
423 * Jhon H. Caicedo <jhcaiced@osso.org.co>
424 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
425 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
426 * The AMD756 pirq rules are nibble-based
427 * offset 0x56 0-3 PIRQA 4-7 PIRQB
428 * offset 0x57 0-3 PIRQC 4-7 PIRQD
429 */
430static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
431{
432 u8 irq;
433 irq = 0;
434 if (pirq <= 4)
435 {
436 irq = read_config_nybble(router, 0x56, pirq - 1);
437 }
438 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
439 dev->vendor, dev->device, pirq, irq);
440 return irq;
441}
442
443static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
444{
445 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
446 dev->vendor, dev->device, pirq, irq);
447 if (pirq <= 4)
448 {
449 write_config_nybble(router, 0x56, pirq - 1, irq);
450 }
451 return 1;
452}
453
454#ifdef CONFIG_PCI_BIOS
455
456static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
457{
458 struct pci_dev *bridge;
459 int pin = pci_get_interrupt_pin(dev, &bridge);
460 return pcibios_set_irq_routing(bridge, pin, irq);
461}
462
463#endif
464
465static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
466{
467 static struct pci_device_id pirq_440gx[] = {
468 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
469 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
470 { },
471 };
472
473 /* 440GX has a proprietary PIRQ router -- don't use it */
474 if (pci_dev_present(pirq_440gx))
475 return 0;
476
477 switch(device)
478 {
479 case PCI_DEVICE_ID_INTEL_82371FB_0:
480 case PCI_DEVICE_ID_INTEL_82371SB_0:
481 case PCI_DEVICE_ID_INTEL_82371AB_0:
482 case PCI_DEVICE_ID_INTEL_82371MX:
483 case PCI_DEVICE_ID_INTEL_82443MX_0:
484 case PCI_DEVICE_ID_INTEL_82801AA_0:
485 case PCI_DEVICE_ID_INTEL_82801AB_0:
486 case PCI_DEVICE_ID_INTEL_82801BA_0:
487 case PCI_DEVICE_ID_INTEL_82801BA_10:
488 case PCI_DEVICE_ID_INTEL_82801CA_0:
489 case PCI_DEVICE_ID_INTEL_82801CA_12:
490 case PCI_DEVICE_ID_INTEL_82801DB_0:
491 case PCI_DEVICE_ID_INTEL_82801E_0:
492 case PCI_DEVICE_ID_INTEL_82801EB_0:
493 case PCI_DEVICE_ID_INTEL_ESB_1:
494 case PCI_DEVICE_ID_INTEL_ICH6_0:
495 case PCI_DEVICE_ID_INTEL_ICH6_1:
496 case PCI_DEVICE_ID_INTEL_ICH7_0:
497 case PCI_DEVICE_ID_INTEL_ICH7_1:
4d24a439
JG		 498 case PCI_DEVICE_ID_INTEL_ICH7_30:
499 case PCI_DEVICE_ID_INTEL_ICH7_31:
e285f809 500 case PCI_DEVICE_ID_INTEL_ESB2_0:
1da177e4
LT		 501 r->name = "PIIX/ICH";
502 r->get = pirq_piix_get;
503 r->set = pirq_piix_set;
504 return 1;
505 }
506 return 0;
507}
508
509static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
510{
511 /* FIXME: We should move some of the quirk fixup stuff here */
512 switch(device)
513 {
514 case PCI_DEVICE_ID_VIA_82C586_0:
515 case PCI_DEVICE_ID_VIA_82C596:
516 case PCI_DEVICE_ID_VIA_82C686:
517 case PCI_DEVICE_ID_VIA_8231:
518 /* FIXME: add new ones for 8233/5 */
519 r->name = "VIA";
520 r->get = pirq_via_get;
521 r->set = pirq_via_set;
522 return 1;
523 }
524 return 0;
525}
526
527static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
528{
529 switch(device)
530 {
531 case PCI_DEVICE_ID_VLSI_82C534:
532 r->name = "VLSI 82C534";
533 r->get = pirq_vlsi_get;
534 r->set = pirq_vlsi_set;
535 return 1;
536 }
537 return 0;
538}
539
540
541static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
542{
543 switch(device)
544 {
545 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
546 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
547 r->name = "ServerWorks";
548 r->get = pirq_serverworks_get;
549 r->set = pirq_serverworks_set;
550 return 1;
551 }
552 return 0;
553}
554
555static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
556{
557 if (device != PCI_DEVICE_ID_SI_503)
558 return 0;
559
560 r->name = "SIS";
561 r->get = pirq_sis_get;
562 r->set = pirq_sis_set;
563 return 1;
564}
565
566static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
567{
568 switch(device)
569 {
570 case PCI_DEVICE_ID_CYRIX_5520:
571 r->name = "NatSemi";
572 r->get = pirq_cyrix_get;
573 r->set = pirq_cyrix_set;
574 return 1;
575 }
576 return 0;
577}
578
579static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
580{
581 switch(device)
582 {
583 case PCI_DEVICE_ID_OPTI_82C700:
584 r->name = "OPTI";
585 r->get = pirq_opti_get;
586 r->set = pirq_opti_set;
587 return 1;
588 }
589 return 0;
590}
591
592static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
593{
594 switch(device)
595 {
596 case PCI_DEVICE_ID_ITE_IT8330G_0:
597 r->name = "ITE";
598 r->get = pirq_ite_get;
599 r->set = pirq_ite_set;
600 return 1;
601 }
602 return 0;
603}
604
605static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
606{
607 switch(device)
608 {
609 case PCI_DEVICE_ID_AL_M1533:
610 case PCI_DEVICE_ID_AL_M1563:
611 printk("PCI: Using ALI IRQ Router\n");
612 r->name = "ALI";
613 r->get = pirq_ali_get;
614 r->set = pirq_ali_set;
615 return 1;
616 }
617 return 0;
618}
619
620static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
621{
622 switch(device)
623 {
624 case PCI_DEVICE_ID_AMD_VIPER_740B:
625 r->name = "AMD756";
626 break;
627 case PCI_DEVICE_ID_AMD_VIPER_7413:
628 r->name = "AMD766";
629 break;
630 case PCI_DEVICE_ID_AMD_VIPER_7443:
631 r->name = "AMD768";
632 break;
633 default:
634 return 0;
635 }
636 r->get = pirq_amd756_get;
637 r->set = pirq_amd756_set;
638 return 1;
639}
640
641static __initdata struct irq_router_handler pirq_routers[] = {
642 { PCI_VENDOR_ID_INTEL, intel_router_probe },
643 { PCI_VENDOR_ID_AL, ali_router_probe },
644 { PCI_VENDOR_ID_ITE, ite_router_probe },
645 { PCI_VENDOR_ID_VIA, via_router_probe },
646 { PCI_VENDOR_ID_OPTI, opti_router_probe },
647 { PCI_VENDOR_ID_SI, sis_router_probe },
648 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
649 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
650 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
651 { PCI_VENDOR_ID_AMD, amd_router_probe },
652 /* Someone with docs needs to add the ATI Radeon IGP */
653 { 0, NULL }
654};
655static struct irq_router pirq_router;
656static struct pci_dev *pirq_router_dev;
657
658
659/*
660 * FIXME: should we have an option to say "generic for
661 * chipset" ?
662 */
663
664static void __init pirq_find_router(struct irq_router *r)
665{
666 struct irq_routing_table *rt = pirq_table;
667 struct irq_router_handler *h;
668
669#ifdef CONFIG_PCI_BIOS
670 if (!rt->signature) {
671 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
672 r->set = pirq_bios_set;
673 r->name = "BIOS";
674 return;
675 }
676#endif
677
678 /* Default unless a driver reloads it */
679 r->name = "default";
680 r->get = NULL;
681 r->set = NULL;
682
683 DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
684 rt->rtr_vendor, rt->rtr_device);
685
686 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
687 if (!pirq_router_dev) {
688 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
689 return;
690 }
691
692 for( h = pirq_routers; h->vendor; h++) {
693 /* First look for a router match */
694 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
695 break;
696 /* Fall back to a device match */
697 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
698 break;
699 }
700 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
701 pirq_router.name,
702 pirq_router_dev->vendor,
703 pirq_router_dev->device,
704 pci_name(pirq_router_dev));
705}
706
707static struct irq_info *pirq_get_info(struct pci_dev *dev)
708{
709 struct irq_routing_table *rt = pirq_table;
710 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
711 struct irq_info *info;
712
713 for (info = rt->slots; entries--; info++)
714 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
715 return info;
716 return NULL;
717}
718
719static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
720{
721 u8 pin;
722 struct irq_info *info;
723 int i, pirq, newirq;
724 int irq = 0;
725 u32 mask;
726 struct irq_router *r = &pirq_router;
727 struct pci_dev *dev2 = NULL;
728 char *msg = NULL;
729
730 /* Find IRQ pin */
731 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
732 if (!pin) {
733 DBG(" -> no interrupt pin\n");
734 return 0;
735 }
736 pin = pin - 1;
737
738 /* Find IRQ routing entry */
739
740 if (!pirq_table)
741 return 0;
742
743 DBG("IRQ for %s[%c]", pci_name(dev), 'A' + pin);
744 info = pirq_get_info(dev);
745 if (!info) {
746 DBG(" -> not found in routing table\n");
747 return 0;
748 }
749 pirq = info->irq[pin].link;
750 mask = info->irq[pin].bitmap;
751 if (!pirq) {
752 DBG(" -> not routed\n");
753 return 0;
754 }
755 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
756 mask &= pcibios_irq_mask;
757
758 /* Work around broken HP Pavilion Notebooks which assign USB to
759 IRQ 9 even though it is actually wired to IRQ 11 */
760
761 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
762 dev->irq = 11;
763 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
764 r->set(pirq_router_dev, dev, pirq, 11);
765 }
766
767 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
768 if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
769 pirq = 0x68;
770 mask = 0x400;
771 dev->irq = r->get(pirq_router_dev, dev, pirq);
772 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
773 }
774
775 /*
776 * Find the best IRQ to assign: use the one
777 * reported by the device if possible.
778 */
779 newirq = dev->irq;
780 if (!((1 << newirq) & mask)) {
781 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
782 else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, pci_name(dev));
783 }
784 if (!newirq && assign) {
785 for (i = 0; i < 16; i++) {
786 if (!(mask & (1 << i)))
787 continue;
788 if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, SA_SHIRQ))
789 newirq = i;
790 }
791 }
792 DBG(" -> newirq=%d", newirq);
793
794 /* Check if it is hardcoded */
795 if ((pirq & 0xf0) == 0xf0) {
796 irq = pirq & 0xf;
797 DBG(" -> hardcoded IRQ %d\n", irq);
798 msg = "Hardcoded";
799 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
800 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
801 DBG(" -> got IRQ %d\n", irq);
802 msg = "Found";
803 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
804 DBG(" -> assigning IRQ %d", newirq);
805 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
806 eisa_set_level_irq(newirq);
807 DBG(" ... OK\n");
808 msg = "Assigned";
809 irq = newirq;
810 }
811 }
812
813 if (!irq) {
814 DBG(" ... failed\n");
815 if (newirq && mask == (1 << newirq)) {
816 msg = "Guessed";
817 irq = newirq;
818 } else
819 return 0;
820 }
821 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
822
823 /* Update IRQ for all devices with the same pirq value */
824 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
825 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
826 if (!pin)
827 continue;
828 pin--;
829 info = pirq_get_info(dev2);
830 if (!info)
831 continue;
832 if (info->irq[pin].link == pirq) {
833 /* We refuse to override the dev->irq information. Give a warning! */
834 if ( dev2->irq && dev2->irq != irq && \
835 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
836 ((1 << dev2->irq) & mask)) ) {
837#ifndef CONFIG_PCI_MSI
838 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
839 pci_name(dev2), dev2->irq, irq);
840#endif
841 continue;
842 }
843 dev2->irq = irq;
844 pirq_penalty[irq]++;
845 if (dev != dev2)
846 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
847 }
848 }
849 return 1;
850}
851
852static void __init pcibios_fixup_irqs(void)
853{
854 struct pci_dev *dev = NULL;
855 u8 pin;
856
857 DBG("PCI: IRQ fixup\n");
858 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
859 /*
860 * If the BIOS has set an out of range IRQ number, just ignore it.
861 * Also keep track of which IRQ's are already in use.
862 */
863 if (dev->irq >= 16) {
864 DBG("%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
865 dev->irq = 0;
866 }
867 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
868 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
869 pirq_penalty[dev->irq] = 0;
870 pirq_penalty[dev->irq]++;
871 }
872
873 dev = NULL;
874 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
875 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
876#ifdef CONFIG_X86_IO_APIC
877 /*
878 * Recalculate IRQ numbers if we use the I/O APIC.
879 */
880 if (io_apic_assign_pci_irqs)
881 {
882 int irq;
883
884 if (pin) {
885 pin--; /* interrupt pins are numbered starting from 1 */
886 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
887 /*
888 * Busses behind bridges are typically not listed in the MP-table.
889 * In this case we have to look up the IRQ based on the parent bus,
890 * parent slot, and pin number. The SMP code detects such bridged
891 * busses itself so we should get into this branch reliably.
892 */
893 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
894 struct pci_dev * bridge = dev->bus->self;
895
896 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
897 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
898 PCI_SLOT(bridge->devfn), pin);
899 if (irq >= 0)
900 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
901 pci_name(bridge), 'A' + pin, irq);
902 }
903 if (irq >= 0) {
904 if (use_pci_vector() &&
905 !platform_legacy_irq(irq))
906 irq = IO_APIC_VECTOR(irq);
907
908 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
909 pci_name(dev), 'A' + pin, irq);
910 dev->irq = irq;
911 }
912 }
913 }
914#endif
915 /*
916 * Still no IRQ? Try to lookup one...
917 */
918 if (pin && !dev->irq)
919 pcibios_lookup_irq(dev, 0);
920 }
921}
922
923/*
924 * Work around broken HP Pavilion Notebooks which assign USB to
925 * IRQ 9 even though it is actually wired to IRQ 11
926 */
927static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d)
928{
929 if (!broken_hp_bios_irq9) {
930 broken_hp_bios_irq9 = 1;
931 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
932 }
933 return 0;
934}
935
936/*
937 * Work around broken Acer TravelMate 360 Notebooks which assign
938 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
939 */
940static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d)
941{
942 if (!acer_tm360_irqrouting) {
943 acer_tm360_irqrouting = 1;
944 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
945 }
946 return 0;
947}
948
949static struct dmi_system_id __initdata pciirq_dmi_table[] = {
950 {
951 .callback = fix_broken_hp_bios_irq9,
952 .ident = "HP Pavilion N5400 Series Laptop",
953 .matches = {
954 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
955 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
956 DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"),
957 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
958 },
959 },
960 {
961 .callback = fix_acer_tm360_irqrouting,
962 .ident = "Acer TravelMate 36x Laptop",
963 .matches = {
964 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
965 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
966 },
967 },
968 { }
969};
970
971static int __init pcibios_irq_init(void)
972{
973 DBG("PCI: IRQ init\n");
974
975 if (pcibios_enable_irq || raw_pci_ops == NULL)
976 return 0;
977
978 dmi_check_system(pciirq_dmi_table);
979
980 pirq_table = pirq_find_routing_table();
981
982#ifdef CONFIG_PCI_BIOS
983 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
984 pirq_table = pcibios_get_irq_routing_table();
985#endif
986 if (pirq_table) {
987 pirq_peer_trick();
988 pirq_find_router(&pirq_router);
989 if (pirq_table->exclusive_irqs) {
990 int i;
991 for (i=0; i<16; i++)
992 if (!(pirq_table->exclusive_irqs & (1 << i)))
993 pirq_penalty[i] += 100;
994 }
995 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
996 if (io_apic_assign_pci_irqs)
997 pirq_table = NULL;
998 }
999
1000 pcibios_enable_irq = pirq_enable_irq;
1001
1002 pcibios_fixup_irqs();
1003 return 0;
1004}
1005
1006subsys_initcall(pcibios_irq_init);
1007
1008
1009static void pirq_penalize_isa_irq(int irq)
1010{
1011 /*
1012 * If any ISAPnP device reports an IRQ in its list of possible
1013 * IRQ's, we try to avoid assigning it to PCI devices.
1014 */
1015 if (irq < 16)
1016 pirq_penalty[irq] += 100;
1017}
1018
1019void pcibios_penalize_isa_irq(int irq)
1020{
1021#ifdef CONFIG_ACPI_PCI
1022 if (!acpi_noirq)
1023 acpi_penalize_isa_irq(irq);
1024 else
1025#endif
1026 pirq_penalize_isa_irq(irq);
1027}
1028
1029static int pirq_enable_irq(struct pci_dev *dev)
1030{
1031 u8 pin;
1da177e4
LT		 1032 struct pci_dev *temp_dev;
1033
1034 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1035 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1036 char *msg = "";
1037
1038 pin--; /* interrupt pins are numbered starting from 1 */
1039
1040 if (io_apic_assign_pci_irqs) {
1041 int irq;
1042
1043 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1044 /*
1045 * Busses behind bridges are typically not listed in the MP-table.
1046 * In this case we have to look up the IRQ based on the parent bus,
1047 * parent slot, and pin number. The SMP code detects such bridged
1048 * busses itself so we should get into this branch reliably.
1049 */
1050 temp_dev = dev;
1051 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1052 struct pci_dev * bridge = dev->bus->self;
1053
1054 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1055 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1056 PCI_SLOT(bridge->devfn), pin);
1057 if (irq >= 0)
1058 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
1059 pci_name(bridge), 'A' + pin, irq);
1060 dev = bridge;
1061 }
1062 dev = temp_dev;
1063 if (irq >= 0) {
1064#ifdef CONFIG_PCI_MSI
1065 if (!platform_legacy_irq(irq))
1066 irq = IO_APIC_VECTOR(irq);
1067#endif
1068 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
1069 pci_name(dev), 'A' + pin, irq);
1070 dev->irq = irq;
1071 return 0;
1072 } else
1073 msg = " Probably buggy MP table.";
1074 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1075 msg = "";
1076 else
1077 msg = " Please try using pci=biosirq.";
1078
1079 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1080 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1081 return 0;
1082
1083 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1084 'A' + pin, pci_name(dev), msg);
1085 }
1da177e4
LT		 1086 return 0;
1087}
1088
1089int pci_vector_resources(int last, int nr_released)
1090{
1091 int count = nr_released;
1092
1093 int next = last;
1094 int offset = (last % 8);
1095
1096 while (next < FIRST_SYSTEM_VECTOR) {
1097 next += 8;
1098#ifdef CONFIG_X86_64
1099 if (next == IA32_SYSCALL_VECTOR)
1100 continue;
1101#else
1102 if (next == SYSCALL_VECTOR)
1103 continue;
1104#endif
1105 count++;
1106 if (next >= FIRST_SYSTEM_VECTOR) {
1107 if (offset%8) {
1108 next = FIRST_DEVICE_VECTOR + offset;
1109 offset++;
1110 continue;
1111 }
1112 count--;
1113 }
1114 }
1115
1116 return count;
1117}
Linux 6.x block layer and io_uring tree(s)