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Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6-block.git] / arch / i386 / pci / irq.c
CommitLineData
1da177e4
LT		 1/*
2 * Low-Level PCI Support for PC -- Routing of Interrupts
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
6
7#include <linux/config.h>
8#include <linux/types.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12#include <linux/slab.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/dmi.h>
16#include <asm/io.h>
17#include <asm/smp.h>
18#include <asm/io_apic.h>
19#include <asm/hw_irq.h>
20#include <linux/acpi.h>
21
22#include "pci.h"
23
24#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
25#define PIRQ_VERSION 0x0100
26
27static int broken_hp_bios_irq9;
28static int acer_tm360_irqrouting;
29
30static struct irq_routing_table *pirq_table;
31
32static int pirq_enable_irq(struct pci_dev *dev);
33
34/*
35 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
36 * Avoid using: 13, 14 and 15 (FP error and IDE).
37 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
38 */
39unsigned int pcibios_irq_mask = 0xfff8;
40
41static int pirq_penalty[16] = {
42 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
43 0, 0, 0, 0, 1000, 100000, 100000, 100000
44};
45
46struct irq_router {
47 char *name;
48 u16 vendor, device;
49 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
50 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
51};
52
53struct irq_router_handler {
54 u16 vendor;
55 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
56};
57
58int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
59
60/*
61 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
62 */
63
64static struct irq_routing_table * __init pirq_find_routing_table(void)
65{
66 u8 *addr;
67 struct irq_routing_table *rt;
68 int i;
69 u8 sum;
70
71 for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
72 rt = (struct irq_routing_table *) addr;
73 if (rt->signature != PIRQ_SIGNATURE ||
74 rt->version != PIRQ_VERSION ||
75 rt->size % 16 ||
76 rt->size < sizeof(struct irq_routing_table))
77 continue;
78 sum = 0;
79 for(i=0; i<rt->size; i++)
80 sum += addr[i];
81 if (!sum) {
82 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
83 return rt;
84 }
85 }
86 return NULL;
87}
88
89/*
90 * If we have a IRQ routing table, use it to search for peer host
91 * bridges. It's a gross hack, but since there are no other known
92 * ways how to get a list of buses, we have to go this way.
93 */
94
95static void __init pirq_peer_trick(void)
96{
97 struct irq_routing_table *rt = pirq_table;
98 u8 busmap[256];
99 int i;
100 struct irq_info *e;
101
102 memset(busmap, 0, sizeof(busmap));
103 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
104 e = &rt->slots[i];
105#ifdef DEBUG
106 {
107 int j;
108 DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
109 for(j=0; j<4; j++)
110 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
111 DBG("\n");
112 }
113#endif
114 busmap[e->bus] = 1;
115 }
116 for(i = 1; i < 256; i++) {
117 if (!busmap[i] || pci_find_bus(0, i))
118 continue;
119 if (pci_scan_bus(i, &pci_root_ops, NULL))
120 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
121 }
122 pcibios_last_bus = -1;
123}
124
125/*
126 * Code for querying and setting of IRQ routes on various interrupt routers.
127 */
128
129void eisa_set_level_irq(unsigned int irq)
130{
131 unsigned char mask = 1 << (irq & 7);
132 unsigned int port = 0x4d0 + (irq >> 3);
133 unsigned char val;
134 static u16 eisa_irq_mask;
135
136 if (irq >= 16 || (1 << irq) & eisa_irq_mask)
137 return;
138
139 eisa_irq_mask |= (1 << irq);
140 printk("PCI: setting IRQ %u as level-triggered\n", irq);
141 val = inb(port);
142 if (!(val & mask)) {
143 DBG(" -> edge");
144 outb(val | mask, port);
145 }
146}
147
148/*
149 * Common IRQ routing practice: nybbles in config space,
150 * offset by some magic constant.
151 */
152static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
153{
154 u8 x;
155 unsigned reg = offset + (nr >> 1);
156
157 pci_read_config_byte(router, reg, &x);
158 return (nr & 1) ? (x >> 4) : (x & 0xf);
159}
160
161static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
162{
163 u8 x;
164 unsigned reg = offset + (nr >> 1);
165
166 pci_read_config_byte(router, reg, &x);
167 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
168 pci_write_config_byte(router, reg, x);
169}
170
171/*
172 * ALI pirq entries are damn ugly, and completely undocumented.
173 * This has been figured out from pirq tables, and it's not a pretty
174 * picture.
175 */
176static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
177{
178 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
179
180 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
181}
182
183static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
184{
185 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
186 unsigned int val = irqmap[irq];
187
188 if (val) {
189 write_config_nybble(router, 0x48, pirq-1, val);
190 return 1;
191 }
192 return 0;
193}
194
195/*
196 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
197 * just a pointer to the config space.
198 */
199static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
200{
201 u8 x;
202
203 pci_read_config_byte(router, pirq, &x);
204 return (x < 16) ? x : 0;
205}
206
207static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
208{
209 pci_write_config_byte(router, pirq, irq);
210 return 1;
211}
212
213/*
214 * The VIA pirq rules are nibble-based, like ALI,
215 * but without the ugly irq number munging.
216 * However, PIRQD is in the upper instead of lower 4 bits.
217 */
218static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
219{
220 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
221}
222
223static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
224{
225 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
226 return 1;
227}
228
80bb82af
AG		 229/*
230 * The VIA pirq rules are nibble-based, like ALI,
231 * but without the ugly irq number munging.
232 * However, for 82C586, nibble map is different .
233 */
234static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
235{
236 static unsigned int pirqmap[4] = { 3, 2, 5, 1 };
237 return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
238}
239
240static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
241{
242 static unsigned int pirqmap[4] = { 3, 2, 5, 1 };
243 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
244 return 1;
245}
246
1da177e4
LT		 247/*
248 * ITE 8330G pirq rules are nibble-based
249 * FIXME: pirqmap may be { 1, 0, 3, 2 },
250 * 2+3 are both mapped to irq 9 on my system
251 */
252static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
253{
254 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
255 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
256}
257
258static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
259{
260 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
261 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
262 return 1;
263}
264
265/*
266 * OPTI: high four bits are nibble pointer..
267 * I wonder what the low bits do?
268 */
269static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
270{
271 return read_config_nybble(router, 0xb8, pirq >> 4);
272}
273
274static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
275{
276 write_config_nybble(router, 0xb8, pirq >> 4, irq);
277 return 1;
278}
279
280/*
281 * Cyrix: nibble offset 0x5C
282 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
283 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
284 */
285static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
286{
287 return read_config_nybble(router, 0x5C, (pirq-1)^1);
288}
289
290static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
291{
292 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
293 return 1;
294}
295
296/*
297 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
298 * We have to deal with the following issues here:
299 * - vendors have different ideas about the meaning of link values
300 * - some onboard devices (integrated in the chipset) have special
301 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
302 * - different revision of the router have a different layout for
303 * the routing registers, particularly for the onchip devices
304 *
305 * For all routing registers the common thing is we have one byte
306 * per routeable link which is defined as:
307 * bit 7 IRQ mapping enabled (0) or disabled (1)
308 * bits [6:4] reserved (sometimes used for onchip devices)
309 * bits [3:0] IRQ to map to
310 * allowed: 3-7, 9-12, 14-15
311 * reserved: 0, 1, 2, 8, 13
312 *
313 * The config-space registers located at 0x41/0x42/0x43/0x44 are
314 * always used to route the normal PCI INT A/B/C/D respectively.
315 * Apparently there are systems implementing PCI routing table using
316 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
317 * We try our best to handle both link mappings.
318 *
319 * Currently (2003-05-21) it appears most SiS chipsets follow the
320 * definition of routing registers from the SiS-5595 southbridge.
321 * According to the SiS 5595 datasheets the revision id's of the
322 * router (ISA-bridge) should be 0x01 or 0xb0.
323 *
324 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
325 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
326 * They seem to work with the current routing code. However there is
327 * some concern because of the two USB-OHCI HCs (original SiS 5595
328 * had only one). YMMV.
329 *
330 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
331 *
332 * 0x61: IDEIRQ:
333 * bits [6:5] must be written 01
334 * bit 4 channel-select primary (0), secondary (1)
335 *
336 * 0x62: USBIRQ:
337 * bit 6 OHCI function disabled (0), enabled (1)
338 *
339 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
340 *
341 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
342 *
343 * We support USBIRQ (in addition to INTA-INTD) and keep the
344 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
345 *
346 * Currently the only reported exception is the new SiS 65x chipset
347 * which includes the SiS 69x southbridge. Here we have the 85C503
348 * router revision 0x04 and there are changes in the register layout
349 * mostly related to the different USB HCs with USB 2.0 support.
350 *
351 * Onchip routing for router rev-id 0x04 (try-and-error observation)
352 *
353 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
354 * bit 6-4 are probably unused, not like 5595
355 */
356
357#define PIRQ_SIS_IRQ_MASK 0x0f
358#define PIRQ_SIS_IRQ_DISABLE 0x80
359#define PIRQ_SIS_USB_ENABLE 0x40
360
361static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
362{
363 u8 x;
364 int reg;
365
366 reg = pirq;
367 if (reg >= 0x01 && reg <= 0x04)
368 reg += 0x40;
369 pci_read_config_byte(router, reg, &x);
370 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
371}
372
373static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
374{
375 u8 x;
376 int reg;
377
378 reg = pirq;
379 if (reg >= 0x01 && reg <= 0x04)
380 reg += 0x40;
381 pci_read_config_byte(router, reg, &x);
382 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
383 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
384 pci_write_config_byte(router, reg, x);
385 return 1;
386}
387
388
389/*
390 * VLSI: nibble offset 0x74 - educated guess due to routing table and
391 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
392 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
393 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
394 * for the busbridge to the docking station.
395 */
396
397static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
398{
399 if (pirq > 8) {
400 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
401 return 0;
402 }
403 return read_config_nybble(router, 0x74, pirq-1);
404}
405
406static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
407{
408 if (pirq > 8) {
409 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
410 return 0;
411 }
412 write_config_nybble(router, 0x74, pirq-1, irq);
413 return 1;
414}
415
416/*
417 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
418 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
419 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
420 * register is a straight binary coding of desired PIC IRQ (low nibble).
421 *
422 * The 'link' value in the PIRQ table is already in the correct format
423 * for the Index register. There are some special index values:
424 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
425 * and 0x03 for SMBus.
426 */
427static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
428{
429 outb_p(pirq, 0xc00);
430 return inb(0xc01) & 0xf;
431}
432
433static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
434{
435 outb_p(pirq, 0xc00);
436 outb_p(irq, 0xc01);
437 return 1;
438}
439
440/* Support for AMD756 PCI IRQ Routing
441 * Jhon H. Caicedo <jhcaiced@osso.org.co>
442 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
443 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
444 * The AMD756 pirq rules are nibble-based
445 * offset 0x56 0-3 PIRQA 4-7 PIRQB
446 * offset 0x57 0-3 PIRQC 4-7 PIRQD
447 */
448static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
449{
450 u8 irq;
451 irq = 0;
452 if (pirq <= 4)
453 {
454 irq = read_config_nybble(router, 0x56, pirq - 1);
455 }
456 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
457 dev->vendor, dev->device, pirq, irq);
458 return irq;
459}
460
461static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
462{
463 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
464 dev->vendor, dev->device, pirq, irq);
465 if (pirq <= 4)
466 {
467 write_config_nybble(router, 0x56, pirq - 1, irq);
468 }
469 return 1;
470}
471
472#ifdef CONFIG_PCI_BIOS
473
474static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
475{
476 struct pci_dev *bridge;
477 int pin = pci_get_interrupt_pin(dev, &bridge);
478 return pcibios_set_irq_routing(bridge, pin, irq);
479}
480
481#endif
482
483static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
484{
485 static struct pci_device_id pirq_440gx[] = {
486 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
487 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
488 { },
489 };
490
491 /* 440GX has a proprietary PIRQ router -- don't use it */
492 if (pci_dev_present(pirq_440gx))
493 return 0;
494
495 switch(device)
496 {
497 case PCI_DEVICE_ID_INTEL_82371FB_0:
498 case PCI_DEVICE_ID_INTEL_82371SB_0:
499 case PCI_DEVICE_ID_INTEL_82371AB_0:
500 case PCI_DEVICE_ID_INTEL_82371MX:
501 case PCI_DEVICE_ID_INTEL_82443MX_0:
502 case PCI_DEVICE_ID_INTEL_82801AA_0:
503 case PCI_DEVICE_ID_INTEL_82801AB_0:
504 case PCI_DEVICE_ID_INTEL_82801BA_0:
505 case PCI_DEVICE_ID_INTEL_82801BA_10:
506 case PCI_DEVICE_ID_INTEL_82801CA_0:
507 case PCI_DEVICE_ID_INTEL_82801CA_12:
508 case PCI_DEVICE_ID_INTEL_82801DB_0:
509 case PCI_DEVICE_ID_INTEL_82801E_0:
510 case PCI_DEVICE_ID_INTEL_82801EB_0:
511 case PCI_DEVICE_ID_INTEL_ESB_1:
512 case PCI_DEVICE_ID_INTEL_ICH6_0:
513 case PCI_DEVICE_ID_INTEL_ICH6_1:
514 case PCI_DEVICE_ID_INTEL_ICH7_0:
515 case PCI_DEVICE_ID_INTEL_ICH7_1:
4d24a439
JG		 516 case PCI_DEVICE_ID_INTEL_ICH7_30:
517 case PCI_DEVICE_ID_INTEL_ICH7_31:
e285f809 518 case PCI_DEVICE_ID_INTEL_ESB2_0:
1da177e4
LT		 519 r->name = "PIIX/ICH";
520 r->get = pirq_piix_get;
521 r->set = pirq_piix_set;
522 return 1;
523 }
524 return 0;
525}
526
527static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
528{
529 /* FIXME: We should move some of the quirk fixup stuff here */
530 switch(device)
531 {
532 case PCI_DEVICE_ID_VIA_82C586_0:
80bb82af
AG		 533 r->name = "VIA";
534 r->get = pirq_via586_get;
535 r->set = pirq_via586_set;
536 return 1;
1da177e4
LT		 537 case PCI_DEVICE_ID_VIA_82C596:
538 case PCI_DEVICE_ID_VIA_82C686:
539 case PCI_DEVICE_ID_VIA_8231:
540 /* FIXME: add new ones for 8233/5 */
541 r->name = "VIA";
542 r->get = pirq_via_get;
543 r->set = pirq_via_set;
544 return 1;
545 }
546 return 0;
547}
548
549static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
550{
551 switch(device)
552 {
553 case PCI_DEVICE_ID_VLSI_82C534:
554 r->name = "VLSI 82C534";
555 r->get = pirq_vlsi_get;
556 r->set = pirq_vlsi_set;
557 return 1;
558 }
559 return 0;
560}
561
562
563static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
564{
565 switch(device)
566 {
567 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
568 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
569 r->name = "ServerWorks";
570 r->get = pirq_serverworks_get;
571 r->set = pirq_serverworks_set;
572 return 1;
573 }
574 return 0;
575}
576
577static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
578{
579 if (device != PCI_DEVICE_ID_SI_503)
580 return 0;
581
582 r->name = "SIS";
583 r->get = pirq_sis_get;
584 r->set = pirq_sis_set;
585 return 1;
586}
587
588static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
589{
590 switch(device)
591 {
592 case PCI_DEVICE_ID_CYRIX_5520:
593 r->name = "NatSemi";
594 r->get = pirq_cyrix_get;
595 r->set = pirq_cyrix_set;
596 return 1;
597 }
598 return 0;
599}
600
601static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
602{
603 switch(device)
604 {
605 case PCI_DEVICE_ID_OPTI_82C700:
606 r->name = "OPTI";
607 r->get = pirq_opti_get;
608 r->set = pirq_opti_set;
609 return 1;
610 }
611 return 0;
612}
613
614static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
615{
616 switch(device)
617 {
618 case PCI_DEVICE_ID_ITE_IT8330G_0:
619 r->name = "ITE";
620 r->get = pirq_ite_get;
621 r->set = pirq_ite_set;
622 return 1;
623 }
624 return 0;
625}
626
627static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
628{
629 switch(device)
630 {
631 case PCI_DEVICE_ID_AL_M1533:
632 case PCI_DEVICE_ID_AL_M1563:
633 printk("PCI: Using ALI IRQ Router\n");
634 r->name = "ALI";
635 r->get = pirq_ali_get;
636 r->set = pirq_ali_set;
637 return 1;
638 }
639 return 0;
640}
641
642static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
643{
644 switch(device)
645 {
646 case PCI_DEVICE_ID_AMD_VIPER_740B:
647 r->name = "AMD756";
648 break;
649 case PCI_DEVICE_ID_AMD_VIPER_7413:
650 r->name = "AMD766";
651 break;
652 case PCI_DEVICE_ID_AMD_VIPER_7443:
653 r->name = "AMD768";
654 break;
655 default:
656 return 0;
657 }
658 r->get = pirq_amd756_get;
659 r->set = pirq_amd756_set;
660 return 1;
661}
662
663static __initdata struct irq_router_handler pirq_routers[] = {
664 { PCI_VENDOR_ID_INTEL, intel_router_probe },
665 { PCI_VENDOR_ID_AL, ali_router_probe },
666 { PCI_VENDOR_ID_ITE, ite_router_probe },
667 { PCI_VENDOR_ID_VIA, via_router_probe },
668 { PCI_VENDOR_ID_OPTI, opti_router_probe },
669 { PCI_VENDOR_ID_SI, sis_router_probe },
670 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
671 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
672 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
673 { PCI_VENDOR_ID_AMD, amd_router_probe },
674 /* Someone with docs needs to add the ATI Radeon IGP */
675 { 0, NULL }
676};
677static struct irq_router pirq_router;
678static struct pci_dev *pirq_router_dev;
679
680
681/*
682 * FIXME: should we have an option to say "generic for
683 * chipset" ?
684 */
685
686static void __init pirq_find_router(struct irq_router *r)
687{
688 struct irq_routing_table *rt = pirq_table;
689 struct irq_router_handler *h;
690
691#ifdef CONFIG_PCI_BIOS
692 if (!rt->signature) {
693 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
694 r->set = pirq_bios_set;
695 r->name = "BIOS";
696 return;
697 }
698#endif
699
700 /* Default unless a driver reloads it */
701 r->name = "default";
702 r->get = NULL;
703 r->set = NULL;
704
705 DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
706 rt->rtr_vendor, rt->rtr_device);
707
708 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
709 if (!pirq_router_dev) {
710 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
711 return;
712 }
713
714 for( h = pirq_routers; h->vendor; h++) {
715 /* First look for a router match */
716 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
717 break;
718 /* Fall back to a device match */
719 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
720 break;
721 }
722 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
723 pirq_router.name,
724 pirq_router_dev->vendor,
725 pirq_router_dev->device,
726 pci_name(pirq_router_dev));
727}
728
729static struct irq_info *pirq_get_info(struct pci_dev *dev)
730{
731 struct irq_routing_table *rt = pirq_table;
732 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
733 struct irq_info *info;
734
735 for (info = rt->slots; entries--; info++)
736 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
737 return info;
738 return NULL;
739}
740
741static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
742{
743 u8 pin;
744 struct irq_info *info;
745 int i, pirq, newirq;
746 int irq = 0;
747 u32 mask;
748 struct irq_router *r = &pirq_router;
749 struct pci_dev *dev2 = NULL;
750 char *msg = NULL;
751
752 /* Find IRQ pin */
753 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
754 if (!pin) {
755 DBG(" -> no interrupt pin\n");
756 return 0;
757 }
758 pin = pin - 1;
759
760 /* Find IRQ routing entry */
761
762 if (!pirq_table)
763 return 0;
764
765 DBG("IRQ for %s[%c]", pci_name(dev), 'A' + pin);
766 info = pirq_get_info(dev);
767 if (!info) {
768 DBG(" -> not found in routing table\n");
769 return 0;
770 }
771 pirq = info->irq[pin].link;
772 mask = info->irq[pin].bitmap;
773 if (!pirq) {
774 DBG(" -> not routed\n");
775 return 0;
776 }
777 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
778 mask &= pcibios_irq_mask;
779
780 /* Work around broken HP Pavilion Notebooks which assign USB to
781 IRQ 9 even though it is actually wired to IRQ 11 */
782
783 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
784 dev->irq = 11;
785 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
786 r->set(pirq_router_dev, dev, pirq, 11);
787 }
788
789 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
790 if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
791 pirq = 0x68;
792 mask = 0x400;
793 dev->irq = r->get(pirq_router_dev, dev, pirq);
794 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
795 }
796
797 /*
798 * Find the best IRQ to assign: use the one
799 * reported by the device if possible.
800 */
801 newirq = dev->irq;
802 if (!((1 << newirq) & mask)) {
803 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
804 else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, pci_name(dev));
805 }
806 if (!newirq && assign) {
807 for (i = 0; i < 16; i++) {
808 if (!(mask & (1 << i)))
809 continue;
810 if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, SA_SHIRQ))
811 newirq = i;
812 }
813 }
814 DBG(" -> newirq=%d", newirq);
815
816 /* Check if it is hardcoded */
817 if ((pirq & 0xf0) == 0xf0) {
818 irq = pirq & 0xf;
819 DBG(" -> hardcoded IRQ %d\n", irq);
820 msg = "Hardcoded";
821 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
822 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
823 DBG(" -> got IRQ %d\n", irq);
824 msg = "Found";
825 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
826 DBG(" -> assigning IRQ %d", newirq);
827 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
828 eisa_set_level_irq(newirq);
829 DBG(" ... OK\n");
830 msg = "Assigned";
831 irq = newirq;
832 }
833 }
834
835 if (!irq) {
836 DBG(" ... failed\n");
837 if (newirq && mask == (1 << newirq)) {
838 msg = "Guessed";
839 irq = newirq;
840 } else
841 return 0;
842 }
843 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
844
845 /* Update IRQ for all devices with the same pirq value */
846 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
847 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
848 if (!pin)
849 continue;
850 pin--;
851 info = pirq_get_info(dev2);
852 if (!info)
853 continue;
854 if (info->irq[pin].link == pirq) {
855 /* We refuse to override the dev->irq information. Give a warning! */
856 if ( dev2->irq && dev2->irq != irq && \
857 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
858 ((1 << dev2->irq) & mask)) ) {
859#ifndef CONFIG_PCI_MSI
860 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
861 pci_name(dev2), dev2->irq, irq);
862#endif
863 continue;
864 }
865 dev2->irq = irq;
866 pirq_penalty[irq]++;
867 if (dev != dev2)
868 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
869 }
870 }
871 return 1;
872}
873
874static void __init pcibios_fixup_irqs(void)
875{
876 struct pci_dev *dev = NULL;
877 u8 pin;
878
879 DBG("PCI: IRQ fixup\n");
880 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
881 /*
882 * If the BIOS has set an out of range IRQ number, just ignore it.
883 * Also keep track of which IRQ's are already in use.
884 */
885 if (dev->irq >= 16) {
886 DBG("%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
887 dev->irq = 0;
888 }
889 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
890 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
891 pirq_penalty[dev->irq] = 0;
892 pirq_penalty[dev->irq]++;
893 }
894
895 dev = NULL;
896 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
897 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
898#ifdef CONFIG_X86_IO_APIC
899 /*
900 * Recalculate IRQ numbers if we use the I/O APIC.
901 */
902 if (io_apic_assign_pci_irqs)
903 {
904 int irq;
905
906 if (pin) {
907 pin--; /* interrupt pins are numbered starting from 1 */
908 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
909 /*
910 * Busses behind bridges are typically not listed in the MP-table.
911 * In this case we have to look up the IRQ based on the parent bus,
912 * parent slot, and pin number. The SMP code detects such bridged
913 * busses itself so we should get into this branch reliably.
914 */
915 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
916 struct pci_dev * bridge = dev->bus->self;
917
918 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
919 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
920 PCI_SLOT(bridge->devfn), pin);
921 if (irq >= 0)
922 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
923 pci_name(bridge), 'A' + pin, irq);
924 }
925 if (irq >= 0) {
926 if (use_pci_vector() &&
927 !platform_legacy_irq(irq))
928 irq = IO_APIC_VECTOR(irq);
929
930 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
931 pci_name(dev), 'A' + pin, irq);
932 dev->irq = irq;
933 }
934 }
935 }
936#endif
937 /*
938 * Still no IRQ? Try to lookup one...
939 */
940 if (pin && !dev->irq)
941 pcibios_lookup_irq(dev, 0);
942 }
943}
944
945/*
946 * Work around broken HP Pavilion Notebooks which assign USB to
947 * IRQ 9 even though it is actually wired to IRQ 11
948 */
949static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d)
950{
951 if (!broken_hp_bios_irq9) {
952 broken_hp_bios_irq9 = 1;
953 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
954 }
955 return 0;
956}
957
958/*
959 * Work around broken Acer TravelMate 360 Notebooks which assign
960 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
961 */
962static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d)
963{
964 if (!acer_tm360_irqrouting) {
965 acer_tm360_irqrouting = 1;
966 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
967 }
968 return 0;
969}
970
971static struct dmi_system_id __initdata pciirq_dmi_table[] = {
972 {
973 .callback = fix_broken_hp_bios_irq9,
974 .ident = "HP Pavilion N5400 Series Laptop",
975 .matches = {
976 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
977 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
978 DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"),
979 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
980 },
981 },
982 {
983 .callback = fix_acer_tm360_irqrouting,
984 .ident = "Acer TravelMate 36x Laptop",
985 .matches = {
986 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
988 },
989 },
990 { }
991};
992
993static int __init pcibios_irq_init(void)
994{
995 DBG("PCI: IRQ init\n");
996
997 if (pcibios_enable_irq || raw_pci_ops == NULL)
998 return 0;
999
1000 dmi_check_system(pciirq_dmi_table);
1001
1002 pirq_table = pirq_find_routing_table();
1003
1004#ifdef CONFIG_PCI_BIOS
1005 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
1006 pirq_table = pcibios_get_irq_routing_table();
1007#endif
1008 if (pirq_table) {
1009 pirq_peer_trick();
1010 pirq_find_router(&pirq_router);
1011 if (pirq_table->exclusive_irqs) {
1012 int i;
1013 for (i=0; i<16; i++)
1014 if (!(pirq_table->exclusive_irqs & (1 << i)))
1015 pirq_penalty[i] += 100;
1016 }
1017 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
1018 if (io_apic_assign_pci_irqs)
1019 pirq_table = NULL;
1020 }
1021
1022 pcibios_enable_irq = pirq_enable_irq;
1023
1024 pcibios_fixup_irqs();
1025 return 0;
1026}
1027
1028subsys_initcall(pcibios_irq_init);
1029
1030
1031static void pirq_penalize_isa_irq(int irq)
1032{
1033 /*
1034 * If any ISAPnP device reports an IRQ in its list of possible
1035 * IRQ's, we try to avoid assigning it to PCI devices.
1036 */
1037 if (irq < 16)
1038 pirq_penalty[irq] += 100;
1039}
1040
1041void pcibios_penalize_isa_irq(int irq)
1042{
1043#ifdef CONFIG_ACPI_PCI
1044 if (!acpi_noirq)
1045 acpi_penalize_isa_irq(irq);
1046 else
1047#endif
1048 pirq_penalize_isa_irq(irq);
1049}
1050
1051static int pirq_enable_irq(struct pci_dev *dev)
1052{
1053 u8 pin;
1da177e4
LT		 1054 struct pci_dev *temp_dev;
1055
1056 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1057 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1058 char *msg = "";
1059
1060 pin--; /* interrupt pins are numbered starting from 1 */
1061
1062 if (io_apic_assign_pci_irqs) {
1063 int irq;
1064
1065 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1066 /*
1067 * Busses behind bridges are typically not listed in the MP-table.
1068 * In this case we have to look up the IRQ based on the parent bus,
1069 * parent slot, and pin number. The SMP code detects such bridged
1070 * busses itself so we should get into this branch reliably.
1071 */
1072 temp_dev = dev;
1073 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1074 struct pci_dev * bridge = dev->bus->self;
1075
1076 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1077 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1078 PCI_SLOT(bridge->devfn), pin);
1079 if (irq >= 0)
1080 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
1081 pci_name(bridge), 'A' + pin, irq);
1082 dev = bridge;
1083 }
1084 dev = temp_dev;
1085 if (irq >= 0) {
1086#ifdef CONFIG_PCI_MSI
1087 if (!platform_legacy_irq(irq))
1088 irq = IO_APIC_VECTOR(irq);
1089#endif
1090 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
1091 pci_name(dev), 'A' + pin, irq);
1092 dev->irq = irq;
1093 return 0;
1094 } else
1095 msg = " Probably buggy MP table.";
1096 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1097 msg = "";
1098 else
1099 msg = " Please try using pci=biosirq.";
1100
1101 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1102 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1103 return 0;
1104
1105 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1106 'A' + pin, pci_name(dev), msg);
1107 }
1da177e4
LT		 1108 return 0;
1109}
1110
1111int pci_vector_resources(int last, int nr_released)
1112{
1113 int count = nr_released;
1114
1115 int next = last;
1116 int offset = (last % 8);
1117
1118 while (next < FIRST_SYSTEM_VECTOR) {
1119 next += 8;
1120#ifdef CONFIG_X86_64
1121 if (next == IA32_SYSCALL_VECTOR)
1122 continue;
1123#else
1124 if (next == SYSCALL_VECTOR)
1125 continue;
1126#endif
1127 count++;
1128 if (next >= FIRST_SYSTEM_VECTOR) {
1129 if (offset%8) {
1130 next = FIRST_DEVICE_VECTOR + offset;
1131 offset++;
1132 continue;
1133 }
1134 count--;
1135 }
1136 }
1137
1138 return count;
1139}
Linux 6.x block layer and io_uring tree(s)