[linux-2.6-block.git] / arch / i386 / kernel / nmi.c

/*
 *  linux/arch/i386/nmi.c
 *
 *  NMI watchdog support on APIC systems
 *
 *  Started by Ingo Molnar <mingo@redhat.com>
 *
 *  Fixes:
 *  Mikael Pettersson	: AMD K7 support for local APIC NMI watchdog.
 *  Mikael Pettersson	: Power Management for local APIC NMI watchdog.
 *  Mikael Pettersson	: Pentium 4 support for local APIC NMI watchdog.
 *  Pavel Machek and
 *  Mikael Pettersson	: PM converted to driver model. Disable/enable API.
 */

#include <linux/config.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/smp_lock.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/nmi.h>
#include <linux/sysdev.h>
#include <linux/sysctl.h>

#include <asm/smp.h>
#include <asm/div64.h>
#include <asm/nmi.h>

#include "mach_traps.h"

unsigned int nmi_watchdog = NMI_NONE;
extern int unknown_nmi_panic;
static unsigned int nmi_hz = HZ;
static unsigned int nmi_perfctr_msr;	/* the MSR to reset in NMI handler */
static unsigned int nmi_p4_cccr_val;
extern void show_registers(struct pt_regs *regs);

/*
 * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
 * - it may be reserved by some other driver, or not
 * - when not reserved by some other driver, it may be used for
 *   the NMI watchdog, or not
 *
 * This is maintained separately from nmi_active because the NMI
 * watchdog may also be driven from the I/O APIC timer.
 */
static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
static unsigned int lapic_nmi_owner;
#define LAPIC_NMI_WATCHDOG	(1<<0)
#define LAPIC_NMI_RESERVED	(1<<1)

/* nmi_active:
 * +1: the lapic NMI watchdog is active, but can be disabled
 *  0: the lapic NMI watchdog has not been set up, and cannot
 *     be enabled
 * -1: the lapic NMI watchdog is disabled, but can be enabled
 */
int nmi_active;

#define K7_EVNTSEL_ENABLE	(1 << 22)
#define K7_EVNTSEL_INT		(1 << 20)
#define K7_EVNTSEL_OS		(1 << 17)
#define K7_EVNTSEL_USR		(1 << 16)
#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING	0x76
#define K7_NMI_EVENT		K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING

#define P6_EVNTSEL0_ENABLE	(1 << 22)
#define P6_EVNTSEL_INT		(1 << 20)
#define P6_EVNTSEL_OS		(1 << 17)
#define P6_EVNTSEL_USR		(1 << 16)
#define P6_EVENT_CPU_CLOCKS_NOT_HALTED	0x79
#define P6_NMI_EVENT		P6_EVENT_CPU_CLOCKS_NOT_HALTED

#define MSR_P4_MISC_ENABLE	0x1A0
#define MSR_P4_MISC_ENABLE_PERF_AVAIL	(1<<7)
#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL	(1<<12)
#define MSR_P4_PERFCTR0		0x300
#define MSR_P4_CCCR0		0x360
#define P4_ESCR_EVENT_SELECT(N)	((N)<<25)
#define P4_ESCR_OS		(1<<3)
#define P4_ESCR_USR		(1<<2)
#define P4_CCCR_OVF_PMI0	(1<<26)
#define P4_CCCR_OVF_PMI1	(1<<27)
#define P4_CCCR_THRESHOLD(N)	((N)<<20)
#define P4_CCCR_COMPLEMENT	(1<<19)
#define P4_CCCR_COMPARE		(1<<18)
#define P4_CCCR_REQUIRED	(3<<16)
#define P4_CCCR_ESCR_SELECT(N)	((N)<<13)
#define P4_CCCR_ENABLE		(1<<12)
/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
   CRU_ESCR0 (with any non-null event selector) through a complemented
   max threshold. [IA32-Vol3, Section 14.9.9] */
#define MSR_P4_IQ_COUNTER0	0x30C
#define P4_NMI_CRU_ESCR0	(P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
#define P4_NMI_IQ_CCCR0	\
	(P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|	\
	 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)

#ifdef CONFIG_SMP
/* The performance counters used by NMI_LOCAL_APIC don't trigger when
 * the CPU is idle. To make sure the NMI watchdog really ticks on all
 * CPUs during the test make them busy.
 */
static __init void nmi_cpu_busy(void *data)
{
	volatile int *endflag = data;
	local_irq_enable();
	/* Intentionally don't use cpu_relax here. This is
	   to make sure that the performance counter really ticks,
	   even if there is a simulator or similar that catches the
	   pause instruction. On a real HT machine this is fine because
	   all other CPUs are busy with "useless" delay loops and don't
	   care if they get somewhat less cycles. */
	while (*endflag == 0)
		barrier();
}
#endif

static int __init check_nmi_watchdog(void)
{
	volatile int endflag = 0;
	unsigned int *prev_nmi_count;
	int cpu;

	if (nmi_watchdog == NMI_NONE)
		return 0;

	prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
	if (!prev_nmi_count)
		return -1;

	printk(KERN_INFO "Testing NMI watchdog ... ");

	if (nmi_watchdog == NMI_LOCAL_APIC)
		smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);

	for (cpu = 0; cpu < NR_CPUS; cpu++)
		prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
	local_irq_enable();
	mdelay((10*1000)/nmi_hz); // wait 10 ticks

	for (cpu = 0; cpu < NR_CPUS; cpu++) {
#ifdef CONFIG_SMP
		/* Check cpu_callin_map here because that is set
		   after the timer is started. */
		if (!cpu_isset(cpu, cpu_callin_map))
			continue;
#endif
		if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
			endflag = 1;
			printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
				cpu,
				prev_nmi_count[cpu],
				nmi_count(cpu));
			nmi_active = 0;
			lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
			kfree(prev_nmi_count);
			return -1;
		}
	}
	endflag = 1;
	printk("OK.\n");

	/* now that we know it works we can reduce NMI frequency to
	   something more reasonable; makes a difference in some configs */
	if (nmi_watchdog == NMI_LOCAL_APIC)
		nmi_hz = 1;

	kfree(prev_nmi_count);
	return 0;
}
/* This needs to happen later in boot so counters are working */
late_initcall(check_nmi_watchdog);

static int __init setup_nmi_watchdog(char *str)
{
	int nmi;

	get_option(&str, &nmi);

	if (nmi >= NMI_INVALID)
		return 0;
	if (nmi == NMI_NONE)
		nmi_watchdog = nmi;
	/*
	 * If any other x86 CPU has a local APIC, then
	 * please test the NMI stuff there and send me the
	 * missing bits. Right now Intel P6/P4 and AMD K7 only.
	 */
	if ((nmi == NMI_LOCAL_APIC) &&
			(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
			(boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
		nmi_watchdog = nmi;
	if ((nmi == NMI_LOCAL_APIC) &&
			(boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
	  		(boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
		nmi_watchdog = nmi;
	/*
	 * We can enable the IO-APIC watchdog
	 * unconditionally.
	 */
	if (nmi == NMI_IO_APIC) {
		nmi_active = 1;
		nmi_watchdog = nmi;
	}
	return 1;
}

__setup("nmi_watchdog=", setup_nmi_watchdog);

static void disable_lapic_nmi_watchdog(void)
{
	if (nmi_active <= 0)
		return;
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		wrmsr(MSR_K7_EVNTSEL0, 0, 0);
		break;
	case X86_VENDOR_INTEL:
		switch (boot_cpu_data.x86) {
		case 6:
			if (boot_cpu_data.x86_model > 0xd)
				break;

			wrmsr(MSR_P6_EVNTSEL0, 0, 0);
			break;
		case 15:
			if (boot_cpu_data.x86_model > 0x4)
				break;

			wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
			wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
			break;
		}
		break;
	}
	nmi_active = -1;
	/* tell do_nmi() and others that we're not active any more */
	nmi_watchdog = 0;
}

static void enable_lapic_nmi_watchdog(void)
{
	if (nmi_active < 0) {
		nmi_watchdog = NMI_LOCAL_APIC;
		setup_apic_nmi_watchdog();
	}
}

int reserve_lapic_nmi(void)
{
	unsigned int old_owner;

	spin_lock(&lapic_nmi_owner_lock);
	old_owner = lapic_nmi_owner;
	lapic_nmi_owner |= LAPIC_NMI_RESERVED;
	spin_unlock(&lapic_nmi_owner_lock);
	if (old_owner & LAPIC_NMI_RESERVED)
		return -EBUSY;
	if (old_owner & LAPIC_NMI_WATCHDOG)
		disable_lapic_nmi_watchdog();
	return 0;
}

void release_lapic_nmi(void)
{
	unsigned int new_owner;

	spin_lock(&lapic_nmi_owner_lock);
	new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
	lapic_nmi_owner = new_owner;
	spin_unlock(&lapic_nmi_owner_lock);
	if (new_owner & LAPIC_NMI_WATCHDOG)
		enable_lapic_nmi_watchdog();
}

void disable_timer_nmi_watchdog(void)
{
	if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
		return;

	unset_nmi_callback();
	nmi_active = -1;
	nmi_watchdog = NMI_NONE;
}

void enable_timer_nmi_watchdog(void)
{
	if (nmi_active < 0) {
		nmi_watchdog = NMI_IO_APIC;
		touch_nmi_watchdog();
		nmi_active = 1;
	}
}

#ifdef CONFIG_PM

static int nmi_pm_active; /* nmi_active before suspend */

static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	nmi_pm_active = nmi_active;
	disable_lapic_nmi_watchdog();
	return 0;
}

static int lapic_nmi_resume(struct sys_device *dev)
{
	if (nmi_pm_active > 0)
		enable_lapic_nmi_watchdog();
	return 0;
}


static struct sysdev_class nmi_sysclass = {
	set_kset_name("lapic_nmi"),
	.resume		= lapic_nmi_resume,
	.suspend	= lapic_nmi_suspend,
};

static struct sys_device device_lapic_nmi = {
	.id	= 0,
	.cls	= &nmi_sysclass,
};

static int __init init_lapic_nmi_sysfs(void)
{
	int error;

	if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
		return 0;

	error = sysdev_class_register(&nmi_sysclass);
	if (!error)
		error = sysdev_register(&device_lapic_nmi);
	return error;
}
/* must come after the local APIC's device_initcall() */
late_initcall(init_lapic_nmi_sysfs);

#endif	/* CONFIG_PM */

/*
 * Activate the NMI watchdog via the local APIC.
 * Original code written by Keith Owens.
 */

static void clear_msr_range(unsigned int base, unsigned int n)
{
	unsigned int i;

	for(i = 0; i < n; ++i)
		wrmsr(base+i, 0, 0);
}

static inline void write_watchdog_counter(const char *descr)
{
	u64 count = (u64)cpu_khz * 1000;

	do_div(count, nmi_hz);
	if(descr)
		Dprintk("setting %s to -0x%08Lx\n", descr, count);
	wrmsrl(nmi_perfctr_msr, 0 - count);
}

static void setup_k7_watchdog(void)
{
	unsigned int evntsel;

	nmi_perfctr_msr = MSR_K7_PERFCTR0;

	clear_msr_range(MSR_K7_EVNTSEL0, 4);
	clear_msr_range(MSR_K7_PERFCTR0, 4);

	evntsel = K7_EVNTSEL_INT
		| K7_EVNTSEL_OS
		| K7_EVNTSEL_USR
		| K7_NMI_EVENT;

	wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
	write_watchdog_counter("K7_PERFCTR0");
	apic_write(APIC_LVTPC, APIC_DM_NMI);
	evntsel |= K7_EVNTSEL_ENABLE;
	wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
}

static void setup_p6_watchdog(void)
{
	unsigned int evntsel;

	nmi_perfctr_msr = MSR_P6_PERFCTR0;

	clear_msr_range(MSR_P6_EVNTSEL0, 2);
	clear_msr_range(MSR_P6_PERFCTR0, 2);

	evntsel = P6_EVNTSEL_INT
		| P6_EVNTSEL_OS
		| P6_EVNTSEL_USR
		| P6_NMI_EVENT;

	wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
	write_watchdog_counter("P6_PERFCTR0");
	apic_write(APIC_LVTPC, APIC_DM_NMI);
	evntsel |= P6_EVNTSEL0_ENABLE;
	wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
}

static int setup_p4_watchdog(void)
{
	unsigned int misc_enable, dummy;

	rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
	if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
		return 0;

	nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
	nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
#ifdef CONFIG_SMP
	if (smp_num_siblings == 2)
		nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
#endif

	if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
		clear_msr_range(0x3F1, 2);
	/* MSR 0x3F0 seems to have a default value of 0xFC00, but current
	   docs doesn't fully define it, so leave it alone for now. */
	if (boot_cpu_data.x86_model >= 0x3) {
		/* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
		clear_msr_range(0x3A0, 26);
		clear_msr_range(0x3BC, 3);
	} else {
		clear_msr_range(0x3A0, 31);
	}
	clear_msr_range(0x3C0, 6);
	clear_msr_range(0x3C8, 6);
	clear_msr_range(0x3E0, 2);
	clear_msr_range(MSR_P4_CCCR0, 18);
	clear_msr_range(MSR_P4_PERFCTR0, 18);

	wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
	wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
	write_watchdog_counter("P4_IQ_COUNTER0");
	apic_write(APIC_LVTPC, APIC_DM_NMI);
	wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
	return 1;
}

void setup_apic_nmi_watchdog (void)
{
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
			return;
		setup_k7_watchdog();
		break;
	case X86_VENDOR_INTEL:
		switch (boot_cpu_data.x86) {
		case 6:
			if (boot_cpu_data.x86_model > 0xd)
				return;

			setup_p6_watchdog();
			break;
		case 15:
			if (boot_cpu_data.x86_model > 0x4)
				return;

			if (!setup_p4_watchdog())
				return;
			break;
		default:
			return;
		}
		break;
	default:
		return;
	}
	lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
	nmi_active = 1;
}

/*
 * the best way to detect whether a CPU has a 'hard lockup' problem
 * is to check it's local APIC timer IRQ counts. If they are not
 * changing then that CPU has some problem.
 *
 * as these watchdog NMI IRQs are generated on every CPU, we only
 * have to check the current processor.
 *
 * since NMIs don't listen to _any_ locks, we have to be extremely
 * careful not to rely on unsafe variables. The printk might lock
 * up though, so we have to break up any console locks first ...
 * [when there will be more tty-related locks, break them up
 *  here too!]
 */

static unsigned int
	last_irq_sums [NR_CPUS],
	alert_counter [NR_CPUS];

void touch_nmi_watchdog (void)
{
	int i;

	/*
	 * Just reset the alert counters, (other CPUs might be
	 * spinning on locks we hold):
	 */
	for (i = 0; i < NR_CPUS; i++)
		alert_counter[i] = 0;

	/*
	 * Tickle the softlockup detector too:
	 */
	touch_softlockup_watchdog();
}

extern void die_nmi(struct pt_regs *, const char *msg);

void nmi_watchdog_tick (struct pt_regs * regs)
{

	/*
	 * Since current_thread_info()-> is always on the stack, and we
	 * always switch the stack NMI-atomically, it's safe to use
	 * smp_processor_id().
	 */
	int sum, cpu = smp_processor_id();

	sum = per_cpu(irq_stat, cpu).apic_timer_irqs;

	if (last_irq_sums[cpu] == sum) {
		/*
		 * Ayiee, looks like this CPU is stuck ...
		 * wait a few IRQs (5 seconds) before doing the oops ...
		 */
		alert_counter[cpu]++;
		if (alert_counter[cpu] == 5*nmi_hz)
			/*
			 * die_nmi will return ONLY if NOTIFY_STOP happens..
			 */
			die_nmi(regs, "NMI Watchdog detected LOCKUP");

		last_irq_sums[cpu] = sum;
		alert_counter[cpu] = 0;
	}
	if (nmi_perfctr_msr) {
		if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
			/*
			 * P4 quirks:
			 * - An overflown perfctr will assert its interrupt
			 *   until the OVF flag in its CCCR is cleared.
			 * - LVTPC is masked on interrupt and must be
			 *   unmasked by the LVTPC handler.
			 */
			wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
			apic_write(APIC_LVTPC, APIC_DM_NMI);
		}
		else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
			/* Only P6 based Pentium M need to re-unmask
			 * the apic vector but it doesn't hurt
			 * other P6 variant */
			apic_write(APIC_LVTPC, APIC_DM_NMI);
		}
		write_watchdog_counter(NULL);
	}
}

#ifdef CONFIG_SYSCTL

static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
{
	unsigned char reason = get_nmi_reason();
	char buf[64];

	if (!(reason & 0xc0)) {
		sprintf(buf, "NMI received for unknown reason %02x\n", reason);
		die_nmi(regs, buf);
	}
	return 0;
}

/*
 * proc handler for /proc/sys/kernel/unknown_nmi_panic
 */
int proc_unknown_nmi_panic(ctl_table *table, int write, struct file *file,
			void __user *buffer, size_t *length, loff_t *ppos)
{
	int old_state;

	old_state = unknown_nmi_panic;
	proc_dointvec(table, write, file, buffer, length, ppos);
	if (!!old_state == !!unknown_nmi_panic)
		return 0;

	if (unknown_nmi_panic) {
		if (reserve_lapic_nmi() < 0) {
			unknown_nmi_panic = 0;
			return -EBUSY;
		} else {
			set_nmi_callback(unknown_nmi_panic_callback);
		}
	} else {
		release_lapic_nmi();
		unset_nmi_callback();
	}
	return 0;
}

#endif

EXPORT_SYMBOL(nmi_active);
EXPORT_SYMBOL(nmi_watchdog);
EXPORT_SYMBOL(reserve_lapic_nmi);
EXPORT_SYMBOL(release_lapic_nmi);
EXPORT_SYMBOL(disable_timer_nmi_watchdog);
EXPORT_SYMBOL(enable_timer_nmi_watchdog);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/i386/nmi.c
	3	*
	4	* NMI watchdog support on APIC systems
	5	*
	6	* Started by Ingo Molnar <mingo@redhat.com>
	7	*
	8	* Fixes:
	9	* Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
	10	* Mikael Pettersson : Power Management for local APIC NMI watchdog.
	11	* Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
	12	* Pavel Machek and
	13	* Mikael Pettersson : PM converted to driver model. Disable/enable API.
	14	*/
	15
	16	#include <linux/config.h>
	17	#include <linux/mm.h>
1da177e4 LT	18	#include <linux/delay.h>
	19	#include <linux/bootmem.h>
	20	#include <linux/smp_lock.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/mc146818rtc.h>
	23	#include <linux/kernel_stat.h>
	24	#include <linux/module.h>
	25	#include <linux/nmi.h>
	26	#include <linux/sysdev.h>
	27	#include <linux/sysctl.h>
	28
	29	#include <asm/smp.h>
7fbb4f6e	30	#include <asm/div64.h>
1da177e4 LT	31	#include <asm/nmi.h>
	32
	33	#include "mach_traps.h"
	34
	35	unsigned int nmi_watchdog = NMI_NONE;
	36	extern int unknown_nmi_panic;
	37	static unsigned int nmi_hz = HZ;
	38	static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
	39	static unsigned int nmi_p4_cccr_val;
	40	extern void show_registers(struct pt_regs *regs);
	41
	42	/*
	43	* lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
	44	* - it may be reserved by some other driver, or not
	45	* - when not reserved by some other driver, it may be used for
	46	* the NMI watchdog, or not
	47	*
	48	* This is maintained separately from nmi_active because the NMI
	49	* watchdog may also be driven from the I/O APIC timer.
	50	*/
	51	static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
	52	static unsigned int lapic_nmi_owner;
	53	#define LAPIC_NMI_WATCHDOG (1<<0)
	54	#define LAPIC_NMI_RESERVED (1<<1)
	55
	56	/* nmi_active:
	57	* +1: the lapic NMI watchdog is active, but can be disabled
	58	* 0: the lapic NMI watchdog has not been set up, and cannot
	59	* be enabled
	60	* -1: the lapic NMI watchdog is disabled, but can be enabled
	61	*/
	62	int nmi_active;
	63
	64	#define K7_EVNTSEL_ENABLE (1 << 22)
	65	#define K7_EVNTSEL_INT (1 << 20)
	66	#define K7_EVNTSEL_OS (1 << 17)
	67	#define K7_EVNTSEL_USR (1 << 16)
	68	#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
	69	#define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
	70
	71	#define P6_EVNTSEL0_ENABLE (1 << 22)
	72	#define P6_EVNTSEL_INT (1 << 20)
	73	#define P6_EVNTSEL_OS (1 << 17)
	74	#define P6_EVNTSEL_USR (1 << 16)
	75	#define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
	76	#define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
	77
	78	#define MSR_P4_MISC_ENABLE 0x1A0
	79	#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
	80	#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
	81	#define MSR_P4_PERFCTR0 0x300
	82	#define MSR_P4_CCCR0 0x360
	83	#define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
	84	#define P4_ESCR_OS (1<<3)
	85	#define P4_ESCR_USR (1<<2)
	86	#define P4_CCCR_OVF_PMI0 (1<<26)
	87	#define P4_CCCR_OVF_PMI1 (1<<27)
	88	#define P4_CCCR_THRESHOLD(N) ((N)<<20)
	89	#define P4_CCCR_COMPLEMENT (1<<19)
	90	#define P4_CCCR_COMPARE (1<<18)
	91	#define P4_CCCR_REQUIRED (3<<16)
	92	#define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
	93	#define P4_CCCR_ENABLE (1<<12)
	94	/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
95	CRU_ESCR0 (with any non-null event selector) through a complemented
96	max threshold. [IA32-Vol3, Section 14.9.9] */
97	#define MSR_P4_IQ_COUNTER0 0x30C
98	#define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)\|P4_ESCR_OS\|P4_ESCR_USR)
99	#define P4_NMI_IQ_CCCR0 \
100	(P4_CCCR_OVF_PMI0\|P4_CCCR_THRESHOLD(15)\|P4_CCCR_COMPLEMENT\| \
101	P4_CCCR_COMPARE\|P4_CCCR_REQUIRED\|P4_CCCR_ESCR_SELECT(4)\|P4_CCCR_ENABLE)
102
29b70081 EB	103	#ifdef CONFIG_SMP
	104	/* The performance counters used by NMI_LOCAL_APIC don't trigger when
	105	* the CPU is idle. To make sure the NMI watchdog really ticks on all
	106	* CPUs during the test make them busy.
	107	*/
	108	static __init void nmi_cpu_busy(void *data)
	109	{
	110	volatile int *endflag = data;
	111	local_irq_enable();
	112	/* Intentionally don't use cpu_relax here. This is
	113	to make sure that the performance counter really ticks,
	114	even if there is a simulator or similar that catches the
	115	pause instruction. On a real HT machine this is fine because
	116	all other CPUs are busy with "useless" delay loops and don't
	117	care if they get somewhat less cycles. */
	118	while (*endflag == 0)
	119	barrier();
	120	}
	121	#endif
	122
67701ae9	123	static int __init check_nmi_watchdog(void)
1da177e4	124	{
29b70081 EB	125	volatile int endflag = 0;
29b70081 EB	126	unsigned int *prev_nmi_count;
1da177e4 LT	127	int cpu;
1da177e4 LT	128
67701ae9 JV	129	if (nmi_watchdog == NMI_NONE)
	130	return 0;
	131
29b70081 EB	132	prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
	133	if (!prev_nmi_count)
	134	return -1;
	135
67701ae9	136	printk(KERN_INFO "Testing NMI watchdog ... ");
1da177e4	137
29b70081 EB	138	if (nmi_watchdog == NMI_LOCAL_APIC)
	139	smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
	140
1da177e4 LT	141	for (cpu = 0; cpu < NR_CPUS; cpu++)
	142	prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
	143	local_irq_enable();
	144	mdelay((10*1000)/nmi_hz); // wait 10 ticks
	145
1da177e4 LT	146	for (cpu = 0; cpu < NR_CPUS; cpu++) {
	147	#ifdef CONFIG_SMP
	148	/* Check cpu_callin_map here because that is set
	149	after the timer is started. */
	150	if (!cpu_isset(cpu, cpu_callin_map))
	151	continue;
	152	#endif
	153	if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
29b70081 EB	154	endflag = 1;
	155	printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
	156	cpu,
	157	prev_nmi_count[cpu],
	158	nmi_count(cpu));
1da177e4 LT	159	nmi_active = 0;
1da177e4 LT	160	lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
29b70081	161	kfree(prev_nmi_count);
1da177e4 LT	162	return -1;
	163	}
	164	}
29b70081	165	endflag = 1;
1da177e4 LT	166	printk("OK.\n");
	167
	168	/* now that we know it works we can reduce NMI frequency to
	169	something more reasonable; makes a difference in some configs */
	170	if (nmi_watchdog == NMI_LOCAL_APIC)
	171	nmi_hz = 1;
	172
29b70081	173	kfree(prev_nmi_count);
1da177e4 LT	174	return 0;
1da177e4 LT	175	}
67701ae9 JV	176	/* This needs to happen later in boot so counters are working */
67701ae9 JV	177	late_initcall(check_nmi_watchdog);
1da177e4 LT	178
	179	static int __init setup_nmi_watchdog(char *str)
	180	{
	181	int nmi;
	182
	183	get_option(&str, &nmi);
	184
	185	if (nmi >= NMI_INVALID)
	186	return 0;
	187	if (nmi == NMI_NONE)
	188	nmi_watchdog = nmi;
	189	/*
	190	* If any other x86 CPU has a local APIC, then
	191	* please test the NMI stuff there and send me the
	192	* missing bits. Right now Intel P6/P4 and AMD K7 only.
	193	*/
	194	if ((nmi == NMI_LOCAL_APIC) &&
	195	(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	196	(boot_cpu_data.x86 == 6 \|\| boot_cpu_data.x86 == 15))
	197	nmi_watchdog = nmi;
	198	if ((nmi == NMI_LOCAL_APIC) &&
	199	(boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
	200	(boot_cpu_data.x86 == 6 \|\| boot_cpu_data.x86 == 15))
	201	nmi_watchdog = nmi;
	202	/*
	203	* We can enable the IO-APIC watchdog
	204	* unconditionally.
	205	*/
	206	if (nmi == NMI_IO_APIC) {
	207	nmi_active = 1;
	208	nmi_watchdog = nmi;
	209	}
	210	return 1;
	211	}
	212
	213	__setup("nmi_watchdog=", setup_nmi_watchdog);
	214
	215	static void disable_lapic_nmi_watchdog(void)
	216	{
	217	if (nmi_active <= 0)
	218	return;
	219	switch (boot_cpu_data.x86_vendor) {
	220	case X86_VENDOR_AMD:
	221	wrmsr(MSR_K7_EVNTSEL0, 0, 0);
	222	break;
	223	case X86_VENDOR_INTEL:
	224	switch (boot_cpu_data.x86) {
	225	case 6:
	226	if (boot_cpu_data.x86_model > 0xd)
	227	break;
	228
	229	wrmsr(MSR_P6_EVNTSEL0, 0, 0);
	230	break;
	231	case 15:
cd3716ab	232	if (boot_cpu_data.x86_model > 0x4)
1da177e4 LT	233	break;
	234
	235	wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
	236	wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
	237	break;
	238	}
	239	break;
	240	}
	241	nmi_active = -1;
	242	/* tell do_nmi() and others that we're not active any more */
	243	nmi_watchdog = 0;
	244	}
	245
	246	static void enable_lapic_nmi_watchdog(void)
	247	{
	248	if (nmi_active < 0) {
	249	nmi_watchdog = NMI_LOCAL_APIC;
	250	setup_apic_nmi_watchdog();
	251	}
	252	}
	253
	254	int reserve_lapic_nmi(void)
	255	{
	256	unsigned int old_owner;
	257
	258	spin_lock(&lapic_nmi_owner_lock);
	259	old_owner = lapic_nmi_owner;
	260	lapic_nmi_owner \|= LAPIC_NMI_RESERVED;
	261	spin_unlock(&lapic_nmi_owner_lock);
	262	if (old_owner & LAPIC_NMI_RESERVED)
	263	return -EBUSY;
	264	if (old_owner & LAPIC_NMI_WATCHDOG)
	265	disable_lapic_nmi_watchdog();
	266	return 0;
	267	}
	268
	269	void release_lapic_nmi(void)
	270	{
	271	unsigned int new_owner;
	272
	273	spin_lock(&lapic_nmi_owner_lock);
	274	new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
	275	lapic_nmi_owner = new_owner;
	276	spin_unlock(&lapic_nmi_owner_lock);
	277	if (new_owner & LAPIC_NMI_WATCHDOG)
	278	enable_lapic_nmi_watchdog();
	279	}
	280
	281	void disable_timer_nmi_watchdog(void)
	282	{
	283	if ((nmi_watchdog != NMI_IO_APIC) \|\| (nmi_active <= 0))
	284	return;
	285
	286	unset_nmi_callback();
	287	nmi_active = -1;
	288	nmi_watchdog = NMI_NONE;
	289	}
	290
	291	void enable_timer_nmi_watchdog(void)
	292	{
	293	if (nmi_active < 0) {
	294	nmi_watchdog = NMI_IO_APIC;
	295	touch_nmi_watchdog();
	296	nmi_active = 1;
297	}
298	}
299
300	#ifdef CONFIG_PM
301
302	static int nmi_pm_active; /* nmi_active before suspend */
303
438510f6	304	static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	305	{
	306	nmi_pm_active = nmi_active;
	307	disable_lapic_nmi_watchdog();
	308	return 0;
	309	}
	310
	311	static int lapic_nmi_resume(struct sys_device *dev)
	312	{
	313	if (nmi_pm_active > 0)
	314	enable_lapic_nmi_watchdog();
	315	return 0;
	316	}
	317
	318
	319	static struct sysdev_class nmi_sysclass = {
	320	set_kset_name("lapic_nmi"),
	321	.resume = lapic_nmi_resume,
	322	.suspend = lapic_nmi_suspend,
	323	};
	324
	325	static struct sys_device device_lapic_nmi = {
	326	.id = 0,
	327	.cls = &nmi_sysclass,
	328	};
	329
	330	static int __init init_lapic_nmi_sysfs(void)
	331	{
	332	int error;
	333
	334	if (nmi_active == 0 \|\| nmi_watchdog != NMI_LOCAL_APIC)
	335	return 0;
	336
	337	error = sysdev_class_register(&nmi_sysclass);
	338	if (!error)
	339	error = sysdev_register(&device_lapic_nmi);
	340	return error;
	341	}
	342	/* must come after the local APIC's device_initcall() */
	343	late_initcall(init_lapic_nmi_sysfs);
	344
	345	#endif /* CONFIG_PM */
	346
	347	/*
	348	* Activate the NMI watchdog via the local APIC.
	349	* Original code written by Keith Owens.
	350	*/
	351
	352	static void clear_msr_range(unsigned int base, unsigned int n)
	353	{
	354	unsigned int i;
	355
	356	for(i = 0; i < n; ++i)
	357	wrmsr(base+i, 0, 0);
	358	}
	359
7fbb4f6e JB	360	static inline void write_watchdog_counter(const char *descr)
	361	{
	362	u64 count = (u64)cpu_khz * 1000;
	363
	364	do_div(count, nmi_hz);
	365	if(descr)
	366	Dprintk("setting %s to -0x%08Lx\n", descr, count);
	367	wrmsrl(nmi_perfctr_msr, 0 - count);
	368	}
	369
1da177e4 LT	370	static void setup_k7_watchdog(void)
	371	{
	372	unsigned int evntsel;
	373
	374	nmi_perfctr_msr = MSR_K7_PERFCTR0;
	375
	376	clear_msr_range(MSR_K7_EVNTSEL0, 4);
	377	clear_msr_range(MSR_K7_PERFCTR0, 4);
	378
	379	evntsel = K7_EVNTSEL_INT
	380	\| K7_EVNTSEL_OS
	381	\| K7_EVNTSEL_USR
	382	\| K7_NMI_EVENT;
	383
	384	wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
7fbb4f6e	385	write_watchdog_counter("K7_PERFCTR0");
1da177e4 LT	386	apic_write(APIC_LVTPC, APIC_DM_NMI);
	387	evntsel \|= K7_EVNTSEL_ENABLE;
	388	wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
	389	}
	390
	391	static void setup_p6_watchdog(void)
	392	{
	393	unsigned int evntsel;
	394
	395	nmi_perfctr_msr = MSR_P6_PERFCTR0;
	396
	397	clear_msr_range(MSR_P6_EVNTSEL0, 2);
	398	clear_msr_range(MSR_P6_PERFCTR0, 2);
	399
	400	evntsel = P6_EVNTSEL_INT
	401	\| P6_EVNTSEL_OS
	402	\| P6_EVNTSEL_USR
	403	\| P6_NMI_EVENT;
	404
	405	wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
7fbb4f6e	406	write_watchdog_counter("P6_PERFCTR0");
1da177e4 LT	407	apic_write(APIC_LVTPC, APIC_DM_NMI);
	408	evntsel \|= P6_EVNTSEL0_ENABLE;
	409	wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
	410	}
	411
	412	static int setup_p4_watchdog(void)
	413	{
	414	unsigned int misc_enable, dummy;
	415
	416	rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
	417	if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
	418	return 0;
	419
	420	nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
	421	nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
	422	#ifdef CONFIG_SMP
	423	if (smp_num_siblings == 2)
	424	nmi_p4_cccr_val \|= P4_CCCR_OVF_PMI1;
	425	#endif
	426
	427	if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
	428	clear_msr_range(0x3F1, 2);
	429	/* MSR 0x3F0 seems to have a default value of 0xFC00, but current
	430	docs doesn't fully define it, so leave it alone for now. */
	431	if (boot_cpu_data.x86_model >= 0x3) {
	432	/* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
	433	clear_msr_range(0x3A0, 26);
	434	clear_msr_range(0x3BC, 3);
	435	} else {
	436	clear_msr_range(0x3A0, 31);
	437	}
	438	clear_msr_range(0x3C0, 6);
	439	clear_msr_range(0x3C8, 6);
	440	clear_msr_range(0x3E0, 2);
	441	clear_msr_range(MSR_P4_CCCR0, 18);
	442	clear_msr_range(MSR_P4_PERFCTR0, 18);
	443
	444	wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
	445	wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
7fbb4f6e	446	write_watchdog_counter("P4_IQ_COUNTER0");
1da177e4 LT	447	apic_write(APIC_LVTPC, APIC_DM_NMI);
	448	wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
	449	return 1;
	450	}
	451
	452	void setup_apic_nmi_watchdog (void)
	453	{
	454	switch (boot_cpu_data.x86_vendor) {
	455	case X86_VENDOR_AMD:
	456	if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
	457	return;
	458	setup_k7_watchdog();
	459	break;
	460	case X86_VENDOR_INTEL:
	461	switch (boot_cpu_data.x86) {
	462	case 6:
	463	if (boot_cpu_data.x86_model > 0xd)
	464	return;
	465
	466	setup_p6_watchdog();
	467	break;
	468	case 15:
cd3716ab	469	if (boot_cpu_data.x86_model > 0x4)
1da177e4 LT	470	return;
	471
	472	if (!setup_p4_watchdog())
	473	return;
	474	break;
	475	default:
	476	return;
	477	}
	478	break;
	479	default:
	480	return;
	481	}
	482	lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
	483	nmi_active = 1;
	484	}
	485
	486	/*
	487	* the best way to detect whether a CPU has a 'hard lockup' problem
	488	* is to check it's local APIC timer IRQ counts. If they are not
	489	* changing then that CPU has some problem.
	490	*
	491	* as these watchdog NMI IRQs are generated on every CPU, we only
	492	* have to check the current processor.
	493	*
	494	* since NMIs don't listen to _any_ locks, we have to be extremely
	495	* careful not to rely on unsafe variables. The printk might lock
	496	* up though, so we have to break up any console locks first ...
	497	* [when there will be more tty-related locks, break them up
	498	* here too!]
	499	*/
	500
	501	static unsigned int
	502	last_irq_sums [NR_CPUS],
	503	alert_counter [NR_CPUS];
	504
	505	void touch_nmi_watchdog (void)
	506	{
	507	int i;
	508
	509	/*
	510	* Just reset the alert counters, (other CPUs might be
	511	* spinning on locks we hold):
	512	*/
	513	for (i = 0; i < NR_CPUS; i++)
	514	alert_counter[i] = 0;
8446f1d3 IM	515
	516	/*
	517	* Tickle the softlockup detector too:
	518	*/
	519	touch_softlockup_watchdog();
1da177e4 LT	520	}
	521
	522	extern void die_nmi(struct pt_regs , const char msg);
	523
	524	void nmi_watchdog_tick (struct pt_regs * regs)
	525	{
	526
	527	/*
	528	* Since current_thread_info()-> is always on the stack, and we
	529	* always switch the stack NMI-atomically, it's safe to use
	530	* smp_processor_id().
	531	*/
	532	int sum, cpu = smp_processor_id();
	533
	534	sum = per_cpu(irq_stat, cpu).apic_timer_irqs;
	535
	536	if (last_irq_sums[cpu] == sum) {
	537	/*
	538	* Ayiee, looks like this CPU is stuck ...
	539	* wait a few IRQs (5 seconds) before doing the oops ...
	540	*/
	541	alert_counter[cpu]++;
	542	if (alert_counter[cpu] == 5*nmi_hz)
748f2edb GA	543	/*
	544	* die_nmi will return ONLY if NOTIFY_STOP happens..
	545	*/
1da177e4	546	die_nmi(regs, "NMI Watchdog detected LOCKUP");
748f2edb	547
1da177e4 LT	548	last_irq_sums[cpu] = sum;
	549	alert_counter[cpu] = 0;
	550	}
	551	if (nmi_perfctr_msr) {
	552	if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
	553	/*
	554	* P4 quirks:
	555	* - An overflown perfctr will assert its interrupt
	556	* until the OVF flag in its CCCR is cleared.
	557	* - LVTPC is masked on interrupt and must be
	558	* unmasked by the LVTPC handler.
	559	*/
	560	wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
	561	apic_write(APIC_LVTPC, APIC_DM_NMI);
	562	}
	563	else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
	564	/* Only P6 based Pentium M need to re-unmask
	565	* the apic vector but it doesn't hurt
	566	* other P6 variant */
	567	apic_write(APIC_LVTPC, APIC_DM_NMI);
	568	}
7fbb4f6e	569	write_watchdog_counter(NULL);
1da177e4 LT	570	}
	571	}
	572
	573	#ifdef CONFIG_SYSCTL
	574
	575	static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
	576	{
	577	unsigned char reason = get_nmi_reason();
	578	char buf[64];
	579
	580	if (!(reason & 0xc0)) {
	581	sprintf(buf, "NMI received for unknown reason %02x\n", reason);
	582	die_nmi(regs, buf);
	583	}
	584	return 0;
	585	}
	586
	587	/*
	588	* proc handler for /proc/sys/kernel/unknown_nmi_panic
	589	*/
	590	int proc_unknown_nmi_panic(ctl_table table, int write, struct file file,
	591	void __user buffer, size_t length, loff_t *ppos)
	592	{
	593	int old_state;
	594
	595	old_state = unknown_nmi_panic;
	596	proc_dointvec(table, write, file, buffer, length, ppos);
	597	if (!!old_state == !!unknown_nmi_panic)
	598	return 0;
	599
	600	if (unknown_nmi_panic) {
	601	if (reserve_lapic_nmi() < 0) {
	602	unknown_nmi_panic = 0;
	603	return -EBUSY;
	604	} else {
	605	set_nmi_callback(unknown_nmi_panic_callback);
	606	}
	607	} else {
	608	release_lapic_nmi();
	609	unset_nmi_callback();
	610	}
	611	return 0;
	612	}
	613
	614	#endif
	615
	616	EXPORT_SYMBOL(nmi_active);
	617	EXPORT_SYMBOL(nmi_watchdog);
	618	EXPORT_SYMBOL(reserve_lapic_nmi);
	619	EXPORT_SYMBOL(release_lapic_nmi);
	620	EXPORT_SYMBOL(disable_timer_nmi_watchdog);
	621	EXPORT_SYMBOL(enable_timer_nmi_watchdog);