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1 | /* |
2 | * machine_kexec.c - handle transition of Linux booting another kernel | |
3 | * Copyright (C) 2002-2005 Eric Biederman <ebiederm@xmission.com> | |
4 | * | |
5 | * This source code is licensed under the GNU General Public License, | |
6 | * Version 2. See the file COPYING for more details. | |
7 | */ | |
8 | ||
9 | #include <linux/mm.h> | |
10 | #include <linux/kexec.h> | |
11 | #include <linux/delay.h> | |
12 | #include <asm/pgtable.h> | |
13 | #include <asm/pgalloc.h> | |
14 | #include <asm/tlbflush.h> | |
15 | #include <asm/mmu_context.h> | |
16 | #include <asm/io.h> | |
17 | #include <asm/apic.h> | |
18 | #include <asm/cpufeature.h> | |
e7b47cca | 19 | #include <asm/desc.h> |
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20 | |
21 | static inline unsigned long read_cr3(void) | |
22 | { | |
23 | unsigned long cr3; | |
24 | asm volatile("movl %%cr3,%0": "=r"(cr3)); | |
25 | return cr3; | |
26 | } | |
27 | ||
28 | #define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE))) | |
29 | ||
30 | #define L0_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) | |
31 | #define L1_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) | |
32 | #define L2_ATTR (_PAGE_PRESENT) | |
33 | ||
34 | #define LEVEL0_SIZE (1UL << 12UL) | |
35 | ||
36 | #ifndef CONFIG_X86_PAE | |
37 | #define LEVEL1_SIZE (1UL << 22UL) | |
38 | static u32 pgtable_level1[1024] PAGE_ALIGNED; | |
39 | ||
40 | static void identity_map_page(unsigned long address) | |
41 | { | |
42 | unsigned long level1_index, level2_index; | |
43 | u32 *pgtable_level2; | |
44 | ||
45 | /* Find the current page table */ | |
46 | pgtable_level2 = __va(read_cr3()); | |
47 | ||
48 | /* Find the indexes of the physical address to identity map */ | |
49 | level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE; | |
50 | level2_index = address / LEVEL1_SIZE; | |
51 | ||
52 | /* Identity map the page table entry */ | |
53 | pgtable_level1[level1_index] = address | L0_ATTR; | |
54 | pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR; | |
55 | ||
56 | /* Flush the tlb so the new mapping takes effect. | |
57 | * Global tlb entries are not flushed but that is not an issue. | |
58 | */ | |
59 | load_cr3(pgtable_level2); | |
60 | } | |
61 | ||
62 | #else | |
63 | #define LEVEL1_SIZE (1UL << 21UL) | |
64 | #define LEVEL2_SIZE (1UL << 30UL) | |
65 | static u64 pgtable_level1[512] PAGE_ALIGNED; | |
66 | static u64 pgtable_level2[512] PAGE_ALIGNED; | |
67 | ||
68 | static void identity_map_page(unsigned long address) | |
69 | { | |
70 | unsigned long level1_index, level2_index, level3_index; | |
71 | u64 *pgtable_level3; | |
72 | ||
73 | /* Find the current page table */ | |
74 | pgtable_level3 = __va(read_cr3()); | |
75 | ||
76 | /* Find the indexes of the physical address to identity map */ | |
77 | level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE; | |
78 | level2_index = (address % LEVEL2_SIZE)/LEVEL1_SIZE; | |
79 | level3_index = address / LEVEL2_SIZE; | |
80 | ||
81 | /* Identity map the page table entry */ | |
82 | pgtable_level1[level1_index] = address | L0_ATTR; | |
83 | pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR; | |
72414d3f MS |
84 | set_64bit(&pgtable_level3[level3_index], |
85 | __pa(pgtable_level2) | L2_ATTR); | |
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86 | |
87 | /* Flush the tlb so the new mapping takes effect. | |
88 | * Global tlb entries are not flushed but that is not an issue. | |
89 | */ | |
90 | load_cr3(pgtable_level3); | |
91 | } | |
92 | #endif | |
93 | ||
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94 | static void set_idt(void *newidt, __u16 limit) |
95 | { | |
e7b47cca | 96 | struct Xgt_desc_struct curidt; |
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97 | |
98 | /* ia32 supports unaliged loads & stores */ | |
e7b47cca EB |
99 | curidt.size = limit; |
100 | curidt.address = (unsigned long)newidt; | |
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101 | |
102 | __asm__ __volatile__ ( | |
e7b47cca EB |
103 | "lidtl %0\n" |
104 | : : "m" (curidt) | |
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105 | ); |
106 | }; | |
107 | ||
108 | ||
109 | static void set_gdt(void *newgdt, __u16 limit) | |
110 | { | |
e7b47cca | 111 | struct Xgt_desc_struct curgdt; |
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112 | |
113 | /* ia32 supports unaligned loads & stores */ | |
e7b47cca EB |
114 | curgdt.size = limit; |
115 | curgdt.address = (unsigned long)newgdt; | |
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116 | |
117 | __asm__ __volatile__ ( | |
e7b47cca EB |
118 | "lgdtl %0\n" |
119 | : : "m" (curgdt) | |
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120 | ); |
121 | }; | |
122 | ||
123 | static void load_segments(void) | |
124 | { | |
125 | #define __STR(X) #X | |
126 | #define STR(X) __STR(X) | |
127 | ||
128 | __asm__ __volatile__ ( | |
129 | "\tljmp $"STR(__KERNEL_CS)",$1f\n" | |
130 | "\t1:\n" | |
131 | "\tmovl $"STR(__KERNEL_DS)",%eax\n" | |
132 | "\tmovl %eax,%ds\n" | |
133 | "\tmovl %eax,%es\n" | |
134 | "\tmovl %eax,%fs\n" | |
135 | "\tmovl %eax,%gs\n" | |
136 | "\tmovl %eax,%ss\n" | |
137 | ); | |
138 | #undef STR | |
139 | #undef __STR | |
140 | } | |
141 | ||
142 | typedef asmlinkage NORET_TYPE void (*relocate_new_kernel_t)( | |
72414d3f MS |
143 | unsigned long indirection_page, |
144 | unsigned long reboot_code_buffer, | |
145 | unsigned long start_address, | |
146 | unsigned int has_pae) ATTRIB_NORET; | |
5033cba0 EB |
147 | |
148 | const extern unsigned char relocate_new_kernel[]; | |
149 | extern void relocate_new_kernel_end(void); | |
150 | const extern unsigned int relocate_new_kernel_size; | |
151 | ||
152 | /* | |
153 | * A architecture hook called to validate the | |
154 | * proposed image and prepare the control pages | |
155 | * as needed. The pages for KEXEC_CONTROL_CODE_SIZE | |
156 | * have been allocated, but the segments have yet | |
157 | * been copied into the kernel. | |
158 | * | |
159 | * Do what every setup is needed on image and the | |
160 | * reboot code buffer to allow us to avoid allocations | |
161 | * later. | |
162 | * | |
163 | * Currently nothing. | |
164 | */ | |
165 | int machine_kexec_prepare(struct kimage *image) | |
166 | { | |
167 | return 0; | |
168 | } | |
169 | ||
170 | /* | |
171 | * Undo anything leftover by machine_kexec_prepare | |
172 | * when an image is freed. | |
173 | */ | |
174 | void machine_kexec_cleanup(struct kimage *image) | |
175 | { | |
176 | } | |
177 | ||
178 | /* | |
179 | * Do not allocate memory (or fail in any way) in machine_kexec(). | |
180 | * We are past the point of no return, committed to rebooting now. | |
181 | */ | |
182 | NORET_TYPE void machine_kexec(struct kimage *image) | |
183 | { | |
184 | unsigned long page_list; | |
185 | unsigned long reboot_code_buffer; | |
72414d3f | 186 | |
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187 | relocate_new_kernel_t rnk; |
188 | ||
189 | /* Interrupts aren't acceptable while we reboot */ | |
190 | local_irq_disable(); | |
191 | ||
192 | /* Compute some offsets */ | |
72414d3f MS |
193 | reboot_code_buffer = page_to_pfn(image->control_code_page) |
194 | << PAGE_SHIFT; | |
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195 | page_list = image->head; |
196 | ||
197 | /* Set up an identity mapping for the reboot_code_buffer */ | |
198 | identity_map_page(reboot_code_buffer); | |
199 | ||
200 | /* copy it out */ | |
72414d3f MS |
201 | memcpy((void *)reboot_code_buffer, relocate_new_kernel, |
202 | relocate_new_kernel_size); | |
5033cba0 EB |
203 | |
204 | /* The segment registers are funny things, they are | |
205 | * automatically loaded from a table, in memory wherever you | |
206 | * set them to a specific selector, but this table is never | |
207 | * accessed again you set the segment to a different selector. | |
208 | * | |
209 | * The more common model is are caches where the behide | |
210 | * the scenes work is done, but is also dropped at arbitrary | |
211 | * times. | |
212 | * | |
213 | * I take advantage of this here by force loading the | |
214 | * segments, before I zap the gdt with an invalid value. | |
215 | */ | |
216 | load_segments(); | |
217 | /* The gdt & idt are now invalid. | |
218 | * If you want to load them you must set up your own idt & gdt. | |
219 | */ | |
220 | set_gdt(phys_to_virt(0),0); | |
221 | set_idt(phys_to_virt(0),0); | |
222 | ||
223 | /* now call it */ | |
224 | rnk = (relocate_new_kernel_t) reboot_code_buffer; | |
225 | (*rnk)(page_list, reboot_code_buffer, image->start, cpu_has_pae); | |
226 | } |