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header cleaning: don't include smp_lock.h when not used
[linux-2.6-block.git] / arch / i386 / kernel / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
1da177e4
LT		 28#include <linux/mc146818rtc.h>
29#include <linux/compiler.h>
30#include <linux/acpi.h>
129f6946 31#include <linux/module.h>
1da177e4 32#include <linux/sysdev.h>
2d3fcc1c 33#include <linux/pci.h>
3b7d1921 34#include <linux/msi.h>
95d77884 35#include <linux/htirq.h>
7dfb7103 36#include <linux/freezer.h>
f26d6a2b 37#include <linux/kthread.h>
54d5d424 38
1da177e4
LT		 39#include <asm/io.h>
40#include <asm/smp.h>
41#include <asm/desc.h>
42#include <asm/timer.h>
306e440d 43#include <asm/i8259.h>
3e4ff115 44#include <asm/nmi.h>
2d3fcc1c 45#include <asm/msidef.h>
8b955b0d 46#include <asm/hypertransport.h>
1da177e4
LT		 47
48#include <mach_apic.h>
874c4fe3 49#include <mach_apicdef.h>
1da177e4
LT		 50
51#include "io_ports.h"
52
53int (*ioapic_renumber_irq)(int ioapic, int irq);
54atomic_t irq_mis_count;
55
fcfd636a
EB		 56/* Where if anywhere is the i8259 connect in external int mode */
57static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58
1da177e4 59static DEFINE_SPINLOCK(ioapic_lock);
0a1ad60d 60static DEFINE_SPINLOCK(vector_lock);
1da177e4 61
f9262c12
AK		 62int timer_over_8254 __initdata = 1;
63
1da177e4
LT		 64/*
65 * Is the SiS APIC rmw bug present ?
66 * -1 = don't know, 0 = no, 1 = yes
67 */
68int sis_apic_bug = -1;
69
70/*
71 * # of IRQ routing registers
72 */
73int nr_ioapic_registers[MAX_IO_APICS];
74
1a3f239d 75static int disable_timer_pin_1 __initdata;
66759a01 76
1da177e4
LT		 77/*
78 * Rough estimation of how many shared IRQs there are, can
79 * be changed anytime.
80 */
81#define MAX_PLUS_SHARED_IRQS NR_IRQS
82#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
83
84/*
85 * This is performance-critical, we want to do it O(1)
86 *
87 * the indexing order of this array favors 1:1 mappings
88 * between pins and IRQs.
89 */
90
91static struct irq_pin_list {
92 int apic, pin, next;
93} irq_2_pin[PIN_MAP_SIZE];
94
130fe05d
LT		 95struct io_apic {
96 unsigned int index;
97 unsigned int unused[3];
98 unsigned int data;
99};
100
101static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
102{
103 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
104 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
105}
106
107static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
108{
109 struct io_apic __iomem *io_apic = io_apic_base(apic);
110 writel(reg, &io_apic->index);
111 return readl(&io_apic->data);
112}
113
114static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
115{
116 struct io_apic __iomem *io_apic = io_apic_base(apic);
117 writel(reg, &io_apic->index);
118 writel(value, &io_apic->data);
119}
120
121/*
122 * Re-write a value: to be used for read-modify-write
123 * cycles where the read already set up the index register.
124 *
125 * Older SiS APIC requires we rewrite the index register
126 */
127static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
128{
cb468984 129 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
130fe05d
LT		 130 if (sis_apic_bug)
131 writel(reg, &io_apic->index);
132 writel(value, &io_apic->data);
133}
134
cf4c6a2f
AK		 135union entry_union {
136 struct { u32 w1, w2; };
137 struct IO_APIC_route_entry entry;
138};
139
140static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
141{
142 union entry_union eu;
143 unsigned long flags;
144 spin_lock_irqsave(&ioapic_lock, flags);
145 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
146 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
147 spin_unlock_irqrestore(&ioapic_lock, flags);
148 return eu.entry;
149}
150
f9dadfa7
LT		 151/*
152 * When we write a new IO APIC routing entry, we need to write the high
153 * word first! If the mask bit in the low word is clear, we will enable
154 * the interrupt, and we need to make sure the entry is fully populated
155 * before that happens.
156 */
d15512f4
AK		 157static void
158__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
cf4c6a2f 159{
cf4c6a2f
AK		 160 union entry_union eu;
161 eu.entry = e;
f9dadfa7
LT		 162 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
163 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
d15512f4
AK		 164}
165
166static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
167{
168 unsigned long flags;
169 spin_lock_irqsave(&ioapic_lock, flags);
170 __ioapic_write_entry(apic, pin, e);
f9dadfa7
LT		 171 spin_unlock_irqrestore(&ioapic_lock, flags);
172}
173
174/*
175 * When we mask an IO APIC routing entry, we need to write the low
176 * word first, in order to set the mask bit before we change the
177 * high bits!
178 */
179static void ioapic_mask_entry(int apic, int pin)
180{
181 unsigned long flags;
182 union entry_union eu = { .entry.mask = 1 };
183
cf4c6a2f
AK		 184 spin_lock_irqsave(&ioapic_lock, flags);
185 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
186 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
187 spin_unlock_irqrestore(&ioapic_lock, flags);
188}
189
1da177e4
LT		 190/*
191 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
192 * shared ISA-space IRQs, so we have to support them. We are super
193 * fast in the common case, and fast for shared ISA-space IRQs.
194 */
195static void add_pin_to_irq(unsigned int irq, int apic, int pin)
196{
197 static int first_free_entry = NR_IRQS;
198 struct irq_pin_list *entry = irq_2_pin + irq;
199
200 while (entry->next)
201 entry = irq_2_pin + entry->next;
202
203 if (entry->pin != -1) {
204 entry->next = first_free_entry;
205 entry = irq_2_pin + entry->next;
206 if (++first_free_entry >= PIN_MAP_SIZE)
207 panic("io_apic.c: whoops");
208 }
209 entry->apic = apic;
210 entry->pin = pin;
211}
212
213/*
214 * Reroute an IRQ to a different pin.
215 */
216static void __init replace_pin_at_irq(unsigned int irq,
217 int oldapic, int oldpin,
218 int newapic, int newpin)
219{
220 struct irq_pin_list *entry = irq_2_pin + irq;
221
222 while (1) {
223 if (entry->apic == oldapic && entry->pin == oldpin) {
224 entry->apic = newapic;
225 entry->pin = newpin;
226 }
227 if (!entry->next)
228 break;
229 entry = irq_2_pin + entry->next;
230 }
231}
232
233static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
234{
235 struct irq_pin_list *entry = irq_2_pin + irq;
236 unsigned int pin, reg;
237
238 for (;;) {
239 pin = entry->pin;
240 if (pin == -1)
241 break;
242 reg = io_apic_read(entry->apic, 0x10 + pin*2);
243 reg &= ~disable;
244 reg |= enable;
245 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
246 if (!entry->next)
247 break;
248 entry = irq_2_pin + entry->next;
249 }
250}
251
252/* mask = 1 */
253static void __mask_IO_APIC_irq (unsigned int irq)
254{
255 __modify_IO_APIC_irq(irq, 0x00010000, 0);
256}
257
258/* mask = 0 */
259static void __unmask_IO_APIC_irq (unsigned int irq)
260{
261 __modify_IO_APIC_irq(irq, 0, 0x00010000);
262}
263
264/* mask = 1, trigger = 0 */
265static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
266{
267 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
268}
269
270/* mask = 0, trigger = 1 */
271static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
272{
273 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
274}
275
276static void mask_IO_APIC_irq (unsigned int irq)
277{
278 unsigned long flags;
279
280 spin_lock_irqsave(&ioapic_lock, flags);
281 __mask_IO_APIC_irq(irq);
282 spin_unlock_irqrestore(&ioapic_lock, flags);
283}
284
285static void unmask_IO_APIC_irq (unsigned int irq)
286{
287 unsigned long flags;
288
289 spin_lock_irqsave(&ioapic_lock, flags);
290 __unmask_IO_APIC_irq(irq);
291 spin_unlock_irqrestore(&ioapic_lock, flags);
292}
293
294static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
295{
296 struct IO_APIC_route_entry entry;
1da177e4
LT		 297
298 /* Check delivery_mode to be sure we're not clearing an SMI pin */
cf4c6a2f 299 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 300 if (entry.delivery_mode == dest_SMI)
301 return;
302
303 /*
304 * Disable it in the IO-APIC irq-routing table:
305 */
f9dadfa7 306 ioapic_mask_entry(apic, pin);
1da177e4
LT		 307}
308
309static void clear_IO_APIC (void)
310{
311 int apic, pin;
312
313 for (apic = 0; apic < nr_ioapics; apic++)
314 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
315 clear_IO_APIC_pin(apic, pin);
316}
317
54d5d424 318#ifdef CONFIG_SMP
1da177e4
LT		 319static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
320{
321 unsigned long flags;
322 int pin;
323 struct irq_pin_list *entry = irq_2_pin + irq;
324 unsigned int apicid_value;
54d5d424 325 cpumask_t tmp;
1da177e4 326
54d5d424
AR		 327 cpus_and(tmp, cpumask, cpu_online_map);
328 if (cpus_empty(tmp))
329 tmp = TARGET_CPUS;
330
331 cpus_and(cpumask, tmp, CPU_MASK_ALL);
332
1da177e4
LT		 333 apicid_value = cpu_mask_to_apicid(cpumask);
334 /* Prepare to do the io_apic_write */
335 apicid_value = apicid_value << 24;
336 spin_lock_irqsave(&ioapic_lock, flags);
337 for (;;) {
338 pin = entry->pin;
339 if (pin == -1)
340 break;
341 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
342 if (!entry->next)
343 break;
344 entry = irq_2_pin + entry->next;
345 }
9f0a5ba5 346 irq_desc[irq].affinity = cpumask;
1da177e4
LT		 347 spin_unlock_irqrestore(&ioapic_lock, flags);
348}
349
350#if defined(CONFIG_IRQBALANCE)
351# include <asm/processor.h> /* kernel_thread() */
352# include <linux/kernel_stat.h> /* kstat */
353# include <linux/slab.h> /* kmalloc() */
354# include <linux/timer.h> /* time_after() */
355
1b61b910 356#ifdef CONFIG_BALANCED_IRQ_DEBUG
1da177e4
LT		 357# define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
358# define Dprintk(x...) do { TDprintk(x); } while (0)
359# else
360# define TDprintk(x...)
361# define Dprintk(x...)
362# endif
363
1da177e4 364#define IRQBALANCE_CHECK_ARCH -999
1b61b910
ZY		 365#define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
366#define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
367#define BALANCED_IRQ_MORE_DELTA (HZ/10)
368#define BALANCED_IRQ_LESS_DELTA (HZ)
369
370static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
371static int physical_balance __read_mostly;
372static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
1da177e4
LT		 373
374static struct irq_cpu_info {
375 unsigned long * last_irq;
376 unsigned long * irq_delta;
377 unsigned long irq;
378} irq_cpu_data[NR_CPUS];
379
380#define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
381#define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
382#define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
383
384#define IDLE_ENOUGH(cpu,now) \
385 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
386
387#define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
388
389#define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
390
1b61b910
ZY		 391static cpumask_t balance_irq_affinity[NR_IRQS] = {
392 [0 ... NR_IRQS-1] = CPU_MASK_ALL
393};
1da177e4 394
1b61b910
ZY		 395void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
396{
397 balance_irq_affinity[irq] = mask;
398}
1da177e4
LT		 399
400static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
401 unsigned long now, int direction)
402{
403 int search_idle = 1;
404 int cpu = curr_cpu;
405
406 goto inside;
407
408 do {
409 if (unlikely(cpu == curr_cpu))
410 search_idle = 0;
411inside:
412 if (direction == 1) {
413 cpu++;
414 if (cpu >= NR_CPUS)
415 cpu = 0;
416 } else {
417 cpu--;
418 if (cpu == -1)
419 cpu = NR_CPUS-1;
420 }
421 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
422 (search_idle && !IDLE_ENOUGH(cpu,now)));
423
424 return cpu;
425}
426
427static inline void balance_irq(int cpu, int irq)
428{
429 unsigned long now = jiffies;
430 cpumask_t allowed_mask;
431 unsigned int new_cpu;
432
433 if (irqbalance_disabled)
434 return;
435
1b61b910 436 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
1da177e4
LT		 437 new_cpu = move(cpu, allowed_mask, now, 1);
438 if (cpu != new_cpu) {
54d5d424 439 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
1da177e4
LT		 440 }
441}
442
443static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
444{
445 int i, j;
446 Dprintk("Rotating IRQs among CPUs.\n");
394e3902
AM		 447 for_each_online_cpu(i) {
448 for (j = 0; j < NR_IRQS; j++) {
1da177e4
LT		 449 if (!irq_desc[j].action)
450 continue;
451 /* Is it a significant load ? */
452 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
453 useful_load_threshold)
454 continue;
455 balance_irq(i, j);
456 }
457 }
458 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
459 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
460 return;
461}
462
463static void do_irq_balance(void)
464{
465 int i, j;
466 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
467 unsigned long move_this_load = 0;
468 int max_loaded = 0, min_loaded = 0;
469 int load;
470 unsigned long useful_load_threshold = balanced_irq_interval + 10;
471 int selected_irq;
472 int tmp_loaded, first_attempt = 1;
473 unsigned long tmp_cpu_irq;
474 unsigned long imbalance = 0;
475 cpumask_t allowed_mask, target_cpu_mask, tmp;
476
c8912599 477 for_each_possible_cpu(i) {
1da177e4
LT		 478 int package_index;
479 CPU_IRQ(i) = 0;
480 if (!cpu_online(i))
481 continue;
482 package_index = CPU_TO_PACKAGEINDEX(i);
483 for (j = 0; j < NR_IRQS; j++) {
484 unsigned long value_now, delta;
950f4427
TG		 485 /* Is this an active IRQ or balancing disabled ? */
486 if (!irq_desc[j].action || irq_balancing_disabled(j))
1da177e4
LT		 487 continue;
488 if ( package_index == i )
489 IRQ_DELTA(package_index,j) = 0;
490 /* Determine the total count per processor per IRQ */
491 value_now = (unsigned long) kstat_cpu(i).irqs[j];
492
493 /* Determine the activity per processor per IRQ */
494 delta = value_now - LAST_CPU_IRQ(i,j);
495
496 /* Update last_cpu_irq[][] for the next time */
497 LAST_CPU_IRQ(i,j) = value_now;
498
499 /* Ignore IRQs whose rate is less than the clock */
500 if (delta < useful_load_threshold)
501 continue;
502 /* update the load for the processor or package total */
503 IRQ_DELTA(package_index,j) += delta;
504
505 /* Keep track of the higher numbered sibling as well */
506 if (i != package_index)
507 CPU_IRQ(i) += delta;
508 /*
509 * We have sibling A and sibling B in the package
510 *
511 * cpu_irq[A] = load for cpu A + load for cpu B
512 * cpu_irq[B] = load for cpu B
513 */
514 CPU_IRQ(package_index) += delta;
515 }
516 }
517 /* Find the least loaded processor package */
394e3902 518 for_each_online_cpu(i) {
1da177e4
LT		 519 if (i != CPU_TO_PACKAGEINDEX(i))
520 continue;
521 if (min_cpu_irq > CPU_IRQ(i)) {
522 min_cpu_irq = CPU_IRQ(i);
523 min_loaded = i;
524 }
525 }
526 max_cpu_irq = ULONG_MAX;
527
528tryanothercpu:
529 /* Look for heaviest loaded processor.
530 * We may come back to get the next heaviest loaded processor.
531 * Skip processors with trivial loads.
532 */
533 tmp_cpu_irq = 0;
534 tmp_loaded = -1;
394e3902 535 for_each_online_cpu(i) {
1da177e4
LT		 536 if (i != CPU_TO_PACKAGEINDEX(i))
537 continue;
538 if (max_cpu_irq <= CPU_IRQ(i))
539 continue;
540 if (tmp_cpu_irq < CPU_IRQ(i)) {
541 tmp_cpu_irq = CPU_IRQ(i);
542 tmp_loaded = i;
543 }
544 }
545
546 if (tmp_loaded == -1) {
547 /* In the case of small number of heavy interrupt sources,
548 * loading some of the cpus too much. We use Ingo's original
549 * approach to rotate them around.
550 */
551 if (!first_attempt && imbalance >= useful_load_threshold) {
552 rotate_irqs_among_cpus(useful_load_threshold);
553 return;
554 }
555 goto not_worth_the_effort;
556 }
557
558 first_attempt = 0; /* heaviest search */
559 max_cpu_irq = tmp_cpu_irq; /* load */
560 max_loaded = tmp_loaded; /* processor */
561 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
562
563 Dprintk("max_loaded cpu = %d\n", max_loaded);
564 Dprintk("min_loaded cpu = %d\n", min_loaded);
565 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
566 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
567 Dprintk("load imbalance = %lu\n", imbalance);
568
569 /* if imbalance is less than approx 10% of max load, then
570 * observe diminishing returns action. - quit
571 */
572 if (imbalance < (max_cpu_irq >> 3)) {
573 Dprintk("Imbalance too trivial\n");
574 goto not_worth_the_effort;
575 }
576
577tryanotherirq:
578 /* if we select an IRQ to move that can't go where we want, then
579 * see if there is another one to try.
580 */
581 move_this_load = 0;
582 selected_irq = -1;
583 for (j = 0; j < NR_IRQS; j++) {
584 /* Is this an active IRQ? */
585 if (!irq_desc[j].action)
586 continue;
587 if (imbalance <= IRQ_DELTA(max_loaded,j))
588 continue;
589 /* Try to find the IRQ that is closest to the imbalance
590 * without going over.
591 */
592 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
593 move_this_load = IRQ_DELTA(max_loaded,j);
594 selected_irq = j;
595 }
596 }
597 if (selected_irq == -1) {
598 goto tryanothercpu;
599 }
600
601 imbalance = move_this_load;
602
603 /* For physical_balance case, we accumlated both load
604 * values in the one of the siblings cpu_irq[],
605 * to use the same code for physical and logical processors
606 * as much as possible.
607 *
608 * NOTE: the cpu_irq[] array holds the sum of the load for
609 * sibling A and sibling B in the slot for the lowest numbered
610 * sibling (A), _AND_ the load for sibling B in the slot for
611 * the higher numbered sibling.
612 *
613 * We seek the least loaded sibling by making the comparison
614 * (A+B)/2 vs B
615 */
616 load = CPU_IRQ(min_loaded) >> 1;
617 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
618 if (load > CPU_IRQ(j)) {
619 /* This won't change cpu_sibling_map[min_loaded] */
620 load = CPU_IRQ(j);
621 min_loaded = j;
622 }
623 }
624
1b61b910
ZY		 625 cpus_and(allowed_mask,
626 cpu_online_map,
627 balance_irq_affinity[selected_irq]);
1da177e4
LT		 628 target_cpu_mask = cpumask_of_cpu(min_loaded);
629 cpus_and(tmp, target_cpu_mask, allowed_mask);
630
631 if (!cpus_empty(tmp)) {
1da177e4
LT		 632
633 Dprintk("irq = %d moved to cpu = %d\n",
634 selected_irq, min_loaded);
635 /* mark for change destination */
54d5d424
AR		 636 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
637
1da177e4
LT		 638 /* Since we made a change, come back sooner to
639 * check for more variation.
640 */
641 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
642 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
643 return;
644 }
645 goto tryanotherirq;
646
647not_worth_the_effort:
648 /*
649 * if we did not find an IRQ to move, then adjust the time interval
650 * upward
651 */
652 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
653 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
654 Dprintk("IRQ worth rotating not found\n");
655 return;
656}
657
658static int balanced_irq(void *unused)
659{
660 int i;
661 unsigned long prev_balance_time = jiffies;
662 long time_remaining = balanced_irq_interval;
663
1da177e4
LT		 664 /* push everything to CPU 0 to give us a starting point. */
665 for (i = 0 ; i < NR_IRQS ; i++) {
cd916d31 666 irq_desc[i].pending_mask = cpumask_of_cpu(0);
54d5d424 667 set_pending_irq(i, cpumask_of_cpu(0));
1da177e4
LT		 668 }
669
670 for ( ; ; ) {
52e6e630 671 time_remaining = schedule_timeout_interruptible(time_remaining);
3e1d1d28 672 try_to_freeze();
1da177e4
LT		 673 if (time_after(jiffies,
674 prev_balance_time+balanced_irq_interval)) {
f3705136 675 preempt_disable();
1da177e4
LT		 676 do_irq_balance();
677 prev_balance_time = jiffies;
678 time_remaining = balanced_irq_interval;
f3705136 679 preempt_enable();
1da177e4
LT		 680 }
681 }
682 return 0;
683}
684
685static int __init balanced_irq_init(void)
686{
687 int i;
688 struct cpuinfo_x86 *c;
689 cpumask_t tmp;
690
691 cpus_shift_right(tmp, cpu_online_map, 2);
692 c = &boot_cpu_data;
693 /* When not overwritten by the command line ask subarchitecture. */
694 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
695 irqbalance_disabled = NO_BALANCE_IRQ;
696 if (irqbalance_disabled)
697 return 0;
698
699 /* disable irqbalance completely if there is only one processor online */
700 if (num_online_cpus() < 2) {
701 irqbalance_disabled = 1;
702 return 0;
703 }
704 /*
705 * Enable physical balance only if more than 1 physical processor
706 * is present
707 */
708 if (smp_num_siblings > 1 && !cpus_empty(tmp))
709 physical_balance = 1;
710
394e3902 711 for_each_online_cpu(i) {
1da177e4
LT		 712 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
713 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
714 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
715 printk(KERN_ERR "balanced_irq_init: out of memory");
716 goto failed;
717 }
718 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
719 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
720 }
721
722 printk(KERN_INFO "Starting balanced_irq\n");
f26d6a2b 723 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
1da177e4 724 return 0;
f26d6a2b 725 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
1da177e4 726failed:
c8912599 727 for_each_possible_cpu(i) {
4ae6673e 728 kfree(irq_cpu_data[i].irq_delta);
394e3902 729 irq_cpu_data[i].irq_delta = NULL;
4ae6673e 730 kfree(irq_cpu_data[i].last_irq);
394e3902 731 irq_cpu_data[i].last_irq = NULL;
1da177e4
LT		 732 }
733 return 0;
734}
735
c2481cc4 736int __devinit irqbalance_disable(char *str)
1da177e4
LT		 737{
738 irqbalance_disabled = 1;
9b41046c 739 return 1;
1da177e4
LT		 740}
741
742__setup("noirqbalance", irqbalance_disable);
743
1da177e4 744late_initcall(balanced_irq_init);
1da177e4 745#endif /* CONFIG_IRQBALANCE */
54d5d424 746#endif /* CONFIG_SMP */
1da177e4
LT		 747
748#ifndef CONFIG_SMP
749void fastcall send_IPI_self(int vector)
750{
751 unsigned int cfg;
752
753 /*
754 * Wait for idle.
755 */
756 apic_wait_icr_idle();
757 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
758 /*
759 * Send the IPI. The write to APIC_ICR fires this off.
760 */
761 apic_write_around(APIC_ICR, cfg);
762}
763#endif /* !CONFIG_SMP */
764
765
766/*
767 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
768 * specific CPU-side IRQs.
769 */
770
771#define MAX_PIRQS 8
772static int pirq_entries [MAX_PIRQS];
773static int pirqs_enabled;
774int skip_ioapic_setup;
775
776static int __init ioapic_setup(char *str)
777{
778 skip_ioapic_setup = 1;
779 return 1;
780}
781
782__setup("noapic", ioapic_setup);
783
784static int __init ioapic_pirq_setup(char *str)
785{
786 int i, max;
787 int ints[MAX_PIRQS+1];
788
789 get_options(str, ARRAY_SIZE(ints), ints);
790
791 for (i = 0; i < MAX_PIRQS; i++)
792 pirq_entries[i] = -1;
793
794 pirqs_enabled = 1;
795 apic_printk(APIC_VERBOSE, KERN_INFO
796 "PIRQ redirection, working around broken MP-BIOS.\n");
797 max = MAX_PIRQS;
798 if (ints[0] < MAX_PIRQS)
799 max = ints[0];
800
801 for (i = 0; i < max; i++) {
802 apic_printk(APIC_VERBOSE, KERN_DEBUG
803 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
804 /*
805 * PIRQs are mapped upside down, usually.
806 */
807 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
808 }
809 return 1;
810}
811
812__setup("pirq=", ioapic_pirq_setup);
813
814/*
815 * Find the IRQ entry number of a certain pin.
816 */
817static int find_irq_entry(int apic, int pin, int type)
818{
819 int i;
820
821 for (i = 0; i < mp_irq_entries; i++)
822 if (mp_irqs[i].mpc_irqtype == type &&
823 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
824 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
825 mp_irqs[i].mpc_dstirq == pin)
826 return i;
827
828 return -1;
829}
830
831/*
832 * Find the pin to which IRQ[irq] (ISA) is connected
833 */
fcfd636a 834static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 835{
836 int i;
837
838 for (i = 0; i < mp_irq_entries; i++) {
839 int lbus = mp_irqs[i].mpc_srcbus;
840
841 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
842 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
d7fb0271 843 mp_bus_id_to_type[lbus] == MP_BUS_MCA
1da177e4
LT		 844 ) &&
845 (mp_irqs[i].mpc_irqtype == type) &&
846 (mp_irqs[i].mpc_srcbusirq == irq))
847
848 return mp_irqs[i].mpc_dstirq;
849 }
850 return -1;
851}
852
fcfd636a
EB		 853static int __init find_isa_irq_apic(int irq, int type)
854{
855 int i;
856
857 for (i = 0; i < mp_irq_entries; i++) {
858 int lbus = mp_irqs[i].mpc_srcbus;
859
860 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
861 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
d7fb0271 862 mp_bus_id_to_type[lbus] == MP_BUS_MCA
fcfd636a
EB		 863 ) &&
864 (mp_irqs[i].mpc_irqtype == type) &&
865 (mp_irqs[i].mpc_srcbusirq == irq))
866 break;
867 }
868 if (i < mp_irq_entries) {
869 int apic;
870 for(apic = 0; apic < nr_ioapics; apic++) {
871 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
872 return apic;
873 }
874 }
875
876 return -1;
877}
878
1da177e4
LT		 879/*
880 * Find a specific PCI IRQ entry.
881 * Not an __init, possibly needed by modules
882 */
883static int pin_2_irq(int idx, int apic, int pin);
884
885int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
886{
887 int apic, i, best_guess = -1;
888
889 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
890 "slot:%d, pin:%d.\n", bus, slot, pin);
891 if (mp_bus_id_to_pci_bus[bus] == -1) {
892 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
893 return -1;
894 }
895 for (i = 0; i < mp_irq_entries; i++) {
896 int lbus = mp_irqs[i].mpc_srcbus;
897
898 for (apic = 0; apic < nr_ioapics; apic++)
899 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
900 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
901 break;
902
903 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
904 !mp_irqs[i].mpc_irqtype &&
905 (bus == lbus) &&
906 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
907 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
908
909 if (!(apic || IO_APIC_IRQ(irq)))
910 continue;
911
912 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
913 return irq;
914 /*
915 * Use the first all-but-pin matching entry as a
916 * best-guess fuzzy result for broken mptables.
917 */
918 if (best_guess < 0)
919 best_guess = irq;
920 }
921 }
922 return best_guess;
923}
129f6946 924EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1da177e4
LT		 925
926/*
927 * This function currently is only a helper for the i386 smp boot process where
928 * we need to reprogram the ioredtbls to cater for the cpus which have come online
929 * so mask in all cases should simply be TARGET_CPUS
930 */
54d5d424 931#ifdef CONFIG_SMP
1da177e4
LT		 932void __init setup_ioapic_dest(void)
933{
934 int pin, ioapic, irq, irq_entry;
935
936 if (skip_ioapic_setup == 1)
937 return;
938
939 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
940 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
941 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
942 if (irq_entry == -1)
943 continue;
944 irq = pin_2_irq(irq_entry, ioapic, pin);
945 set_ioapic_affinity_irq(irq, TARGET_CPUS);
946 }
947
948 }
949}
54d5d424 950#endif
1da177e4
LT		 951
952/*
953 * EISA Edge/Level control register, ELCR
954 */
955static int EISA_ELCR(unsigned int irq)
956{
957 if (irq < 16) {
958 unsigned int port = 0x4d0 + (irq >> 3);
959 return (inb(port) >> (irq & 7)) & 1;
960 }
961 apic_printk(APIC_VERBOSE, KERN_INFO
962 "Broken MPtable reports ISA irq %d\n", irq);
963 return 0;
964}
965
966/* EISA interrupts are always polarity zero and can be edge or level
967 * trigger depending on the ELCR value. If an interrupt is listed as
968 * EISA conforming in the MP table, that means its trigger type must
969 * be read in from the ELCR */
970
971#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
972#define default_EISA_polarity(idx) (0)
973
974/* ISA interrupts are always polarity zero edge triggered,
975 * when listed as conforming in the MP table. */
976
977#define default_ISA_trigger(idx) (0)
978#define default_ISA_polarity(idx) (0)
979
980/* PCI interrupts are always polarity one level triggered,
981 * when listed as conforming in the MP table. */
982
983#define default_PCI_trigger(idx) (1)
984#define default_PCI_polarity(idx) (1)
985
986/* MCA interrupts are always polarity zero level triggered,
987 * when listed as conforming in the MP table. */
988
989#define default_MCA_trigger(idx) (1)
990#define default_MCA_polarity(idx) (0)
991
1da177e4
LT		 992static int __init MPBIOS_polarity(int idx)
993{
994 int bus = mp_irqs[idx].mpc_srcbus;
995 int polarity;
996
997 /*
998 * Determine IRQ line polarity (high active or low active):
999 */
1000 switch (mp_irqs[idx].mpc_irqflag & 3)
1001 {
1002 case 0: /* conforms, ie. bus-type dependent polarity */
1003 {
1004 switch (mp_bus_id_to_type[bus])
1005 {
1006 case MP_BUS_ISA: /* ISA pin */
1007 {
1008 polarity = default_ISA_polarity(idx);
1009 break;
1010 }
1011 case MP_BUS_EISA: /* EISA pin */
1012 {
1013 polarity = default_EISA_polarity(idx);
1014 break;
1015 }
1016 case MP_BUS_PCI: /* PCI pin */
1017 {
1018 polarity = default_PCI_polarity(idx);
1019 break;
1020 }
1021 case MP_BUS_MCA: /* MCA pin */
1022 {
1023 polarity = default_MCA_polarity(idx);
1024 break;
1025 }
1da177e4
LT		 1026 default:
1027 {
1028 printk(KERN_WARNING "broken BIOS!!\n");
1029 polarity = 1;
1030 break;
1031 }
1032 }
1033 break;
1034 }
1035 case 1: /* high active */
1036 {
1037 polarity = 0;
1038 break;
1039 }
1040 case 2: /* reserved */
1041 {
1042 printk(KERN_WARNING "broken BIOS!!\n");
1043 polarity = 1;
1044 break;
1045 }
1046 case 3: /* low active */
1047 {
1048 polarity = 1;
1049 break;
1050 }
1051 default: /* invalid */
1052 {
1053 printk(KERN_WARNING "broken BIOS!!\n");
1054 polarity = 1;
1055 break;
1056 }
1057 }
1058 return polarity;
1059}
1060
1061static int MPBIOS_trigger(int idx)
1062{
1063 int bus = mp_irqs[idx].mpc_srcbus;
1064 int trigger;
1065
1066 /*
1067 * Determine IRQ trigger mode (edge or level sensitive):
1068 */
1069 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1070 {
1071 case 0: /* conforms, ie. bus-type dependent */
1072 {
1073 switch (mp_bus_id_to_type[bus])
1074 {
1075 case MP_BUS_ISA: /* ISA pin */
1076 {
1077 trigger = default_ISA_trigger(idx);
1078 break;
1079 }
1080 case MP_BUS_EISA: /* EISA pin */
1081 {
1082 trigger = default_EISA_trigger(idx);
1083 break;
1084 }
1085 case MP_BUS_PCI: /* PCI pin */
1086 {
1087 trigger = default_PCI_trigger(idx);
1088 break;
1089 }
1090 case MP_BUS_MCA: /* MCA pin */
1091 {
1092 trigger = default_MCA_trigger(idx);
1093 break;
1094 }
1da177e4
LT		 1095 default:
1096 {
1097 printk(KERN_WARNING "broken BIOS!!\n");
1098 trigger = 1;
1099 break;
1100 }
1101 }
1102 break;
1103 }
1104 case 1: /* edge */
1105 {
1106 trigger = 0;
1107 break;
1108 }
1109 case 2: /* reserved */
1110 {
1111 printk(KERN_WARNING "broken BIOS!!\n");
1112 trigger = 1;
1113 break;
1114 }
1115 case 3: /* level */
1116 {
1117 trigger = 1;
1118 break;
1119 }
1120 default: /* invalid */
1121 {
1122 printk(KERN_WARNING "broken BIOS!!\n");
1123 trigger = 0;
1124 break;
1125 }
1126 }
1127 return trigger;
1128}
1129
1130static inline int irq_polarity(int idx)
1131{
1132 return MPBIOS_polarity(idx);
1133}
1134
1135static inline int irq_trigger(int idx)
1136{
1137 return MPBIOS_trigger(idx);
1138}
1139
1140static int pin_2_irq(int idx, int apic, int pin)
1141{
1142 int irq, i;
1143 int bus = mp_irqs[idx].mpc_srcbus;
1144
1145 /*
1146 * Debugging check, we are in big trouble if this message pops up!
1147 */
1148 if (mp_irqs[idx].mpc_dstirq != pin)
1149 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1150
1151 switch (mp_bus_id_to_type[bus])
1152 {
1153 case MP_BUS_ISA: /* ISA pin */
1154 case MP_BUS_EISA:
1155 case MP_BUS_MCA:
1da177e4
LT		 1156 {
1157 irq = mp_irqs[idx].mpc_srcbusirq;
1158 break;
1159 }
1160 case MP_BUS_PCI: /* PCI pin */
1161 {
1162 /*
1163 * PCI IRQs are mapped in order
1164 */
1165 i = irq = 0;
1166 while (i < apic)
1167 irq += nr_ioapic_registers[i++];
1168 irq += pin;
1169
1170 /*
1171 * For MPS mode, so far only needed by ES7000 platform
1172 */
1173 if (ioapic_renumber_irq)
1174 irq = ioapic_renumber_irq(apic, irq);
1175
1176 break;
1177 }
1178 default:
1179 {
1180 printk(KERN_ERR "unknown bus type %d.\n",bus);
1181 irq = 0;
1182 break;
1183 }
1184 }
1185
1186 /*
1187 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1188 */
1189 if ((pin >= 16) && (pin <= 23)) {
1190 if (pirq_entries[pin-16] != -1) {
1191 if (!pirq_entries[pin-16]) {
1192 apic_printk(APIC_VERBOSE, KERN_DEBUG
1193 "disabling PIRQ%d\n", pin-16);
1194 } else {
1195 irq = pirq_entries[pin-16];
1196 apic_printk(APIC_VERBOSE, KERN_DEBUG
1197 "using PIRQ%d -> IRQ %d\n",
1198 pin-16, irq);
1199 }
1200 }
1201 }
1202 return irq;
1203}
1204
1205static inline int IO_APIC_irq_trigger(int irq)
1206{
1207 int apic, idx, pin;
1208
1209 for (apic = 0; apic < nr_ioapics; apic++) {
1210 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1211 idx = find_irq_entry(apic,pin,mp_INT);
1212 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1213 return irq_trigger(idx);
1214 }
1215 }
1216 /*
1217 * nonexistent IRQs are edge default
1218 */
1219 return 0;
1220}
1221
1222/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
7e95b593 1223static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1da177e4 1224
ace80ab7 1225static int __assign_irq_vector(int irq)
1da177e4 1226{
8339f000
EB		 1227 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1228 int vector, offset, i;
1da177e4 1229
ace80ab7 1230 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
0a1ad60d 1231
b940d22d
EB		 1232 if (irq_vector[irq] > 0)
1233 return irq_vector[irq];
ace80ab7 1234
0a1ad60d 1235 vector = current_vector;
8339f000
EB		 1236 offset = current_offset;
1237next:
1238 vector += 8;
1239 if (vector >= FIRST_SYSTEM_VECTOR) {
1240 offset = (offset + 1) % 8;
1241 vector = FIRST_DEVICE_VECTOR + offset;
1242 }
1243 if (vector == current_vector)
1244 return -ENOSPC;
1245 if (vector == SYSCALL_VECTOR)
1246 goto next;
1247 for (i = 0; i < NR_IRQ_VECTORS; i++)
1248 if (irq_vector[i] == vector)
1249 goto next;
1250
1251 current_vector = vector;
1252 current_offset = offset;
b940d22d 1253 irq_vector[irq] = vector;
ace80ab7
EB		 1254
1255 return vector;
1256}
0a1ad60d 1257
ace80ab7
EB		 1258static int assign_irq_vector(int irq)
1259{
1260 unsigned long flags;
1261 int vector;
1262
1263 spin_lock_irqsave(&vector_lock, flags);
1264 vector = __assign_irq_vector(irq);
26a3c49c 1265 spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 1266
0a1ad60d 1267 return vector;
1da177e4 1268}
f5b9ed7a 1269static struct irq_chip ioapic_chip;
1da177e4
LT		 1270
1271#define IOAPIC_AUTO -1
1272#define IOAPIC_EDGE 0
1273#define IOAPIC_LEVEL 1
1274
d1bef4ed 1275static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1da177e4 1276{
6ebcc00e
JB		 1277 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1278 trigger == IOAPIC_LEVEL)
a460e745
IM		 1279 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1280 handle_fasteoi_irq, "fasteoi");
d7e25f33 1281 else
a460e745
IM		 1282 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1283 handle_edge_irq, "edge");
ace80ab7 1284 set_intr_gate(vector, interrupt[irq]);
1da177e4
LT		 1285}
1286
1287static void __init setup_IO_APIC_irqs(void)
1288{
1289 struct IO_APIC_route_entry entry;
1290 int apic, pin, idx, irq, first_notcon = 1, vector;
1291 unsigned long flags;
1292
1293 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1294
1295 for (apic = 0; apic < nr_ioapics; apic++) {
1296 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1297
1298 /*
1299 * add it to the IO-APIC irq-routing table:
1300 */
1301 memset(&entry,0,sizeof(entry));
1302
1303 entry.delivery_mode = INT_DELIVERY_MODE;
1304 entry.dest_mode = INT_DEST_MODE;
1305 entry.mask = 0; /* enable IRQ */
1306 entry.dest.logical.logical_dest =
1307 cpu_mask_to_apicid(TARGET_CPUS);
1308
1309 idx = find_irq_entry(apic,pin,mp_INT);
1310 if (idx == -1) {
1311 if (first_notcon) {
1312 apic_printk(APIC_VERBOSE, KERN_DEBUG
1313 " IO-APIC (apicid-pin) %d-%d",
1314 mp_ioapics[apic].mpc_apicid,
1315 pin);
1316 first_notcon = 0;
1317 } else
1318 apic_printk(APIC_VERBOSE, ", %d-%d",
1319 mp_ioapics[apic].mpc_apicid, pin);
1320 continue;
1321 }
1322
1323 entry.trigger = irq_trigger(idx);
1324 entry.polarity = irq_polarity(idx);
1325
1326 if (irq_trigger(idx)) {
1327 entry.trigger = 1;
1328 entry.mask = 1;
1329 }
1330
1331 irq = pin_2_irq(idx, apic, pin);
1332 /*
1333 * skip adding the timer int on secondary nodes, which causes
1334 * a small but painful rift in the time-space continuum
1335 */
1336 if (multi_timer_check(apic, irq))
1337 continue;
1338 else
1339 add_pin_to_irq(irq, apic, pin);
1340
1341 if (!apic && !IO_APIC_IRQ(irq))
1342 continue;
1343
1344 if (IO_APIC_IRQ(irq)) {
1345 vector = assign_irq_vector(irq);
1346 entry.vector = vector;
1347 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1348
1349 if (!apic && (irq < 16))
1350 disable_8259A_irq(irq);
1351 }
1352 spin_lock_irqsave(&ioapic_lock, flags);
d15512f4 1353 __ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1354 spin_unlock_irqrestore(&ioapic_lock, flags);
1355 }
1356 }
1357
1358 if (!first_notcon)
1359 apic_printk(APIC_VERBOSE, " not connected.\n");
1360}
1361
1362/*
1363 * Set up the 8259A-master output pin:
1364 */
fcfd636a 1365static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1da177e4
LT		 1366{
1367 struct IO_APIC_route_entry entry;
1da177e4
LT		 1368
1369 memset(&entry,0,sizeof(entry));
1370
1371 disable_8259A_irq(0);
1372
1373 /* mask LVT0 */
1374 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1375
1376 /*
1377 * We use logical delivery to get the timer IRQ
1378 * to the first CPU.
1379 */
1380 entry.dest_mode = INT_DEST_MODE;
1381 entry.mask = 0; /* unmask IRQ now */
1382 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1383 entry.delivery_mode = INT_DELIVERY_MODE;
1384 entry.polarity = 0;
1385 entry.trigger = 0;
1386 entry.vector = vector;
1387
1388 /*
1389 * The timer IRQ doesn't have to know that behind the
1390 * scene we have a 8259A-master in AEOI mode ...
1391 */
f5b9ed7a
IM		 1392 irq_desc[0].chip = &ioapic_chip;
1393 set_irq_handler(0, handle_edge_irq);
1da177e4
LT		 1394
1395 /*
1396 * Add it to the IO-APIC irq-routing table:
1397 */
cf4c6a2f 1398 ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1399
1400 enable_8259A_irq(0);
1401}
1402
1da177e4
LT		 1403void __init print_IO_APIC(void)
1404{
1405 int apic, i;
1406 union IO_APIC_reg_00 reg_00;
1407 union IO_APIC_reg_01 reg_01;
1408 union IO_APIC_reg_02 reg_02;
1409 union IO_APIC_reg_03 reg_03;
1410 unsigned long flags;
1411
1412 if (apic_verbosity == APIC_QUIET)
1413 return;
1414
1415 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1416 for (i = 0; i < nr_ioapics; i++)
1417 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1418 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1419
1420 /*
1421 * We are a bit conservative about what we expect. We have to
1422 * know about every hardware change ASAP.
1423 */
1424 printk(KERN_INFO "testing the IO APIC.......................\n");
1425
1426 for (apic = 0; apic < nr_ioapics; apic++) {
1427
1428 spin_lock_irqsave(&ioapic_lock, flags);
1429 reg_00.raw = io_apic_read(apic, 0);
1430 reg_01.raw = io_apic_read(apic, 1);
1431 if (reg_01.bits.version >= 0x10)
1432 reg_02.raw = io_apic_read(apic, 2);
1433 if (reg_01.bits.version >= 0x20)
1434 reg_03.raw = io_apic_read(apic, 3);
1435 spin_unlock_irqrestore(&ioapic_lock, flags);
1436
1437 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1438 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1439 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1440 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1441 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1da177e4
LT		 1442
1443 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1444 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 1445
1446 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1447 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 1448
1449 /*
1450 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1451 * but the value of reg_02 is read as the previous read register
1452 * value, so ignore it if reg_02 == reg_01.
1453 */
1454 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1455 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1456 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 1457 }
1458
1459 /*
1460 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1461 * or reg_03, but the value of reg_0[23] is read as the previous read
1462 * register value, so ignore it if reg_03 == reg_0[12].
1463 */
1464 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1465 reg_03.raw != reg_01.raw) {
1466 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1467 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1da177e4
LT		 1468 }
1469
1470 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1471
1472 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1473 " Stat Dest Deli Vect: \n");
1474
1475 for (i = 0; i <= reg_01.bits.entries; i++) {
1476 struct IO_APIC_route_entry entry;
1477
cf4c6a2f 1478 entry = ioapic_read_entry(apic, i);
1da177e4
LT		 1479
1480 printk(KERN_DEBUG " %02x %03X %02X ",
1481 i,
1482 entry.dest.logical.logical_dest,
1483 entry.dest.physical.physical_dest
1484 );
1485
1486 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1487 entry.mask,
1488 entry.trigger,
1489 entry.irr,
1490 entry.polarity,
1491 entry.delivery_status,
1492 entry.dest_mode,
1493 entry.delivery_mode,
1494 entry.vector
1495 );
1496 }
1497 }
1da177e4
LT		 1498 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1499 for (i = 0; i < NR_IRQS; i++) {
1500 struct irq_pin_list *entry = irq_2_pin + i;
1501 if (entry->pin < 0)
1502 continue;
ace80ab7 1503 printk(KERN_DEBUG "IRQ%d ", i);
1da177e4
LT		 1504 for (;;) {
1505 printk("-> %d:%d", entry->apic, entry->pin);
1506 if (!entry->next)
1507 break;
1508 entry = irq_2_pin + entry->next;
1509 }
1510 printk("\n");
1511 }
1512
1513 printk(KERN_INFO ".................................... done.\n");
1514
1515 return;
1516}
1517
1518#if 0
1519
1520static void print_APIC_bitfield (int base)
1521{
1522 unsigned int v;
1523 int i, j;
1524
1525 if (apic_verbosity == APIC_QUIET)
1526 return;
1527
1528 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1529 for (i = 0; i < 8; i++) {
1530 v = apic_read(base + i*0x10);
1531 for (j = 0; j < 32; j++) {
1532 if (v & (1<<j))
1533 printk("1");
1534 else
1535 printk("0");
1536 }
1537 printk("\n");
1538 }
1539}
1540
1541void /*__init*/ print_local_APIC(void * dummy)
1542{
1543 unsigned int v, ver, maxlvt;
1544
1545 if (apic_verbosity == APIC_QUIET)
1546 return;
1547
1548 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1549 smp_processor_id(), hard_smp_processor_id());
1550 v = apic_read(APIC_ID);
1551 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1552 v = apic_read(APIC_LVR);
1553 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1554 ver = GET_APIC_VERSION(v);
e05d723f 1555 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1556
1557 v = apic_read(APIC_TASKPRI);
1558 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1559
1560 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1561 v = apic_read(APIC_ARBPRI);
1562 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1563 v & APIC_ARBPRI_MASK);
1564 v = apic_read(APIC_PROCPRI);
1565 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1566 }
1567
1568 v = apic_read(APIC_EOI);
1569 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1570 v = apic_read(APIC_RRR);
1571 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1572 v = apic_read(APIC_LDR);
1573 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1574 v = apic_read(APIC_DFR);
1575 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1576 v = apic_read(APIC_SPIV);
1577 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1578
1579 printk(KERN_DEBUG "... APIC ISR field:\n");
1580 print_APIC_bitfield(APIC_ISR);
1581 printk(KERN_DEBUG "... APIC TMR field:\n");
1582 print_APIC_bitfield(APIC_TMR);
1583 printk(KERN_DEBUG "... APIC IRR field:\n");
1584 print_APIC_bitfield(APIC_IRR);
1585
1586 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1587 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1588 apic_write(APIC_ESR, 0);
1589 v = apic_read(APIC_ESR);
1590 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1591 }
1592
1593 v = apic_read(APIC_ICR);
1594 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1595 v = apic_read(APIC_ICR2);
1596 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1597
1598 v = apic_read(APIC_LVTT);
1599 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1600
1601 if (maxlvt > 3) { /* PC is LVT#4. */
1602 v = apic_read(APIC_LVTPC);
1603 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1604 }
1605 v = apic_read(APIC_LVT0);
1606 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1607 v = apic_read(APIC_LVT1);
1608 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1609
1610 if (maxlvt > 2) { /* ERR is LVT#3. */
1611 v = apic_read(APIC_LVTERR);
1612 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1613 }
1614
1615 v = apic_read(APIC_TMICT);
1616 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1617 v = apic_read(APIC_TMCCT);
1618 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1619 v = apic_read(APIC_TDCR);
1620 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1621 printk("\n");
1622}
1623
1624void print_all_local_APICs (void)
1625{
1626 on_each_cpu(print_local_APIC, NULL, 1, 1);
1627}
1628
1629void /*__init*/ print_PIC(void)
1630{
1da177e4
LT		 1631 unsigned int v;
1632 unsigned long flags;
1633
1634 if (apic_verbosity == APIC_QUIET)
1635 return;
1636
1637 printk(KERN_DEBUG "\nprinting PIC contents\n");
1638
1639 spin_lock_irqsave(&i8259A_lock, flags);
1640
1641 v = inb(0xa1) << 8 | inb(0x21);
1642 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1643
1644 v = inb(0xa0) << 8 | inb(0x20);
1645 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1646
1647 outb(0x0b,0xa0);
1648 outb(0x0b,0x20);
1649 v = inb(0xa0) << 8 | inb(0x20);
1650 outb(0x0a,0xa0);
1651 outb(0x0a,0x20);
1652
1653 spin_unlock_irqrestore(&i8259A_lock, flags);
1654
1655 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1656
1657 v = inb(0x4d1) << 8 | inb(0x4d0);
1658 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1659}
1660
1661#endif /* 0 */
1662
1663static void __init enable_IO_APIC(void)
1664{
1665 union IO_APIC_reg_01 reg_01;
fcfd636a
EB		 1666 int i8259_apic, i8259_pin;
1667 int i, apic;
1da177e4
LT		 1668 unsigned long flags;
1669
1670 for (i = 0; i < PIN_MAP_SIZE; i++) {
1671 irq_2_pin[i].pin = -1;
1672 irq_2_pin[i].next = 0;
1673 }
1674 if (!pirqs_enabled)
1675 for (i = 0; i < MAX_PIRQS; i++)
1676 pirq_entries[i] = -1;
1677
1678 /*
1679 * The number of IO-APIC IRQ registers (== #pins):
1680 */
fcfd636a 1681 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1682 spin_lock_irqsave(&ioapic_lock, flags);
fcfd636a 1683 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1684 spin_unlock_irqrestore(&ioapic_lock, flags);
fcfd636a
EB		 1685 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1686 }
1687 for(apic = 0; apic < nr_ioapics; apic++) {
1688 int pin;
1689 /* See if any of the pins is in ExtINT mode */
1008fddc 1690 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
fcfd636a 1691 struct IO_APIC_route_entry entry;
cf4c6a2f 1692 entry = ioapic_read_entry(apic, pin);
fcfd636a
EB		 1693
1694
1695 /* If the interrupt line is enabled and in ExtInt mode
1696 * I have found the pin where the i8259 is connected.
1697 */
1698 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1699 ioapic_i8259.apic = apic;
1700 ioapic_i8259.pin = pin;
1701 goto found_i8259;
1702 }
1703 }
1704 }
1705 found_i8259:
1706 /* Look to see what if the MP table has reported the ExtINT */
1707 /* If we could not find the appropriate pin by looking at the ioapic
1708 * the i8259 probably is not connected the ioapic but give the
1709 * mptable a chance anyway.
1710 */
1711 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1712 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1713 /* Trust the MP table if nothing is setup in the hardware */
1714 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1715 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1716 ioapic_i8259.pin = i8259_pin;
1717 ioapic_i8259.apic = i8259_apic;
1718 }
1719 /* Complain if the MP table and the hardware disagree */
1720 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1721 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1722 {
1723 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1724 }
1725
1726 /*
1727 * Do not trust the IO-APIC being empty at bootup
1728 */
1729 clear_IO_APIC();
1730}
1731
1732/*
1733 * Not an __init, needed by the reboot code
1734 */
1735void disable_IO_APIC(void)
1736{
1737 /*
1738 * Clear the IO-APIC before rebooting:
1739 */
1740 clear_IO_APIC();
1741
650927ef 1742 /*
0b968d23 1743 * If the i8259 is routed through an IOAPIC
650927ef 1744 * Put that IOAPIC in virtual wire mode
0b968d23 1745 * so legacy interrupts can be delivered.
650927ef 1746 */
fcfd636a 1747 if (ioapic_i8259.pin != -1) {
650927ef 1748 struct IO_APIC_route_entry entry;
650927ef
EB		 1749
1750 memset(&entry, 0, sizeof(entry));
1751 entry.mask = 0; /* Enabled */
1752 entry.trigger = 0; /* Edge */
1753 entry.irr = 0;
1754 entry.polarity = 0; /* High */
1755 entry.delivery_status = 0;
1756 entry.dest_mode = 0; /* Physical */
fcfd636a 1757 entry.delivery_mode = dest_ExtINT; /* ExtInt */
650927ef 1758 entry.vector = 0;
76865c3f
VG		 1759 entry.dest.physical.physical_dest =
1760 GET_APIC_ID(apic_read(APIC_ID));
650927ef
EB		 1761
1762 /*
1763 * Add it to the IO-APIC irq-routing table:
1764 */
cf4c6a2f 1765 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
650927ef 1766 }
fcfd636a 1767 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1768}
1769
1770/*
1771 * function to set the IO-APIC physical IDs based on the
1772 * values stored in the MPC table.
1773 *
1774 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1775 */
1776
1777#ifndef CONFIG_X86_NUMAQ
1778static void __init setup_ioapic_ids_from_mpc(void)
1779{
1780 union IO_APIC_reg_00 reg_00;
1781 physid_mask_t phys_id_present_map;
1782 int apic;
1783 int i;
1784 unsigned char old_id;
1785 unsigned long flags;
1786
ca05fea6
NP		 1787 /*
1788 * Don't check I/O APIC IDs for xAPIC systems. They have
1789 * no meaning without the serial APIC bus.
1790 */
7c5c1e42
SL		 1791 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1792 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
ca05fea6 1793 return;
1da177e4
LT		 1794 /*
1795 * This is broken; anything with a real cpu count has to
1796 * circumvent this idiocy regardless.
1797 */
1798 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1799
1800 /*
1801 * Set the IOAPIC ID to the value stored in the MPC table.
1802 */
1803 for (apic = 0; apic < nr_ioapics; apic++) {
1804
1805 /* Read the register 0 value */
1806 spin_lock_irqsave(&ioapic_lock, flags);
1807 reg_00.raw = io_apic_read(apic, 0);
1808 spin_unlock_irqrestore(&ioapic_lock, flags);
1809
1810 old_id = mp_ioapics[apic].mpc_apicid;
1811
1812 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1813 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1814 apic, mp_ioapics[apic].mpc_apicid);
1815 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1816 reg_00.bits.ID);
1817 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1818 }
1819
1da177e4
LT		 1820 /*
1821 * Sanity check, is the ID really free? Every APIC in a
1822 * system must have a unique ID or we get lots of nice
1823 * 'stuck on smp_invalidate_needed IPI wait' messages.
1824 */
1825 if (check_apicid_used(phys_id_present_map,
1826 mp_ioapics[apic].mpc_apicid)) {
1827 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1828 apic, mp_ioapics[apic].mpc_apicid);
1829 for (i = 0; i < get_physical_broadcast(); i++)
1830 if (!physid_isset(i, phys_id_present_map))
1831 break;
1832 if (i >= get_physical_broadcast())
1833 panic("Max APIC ID exceeded!\n");
1834 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1835 i);
1836 physid_set(i, phys_id_present_map);
1837 mp_ioapics[apic].mpc_apicid = i;
1838 } else {
1839 physid_mask_t tmp;
1840 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1841 apic_printk(APIC_VERBOSE, "Setting %d in the "
1842 "phys_id_present_map\n",
1843 mp_ioapics[apic].mpc_apicid);
1844 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1845 }
1846
1847
1848 /*
1849 * We need to adjust the IRQ routing table
1850 * if the ID changed.
1851 */
1852 if (old_id != mp_ioapics[apic].mpc_apicid)
1853 for (i = 0; i < mp_irq_entries; i++)
1854 if (mp_irqs[i].mpc_dstapic == old_id)
1855 mp_irqs[i].mpc_dstapic
1856 = mp_ioapics[apic].mpc_apicid;
1857
1858 /*
1859 * Read the right value from the MPC table and
1860 * write it into the ID register.
1861 */
1862 apic_printk(APIC_VERBOSE, KERN_INFO
1863 "...changing IO-APIC physical APIC ID to %d ...",
1864 mp_ioapics[apic].mpc_apicid);
1865
1866 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1867 spin_lock_irqsave(&ioapic_lock, flags);
1868 io_apic_write(apic, 0, reg_00.raw);
1869 spin_unlock_irqrestore(&ioapic_lock, flags);
1870
1871 /*
1872 * Sanity check
1873 */
1874 spin_lock_irqsave(&ioapic_lock, flags);
1875 reg_00.raw = io_apic_read(apic, 0);
1876 spin_unlock_irqrestore(&ioapic_lock, flags);
1877 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1878 printk("could not set ID!\n");
1879 else
1880 apic_printk(APIC_VERBOSE, " ok.\n");
1881 }
1882}
1883#else
1884static void __init setup_ioapic_ids_from_mpc(void) { }
1885#endif
1886
7ce0bcfd 1887int no_timer_check __initdata;
8542b200
ZA		 1888
1889static int __init notimercheck(char *s)
1890{
1891 no_timer_check = 1;
1892 return 1;
1893}
1894__setup("no_timer_check", notimercheck);
1895
1da177e4
LT		 1896/*
1897 * There is a nasty bug in some older SMP boards, their mptable lies
1898 * about the timer IRQ. We do the following to work around the situation:
1899 *
1900 * - timer IRQ defaults to IO-APIC IRQ
1901 * - if this function detects that timer IRQs are defunct, then we fall
1902 * back to ISA timer IRQs
1903 */
8542b200 1904int __init timer_irq_works(void)
1da177e4
LT		 1905{
1906 unsigned long t1 = jiffies;
1907
8542b200
ZA		 1908 if (no_timer_check)
1909 return 1;
1910
1da177e4
LT		 1911 local_irq_enable();
1912 /* Let ten ticks pass... */
1913 mdelay((10 * 1000) / HZ);
1914
1915 /*
1916 * Expect a few ticks at least, to be sure some possible
1917 * glue logic does not lock up after one or two first
1918 * ticks in a non-ExtINT mode. Also the local APIC
1919 * might have cached one ExtINT interrupt. Finally, at
1920 * least one tick may be lost due to delays.
1921 */
1922 if (jiffies - t1 > 4)
1923 return 1;
1924
1925 return 0;
1926}
1927
1928/*
1929 * In the SMP+IOAPIC case it might happen that there are an unspecified
1930 * number of pending IRQ events unhandled. These cases are very rare,
1931 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1932 * better to do it this way as thus we do not have to be aware of
1933 * 'pending' interrupts in the IRQ path, except at this point.
1934 */
1935/*
1936 * Edge triggered needs to resend any interrupt
1937 * that was delayed but this is now handled in the device
1938 * independent code.
1939 */
1940
1941/*
f5b9ed7a
IM		 1942 * Startup quirk:
1943 *
1da177e4
LT		 1944 * Starting up a edge-triggered IO-APIC interrupt is
1945 * nasty - we need to make sure that we get the edge.
1946 * If it is already asserted for some reason, we need
1947 * return 1 to indicate that is was pending.
1948 *
1949 * This is not complete - we should be able to fake
1950 * an edge even if it isn't on the 8259A...
f5b9ed7a
IM		 1951 *
1952 * (We do this for level-triggered IRQs too - it cannot hurt.)
1da177e4 1953 */
f5b9ed7a 1954static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1955{
1956 int was_pending = 0;
1957 unsigned long flags;
1958
1959 spin_lock_irqsave(&ioapic_lock, flags);
1960 if (irq < 16) {
1961 disable_8259A_irq(irq);
1962 if (i8259A_irq_pending(irq))
1963 was_pending = 1;
1964 }
1965 __unmask_IO_APIC_irq(irq);
1966 spin_unlock_irqrestore(&ioapic_lock, flags);
1967
1968 return was_pending;
1969}
1970
f5b9ed7a 1971static void ack_ioapic_irq(unsigned int irq)
1da177e4 1972{
ace80ab7 1973 move_native_irq(irq);
1da177e4
LT		 1974 ack_APIC_irq();
1975}
1976
f5b9ed7a 1977static void ack_ioapic_quirk_irq(unsigned int irq)
1da177e4
LT		 1978{
1979 unsigned long v;
1980 int i;
1981
ace80ab7 1982 move_native_irq(irq);
1da177e4
LT		 1983/*
1984 * It appears there is an erratum which affects at least version 0x11
1985 * of I/O APIC (that's the 82093AA and cores integrated into various
1986 * chipsets). Under certain conditions a level-triggered interrupt is
1987 * erroneously delivered as edge-triggered one but the respective IRR
1988 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1989 * message but it will never arrive and further interrupts are blocked
1990 * from the source. The exact reason is so far unknown, but the
1991 * phenomenon was observed when two consecutive interrupt requests
1992 * from a given source get delivered to the same CPU and the source is
1993 * temporarily disabled in between.
1994 *
1995 * A workaround is to simulate an EOI message manually. We achieve it
1996 * by setting the trigger mode to edge and then to level when the edge
1997 * trigger mode gets detected in the TMR of a local APIC for a
1998 * level-triggered interrupt. We mask the source for the time of the
1999 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2000 * The idea is from Manfred Spraul. --macro
2001 */
b940d22d 2002 i = irq_vector[irq];
1da177e4
LT		 2003
2004 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2005
2006 ack_APIC_irq();
2007
2008 if (!(v & (1 << (i & 0x1f)))) {
2009 atomic_inc(&irq_mis_count);
2010 spin_lock(&ioapic_lock);
2011 __mask_and_edge_IO_APIC_irq(irq);
2012 __unmask_and_level_IO_APIC_irq(irq);
2013 spin_unlock(&ioapic_lock);
2014 }
2015}
2016
ace80ab7 2017static int ioapic_retrigger_irq(unsigned int irq)
1da177e4 2018{
b940d22d 2019 send_IPI_self(irq_vector[irq]);
c0ad90a3
IM		 2020
2021 return 1;
2022}
2023
f5b9ed7a
IM		 2024static struct irq_chip ioapic_chip __read_mostly = {
2025 .name = "IO-APIC",
ace80ab7
EB		 2026 .startup = startup_ioapic_irq,
2027 .mask = mask_IO_APIC_irq,
2028 .unmask = unmask_IO_APIC_irq,
2029 .ack = ack_ioapic_irq,
2030 .eoi = ack_ioapic_quirk_irq,
54d5d424 2031#ifdef CONFIG_SMP
ace80ab7 2032 .set_affinity = set_ioapic_affinity_irq,
54d5d424 2033#endif
ace80ab7 2034 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 2035};
2036
1da177e4
LT		 2037
2038static inline void init_IO_APIC_traps(void)
2039{
2040 int irq;
2041
2042 /*
2043 * NOTE! The local APIC isn't very good at handling
2044 * multiple interrupts at the same interrupt level.
2045 * As the interrupt level is determined by taking the
2046 * vector number and shifting that right by 4, we
2047 * want to spread these out a bit so that they don't
2048 * all fall in the same interrupt level.
2049 *
2050 * Also, we've got to be careful not to trash gate
2051 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2052 */
2053 for (irq = 0; irq < NR_IRQS ; irq++) {
2054 int tmp = irq;
b940d22d 2055 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1da177e4
LT		 2056 /*
2057 * Hmm.. We don't have an entry for this,
2058 * so default to an old-fashioned 8259
2059 * interrupt if we can..
2060 */
2061 if (irq < 16)
2062 make_8259A_irq(irq);
2063 else
2064 /* Strange. Oh, well.. */
f5b9ed7a 2065 irq_desc[irq].chip = &no_irq_chip;
1da177e4
LT		 2066 }
2067 }
2068}
2069
f5b9ed7a
IM		 2070/*
2071 * The local APIC irq-chip implementation:
2072 */
1da177e4 2073
f5b9ed7a
IM		 2074static void ack_apic(unsigned int irq)
2075{
2076 ack_APIC_irq();
1da177e4
LT		 2077}
2078
f5b9ed7a 2079static void mask_lapic_irq (unsigned int irq)
1da177e4
LT		 2080{
2081 unsigned long v;
2082
2083 v = apic_read(APIC_LVT0);
2084 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2085}
2086
f5b9ed7a 2087static void unmask_lapic_irq (unsigned int irq)
1da177e4 2088{
f5b9ed7a 2089 unsigned long v;
1da177e4 2090
f5b9ed7a
IM		 2091 v = apic_read(APIC_LVT0);
2092 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2093}
1da177e4 2094
f5b9ed7a
IM		 2095static struct irq_chip lapic_chip __read_mostly = {
2096 .name = "local-APIC-edge",
2097 .mask = mask_lapic_irq,
2098 .unmask = unmask_lapic_irq,
2099 .eoi = ack_apic,
1da177e4
LT		 2100};
2101
2102static void setup_nmi (void)
2103{
2104 /*
2105 * Dirty trick to enable the NMI watchdog ...
2106 * We put the 8259A master into AEOI mode and
2107 * unmask on all local APICs LVT0 as NMI.
2108 *
2109 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2110 * is from Maciej W. Rozycki - so we do not have to EOI from
2111 * the NMI handler or the timer interrupt.
2112 */
2113 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2114
2115 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2116
2117 apic_printk(APIC_VERBOSE, " done.\n");
2118}
2119
2120/*
2121 * This looks a bit hackish but it's about the only one way of sending
2122 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2123 * not support the ExtINT mode, unfortunately. We need to send these
2124 * cycles as some i82489DX-based boards have glue logic that keeps the
2125 * 8259A interrupt line asserted until INTA. --macro
2126 */
2127static inline void unlock_ExtINT_logic(void)
2128{
fcfd636a 2129 int apic, pin, i;
1da177e4
LT		 2130 struct IO_APIC_route_entry entry0, entry1;
2131 unsigned char save_control, save_freq_select;
1da177e4 2132
fcfd636a 2133 pin = find_isa_irq_pin(8, mp_INT);
956fb531
AB		 2134 if (pin == -1) {
2135 WARN_ON_ONCE(1);
2136 return;
2137 }
fcfd636a 2138 apic = find_isa_irq_apic(8, mp_INT);
956fb531
AB		 2139 if (apic == -1) {
2140 WARN_ON_ONCE(1);
1da177e4 2141 return;
956fb531 2142 }
1da177e4 2143
cf4c6a2f 2144 entry0 = ioapic_read_entry(apic, pin);
fcfd636a 2145 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 2146
2147 memset(&entry1, 0, sizeof(entry1));
2148
2149 entry1.dest_mode = 0; /* physical delivery */
2150 entry1.mask = 0; /* unmask IRQ now */
2151 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2152 entry1.delivery_mode = dest_ExtINT;
2153 entry1.polarity = entry0.polarity;
2154 entry1.trigger = 0;
2155 entry1.vector = 0;
2156
cf4c6a2f 2157 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 2158
2159 save_control = CMOS_READ(RTC_CONTROL);
2160 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2161 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2162 RTC_FREQ_SELECT);
2163 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2164
2165 i = 100;
2166 while (i-- > 0) {
2167 mdelay(10);
2168 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2169 i -= 10;
2170 }
2171
2172 CMOS_WRITE(save_control, RTC_CONTROL);
2173 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
fcfd636a 2174 clear_IO_APIC_pin(apic, pin);
1da177e4 2175
cf4c6a2f 2176 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 2177}
2178
e0c1e9bf
KM		 2179int timer_uses_ioapic_pin_0;
2180
1da177e4
LT		 2181/*
2182 * This code may look a bit paranoid, but it's supposed to cooperate with
2183 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2184 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2185 * fanatically on his truly buggy board.
2186 */
8542b200 2187static inline void __init check_timer(void)
1da177e4 2188{
fcfd636a 2189 int apic1, pin1, apic2, pin2;
1da177e4
LT		 2190 int vector;
2191
2192 /*
2193 * get/set the timer IRQ vector:
2194 */
2195 disable_8259A_irq(0);
2196 vector = assign_irq_vector(0);
2197 set_intr_gate(vector, interrupt[0]);
2198
2199 /*
2200 * Subtle, code in do_timer_interrupt() expects an AEOI
2201 * mode for the 8259A whenever interrupts are routed
2202 * through I/O APICs. Also IRQ0 has to be enabled in
2203 * the 8259A which implies the virtual wire has to be
2204 * disabled in the local APIC.
2205 */
2206 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2207 init_8259A(1);
2208 timer_ack = 1;
f9262c12
AK		 2209 if (timer_over_8254 > 0)
2210 enable_8259A_irq(0);
1da177e4 2211
fcfd636a
EB		 2212 pin1 = find_isa_irq_pin(0, mp_INT);
2213 apic1 = find_isa_irq_apic(0, mp_INT);
2214 pin2 = ioapic_i8259.pin;
2215 apic2 = ioapic_i8259.apic;
1da177e4 2216
e0c1e9bf
KM		 2217 if (pin1 == 0)
2218 timer_uses_ioapic_pin_0 = 1;
2219
fcfd636a
EB		 2220 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2221 vector, apic1, pin1, apic2, pin2);
1da177e4
LT		 2222
2223 if (pin1 != -1) {
2224 /*
2225 * Ok, does IRQ0 through the IOAPIC work?
2226 */
2227 unmask_IO_APIC_irq(0);
2228 if (timer_irq_works()) {
2229 if (nmi_watchdog == NMI_IO_APIC) {
2230 disable_8259A_irq(0);
2231 setup_nmi();
2232 enable_8259A_irq(0);
1da177e4 2233 }
66759a01
CE		 2234 if (disable_timer_pin_1 > 0)
2235 clear_IO_APIC_pin(0, pin1);
1da177e4
LT		 2236 return;
2237 }
fcfd636a
EB		 2238 clear_IO_APIC_pin(apic1, pin1);
2239 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2240 "IO-APIC\n");
1da177e4
LT		 2241 }
2242
2243 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2244 if (pin2 != -1) {
2245 printk("\n..... (found pin %d) ...", pin2);
2246 /*
2247 * legacy devices should be connected to IO APIC #0
2248 */
fcfd636a 2249 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1da177e4
LT		 2250 if (timer_irq_works()) {
2251 printk("works.\n");
2252 if (pin1 != -1)
fcfd636a 2253 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1da177e4 2254 else
fcfd636a 2255 add_pin_to_irq(0, apic2, pin2);
1da177e4
LT		 2256 if (nmi_watchdog == NMI_IO_APIC) {
2257 setup_nmi();
1da177e4
LT		 2258 }
2259 return;
2260 }
2261 /*
2262 * Cleanup, just in case ...
2263 */
fcfd636a 2264 clear_IO_APIC_pin(apic2, pin2);
1da177e4
LT		 2265 }
2266 printk(" failed.\n");
2267
2268 if (nmi_watchdog == NMI_IO_APIC) {
2269 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2270 nmi_watchdog = 0;
2271 }
2272
2273 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2274
2275 disable_8259A_irq(0);
a460e745 2276 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2e188938 2277 "fasteoi");
1da177e4
LT		 2278 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2279 enable_8259A_irq(0);
2280
2281 if (timer_irq_works()) {
2282 printk(" works.\n");
2283 return;
2284 }
2285 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2286 printk(" failed.\n");
2287
2288 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2289
2290 timer_ack = 0;
2291 init_8259A(0);
2292 make_8259A_irq(0);
2293 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2294
2295 unlock_ExtINT_logic();
2296
2297 if (timer_irq_works()) {
2298 printk(" works.\n");
2299 return;
2300 }
2301 printk(" failed :(.\n");
2302 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2303 "report. Then try booting with the 'noapic' option");
2304}
2305
2306/*
2307 *
2308 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2309 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2310 * Linux doesn't really care, as it's not actually used
2311 * for any interrupt handling anyway.
2312 */
2313#define PIC_IRQS (1 << PIC_CASCADE_IR)
2314
2315void __init setup_IO_APIC(void)
2316{
2317 enable_IO_APIC();
2318
2319 if (acpi_ioapic)
2320 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2321 else
2322 io_apic_irqs = ~PIC_IRQS;
2323
2324 printk("ENABLING IO-APIC IRQs\n");
2325
2326 /*
2327 * Set up IO-APIC IRQ routing.
2328 */
2329 if (!acpi_ioapic)
2330 setup_ioapic_ids_from_mpc();
2331 sync_Arb_IDs();
2332 setup_IO_APIC_irqs();
2333 init_IO_APIC_traps();
1e4c85f9 2334 check_timer();
1da177e4
LT		 2335 if (!acpi_ioapic)
2336 print_IO_APIC();
2337}
2338
f9262c12
AK		 2339static int __init setup_disable_8254_timer(char *s)
2340{
2341 timer_over_8254 = -1;
2342 return 1;
2343}
2344static int __init setup_enable_8254_timer(char *s)
2345{
2346 timer_over_8254 = 2;
2347 return 1;
2348}
2349
2350__setup("disable_8254_timer", setup_disable_8254_timer);
2351__setup("enable_8254_timer", setup_enable_8254_timer);
2352
1da177e4
LT		 2353/*
2354 * Called after all the initialization is done. If we didnt find any
2355 * APIC bugs then we can allow the modify fast path
2356 */
2357
2358static int __init io_apic_bug_finalize(void)
2359{
2360 if(sis_apic_bug == -1)
2361 sis_apic_bug = 0;
2362 return 0;
2363}
2364
2365late_initcall(io_apic_bug_finalize);
2366
2367struct sysfs_ioapic_data {
2368 struct sys_device dev;
2369 struct IO_APIC_route_entry entry[0];
2370};
2371static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2372
438510f6 2373static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 2374{
2375 struct IO_APIC_route_entry *entry;
2376 struct sysfs_ioapic_data *data;
1da177e4
LT		 2377 int i;
2378
2379 data = container_of(dev, struct sysfs_ioapic_data, dev);
2380 entry = data->entry;
cf4c6a2f
AK		 2381 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2382 entry[i] = ioapic_read_entry(dev->id, i);
1da177e4
LT		 2383
2384 return 0;
2385}
2386
2387static int ioapic_resume(struct sys_device *dev)
2388{
2389 struct IO_APIC_route_entry *entry;
2390 struct sysfs_ioapic_data *data;
2391 unsigned long flags;
2392 union IO_APIC_reg_00 reg_00;
2393 int i;
2394
2395 data = container_of(dev, struct sysfs_ioapic_data, dev);
2396 entry = data->entry;
2397
2398 spin_lock_irqsave(&ioapic_lock, flags);
2399 reg_00.raw = io_apic_read(dev->id, 0);
2400 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2401 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2402 io_apic_write(dev->id, 0, reg_00.raw);
2403 }
1da177e4 2404 spin_unlock_irqrestore(&ioapic_lock, flags);
cf4c6a2f
AK		 2405 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2406 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 2407
2408 return 0;
2409}
2410
2411static struct sysdev_class ioapic_sysdev_class = {
2412 set_kset_name("ioapic"),
2413 .suspend = ioapic_suspend,
2414 .resume = ioapic_resume,
2415};
2416
2417static int __init ioapic_init_sysfs(void)
2418{
2419 struct sys_device * dev;
2420 int i, size, error = 0;
2421
2422 error = sysdev_class_register(&ioapic_sysdev_class);
2423 if (error)
2424 return error;
2425
2426 for (i = 0; i < nr_ioapics; i++ ) {
2427 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2428 * sizeof(struct IO_APIC_route_entry);
2429 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2430 if (!mp_ioapic_data[i]) {
2431 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2432 continue;
2433 }
2434 memset(mp_ioapic_data[i], 0, size);
2435 dev = &mp_ioapic_data[i]->dev;
2436 dev->id = i;
2437 dev->cls = &ioapic_sysdev_class;
2438 error = sysdev_register(dev);
2439 if (error) {
2440 kfree(mp_ioapic_data[i]);
2441 mp_ioapic_data[i] = NULL;
2442 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2443 continue;
2444 }
2445 }
2446
2447 return 0;
2448}
2449
2450device_initcall(ioapic_init_sysfs);
2451
3fc471ed 2452/*
95d77884 2453 * Dynamic irq allocate and deallocation
3fc471ed
EB		 2454 */
2455int create_irq(void)
2456{
ace80ab7 2457 /* Allocate an unused irq */
306a22c2 2458 int irq, new, vector = 0;
3fc471ed 2459 unsigned long flags;
3fc471ed 2460
ace80ab7
EB		 2461 irq = -ENOSPC;
2462 spin_lock_irqsave(&vector_lock, flags);
2463 for (new = (NR_IRQS - 1); new >= 0; new--) {
2464 if (platform_legacy_irq(new))
2465 continue;
2466 if (irq_vector[new] != 0)
2467 continue;
2468 vector = __assign_irq_vector(new);
2469 if (likely(vector > 0))
2470 irq = new;
2471 break;
2472 }
2473 spin_unlock_irqrestore(&vector_lock, flags);
3fc471ed 2474
ace80ab7 2475 if (irq >= 0) {
3fc471ed 2476 set_intr_gate(vector, interrupt[irq]);
3fc471ed
EB		 2477 dynamic_irq_init(irq);
2478 }
2479 return irq;
2480}
2481
2482void destroy_irq(unsigned int irq)
2483{
2484 unsigned long flags;
3fc471ed
EB		 2485
2486 dynamic_irq_cleanup(irq);
2487
2488 spin_lock_irqsave(&vector_lock, flags);
3fc471ed
EB		 2489 irq_vector[irq] = 0;
2490 spin_unlock_irqrestore(&vector_lock, flags);
2491}
3fc471ed 2492
2d3fcc1c
EB		 2493/*
2494 * MSI mesage composition
2495 */
2496#ifdef CONFIG_PCI_MSI
3b7d1921 2497static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2d3fcc1c 2498{
2d3fcc1c
EB		 2499 int vector;
2500 unsigned dest;
2501
2502 vector = assign_irq_vector(irq);
2503 if (vector >= 0) {
2504 dest = cpu_mask_to_apicid(TARGET_CPUS);
2505
2506 msg->address_hi = MSI_ADDR_BASE_HI;
2507 msg->address_lo =
2508 MSI_ADDR_BASE_LO |
2509 ((INT_DEST_MODE == 0) ?
2510 MSI_ADDR_DEST_MODE_PHYSICAL:
2511 MSI_ADDR_DEST_MODE_LOGICAL) |
2512 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2513 MSI_ADDR_REDIRECTION_CPU:
2514 MSI_ADDR_REDIRECTION_LOWPRI) |
2515 MSI_ADDR_DEST_ID(dest);
2516
2517 msg->data =
2518 MSI_DATA_TRIGGER_EDGE |
2519 MSI_DATA_LEVEL_ASSERT |
2520 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2521 MSI_DATA_DELIVERY_FIXED:
2522 MSI_DATA_DELIVERY_LOWPRI) |
2523 MSI_DATA_VECTOR(vector);
2524 }
2525 return vector;
2526}
2527
3b7d1921
EB		 2528#ifdef CONFIG_SMP
2529static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2d3fcc1c 2530{
3b7d1921
EB		 2531 struct msi_msg msg;
2532 unsigned int dest;
2533 cpumask_t tmp;
2d3fcc1c 2534 int vector;
3b7d1921
EB		 2535
2536 cpus_and(tmp, mask, cpu_online_map);
2537 if (cpus_empty(tmp))
2538 tmp = TARGET_CPUS;
2d3fcc1c
EB		 2539
2540 vector = assign_irq_vector(irq);
3b7d1921
EB		 2541 if (vector < 0)
2542 return;
2d3fcc1c 2543
3b7d1921
EB		 2544 dest = cpu_mask_to_apicid(mask);
2545
2546 read_msi_msg(irq, &msg);
2547
2548 msg.data &= ~MSI_DATA_VECTOR_MASK;
2549 msg.data |= MSI_DATA_VECTOR(vector);
2550 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2551 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2552
2553 write_msi_msg(irq, &msg);
9f0a5ba5 2554 irq_desc[irq].affinity = mask;
2d3fcc1c 2555}
3b7d1921 2556#endif /* CONFIG_SMP */
2d3fcc1c 2557
3b7d1921
EB		 2558/*
2559 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2560 * which implement the MSI or MSI-X Capability Structure.
2561 */
2562static struct irq_chip msi_chip = {
2563 .name = "PCI-MSI",
2564 .unmask = unmask_msi_irq,
2565 .mask = mask_msi_irq,
2566 .ack = ack_ioapic_irq,
2567#ifdef CONFIG_SMP
2568 .set_affinity = set_msi_irq_affinity,
2569#endif
2570 .retrigger = ioapic_retrigger_irq,
2d3fcc1c
EB		 2571};
2572
f7feaca7 2573int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921
EB		 2574{
2575 struct msi_msg msg;
f7feaca7
EB		 2576 int irq, ret;
2577 irq = create_irq();
2578 if (irq < 0)
2579 return irq;
2580
3b7d1921 2581 ret = msi_compose_msg(dev, irq, &msg);
f7feaca7
EB		 2582 if (ret < 0) {
2583 destroy_irq(irq);
3b7d1921 2584 return ret;
f7feaca7 2585 }
3b7d1921 2586
7fe3730d 2587 set_irq_msi(irq, desc);
3b7d1921
EB		 2588 write_msi_msg(irq, &msg);
2589
a460e745
IM		 2590 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2591 "edge");
3b7d1921 2592
7fe3730d 2593 return 0;
3b7d1921
EB		 2594}
2595
2596void arch_teardown_msi_irq(unsigned int irq)
2597{
f7feaca7 2598 destroy_irq(irq);
3b7d1921
EB		 2599}
2600
2d3fcc1c
EB		 2601#endif /* CONFIG_PCI_MSI */
2602
8b955b0d
EB		 2603/*
2604 * Hypertransport interrupt support
2605 */
2606#ifdef CONFIG_HT_IRQ
2607
2608#ifdef CONFIG_SMP
2609
2610static void target_ht_irq(unsigned int irq, unsigned int dest)
2611{
ec68307c
EB		 2612 struct ht_irq_msg msg;
2613 fetch_ht_irq_msg(irq, &msg);
8b955b0d 2614
ec68307c
EB		 2615 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2616 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 2617
ec68307c
EB		 2618 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2619 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2620
ec68307c 2621 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 2622}
2623
2624static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2625{
2626 unsigned int dest;
2627 cpumask_t tmp;
2628
2629 cpus_and(tmp, mask, cpu_online_map);
2630 if (cpus_empty(tmp))
2631 tmp = TARGET_CPUS;
2632
2633 cpus_and(mask, tmp, CPU_MASK_ALL);
2634
2635 dest = cpu_mask_to_apicid(mask);
2636
2637 target_ht_irq(irq, dest);
9f0a5ba5 2638 irq_desc[irq].affinity = mask;
8b955b0d
EB		 2639}
2640#endif
2641
c37e108d 2642static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 2643 .name = "PCI-HT",
2644 .mask = mask_ht_irq,
2645 .unmask = unmask_ht_irq,
2646 .ack = ack_ioapic_irq,
2647#ifdef CONFIG_SMP
2648 .set_affinity = set_ht_irq_affinity,
2649#endif
2650 .retrigger = ioapic_retrigger_irq,
2651};
2652
2653int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2654{
2655 int vector;
2656
2657 vector = assign_irq_vector(irq);
2658 if (vector >= 0) {
ec68307c 2659 struct ht_irq_msg msg;
8b955b0d
EB		 2660 unsigned dest;
2661 cpumask_t tmp;
2662
2663 cpus_clear(tmp);
2664 cpu_set(vector >> 8, tmp);
2665 dest = cpu_mask_to_apicid(tmp);
2666
ec68307c 2667 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2668
ec68307c
EB		 2669 msg.address_lo =
2670 HT_IRQ_LOW_BASE |
8b955b0d
EB		 2671 HT_IRQ_LOW_DEST_ID(dest) |
2672 HT_IRQ_LOW_VECTOR(vector) |
2673 ((INT_DEST_MODE == 0) ?
2674 HT_IRQ_LOW_DM_PHYSICAL :
2675 HT_IRQ_LOW_DM_LOGICAL) |
2676 HT_IRQ_LOW_RQEOI_EDGE |
2677 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2678 HT_IRQ_LOW_MT_FIXED :
2679 HT_IRQ_LOW_MT_ARBITRATED) |
2680 HT_IRQ_LOW_IRQ_MASKED;
2681
ec68307c 2682 write_ht_irq_msg(irq, &msg);
8b955b0d 2683
a460e745
IM		 2684 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2685 handle_edge_irq, "edge");
8b955b0d
EB		 2686 }
2687 return vector;
2688}
2689#endif /* CONFIG_HT_IRQ */
2690
1da177e4
LT		 2691/* --------------------------------------------------------------------------
2692 ACPI-based IOAPIC Configuration
2693 -------------------------------------------------------------------------- */
2694
888ba6c6 2695#ifdef CONFIG_ACPI
1da177e4
LT		 2696
2697int __init io_apic_get_unique_id (int ioapic, int apic_id)
2698{
2699 union IO_APIC_reg_00 reg_00;
2700 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2701 physid_mask_t tmp;
2702 unsigned long flags;
2703 int i = 0;
2704
2705 /*
2706 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2707 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2708 * supports up to 16 on one shared APIC bus.
2709 *
2710 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2711 * advantage of new APIC bus architecture.
2712 */
2713
2714 if (physids_empty(apic_id_map))
2715 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2716
2717 spin_lock_irqsave(&ioapic_lock, flags);
2718 reg_00.raw = io_apic_read(ioapic, 0);
2719 spin_unlock_irqrestore(&ioapic_lock, flags);
2720
2721 if (apic_id >= get_physical_broadcast()) {
2722 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2723 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2724 apic_id = reg_00.bits.ID;
2725 }
2726
2727 /*
2728 * Every APIC in a system must have a unique ID or we get lots of nice
2729 * 'stuck on smp_invalidate_needed IPI wait' messages.
2730 */
2731 if (check_apicid_used(apic_id_map, apic_id)) {
2732
2733 for (i = 0; i < get_physical_broadcast(); i++) {
2734 if (!check_apicid_used(apic_id_map, i))
2735 break;
2736 }
2737
2738 if (i == get_physical_broadcast())
2739 panic("Max apic_id exceeded!\n");
2740
2741 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2742 "trying %d\n", ioapic, apic_id, i);
2743
2744 apic_id = i;
2745 }
2746
2747 tmp = apicid_to_cpu_present(apic_id);
2748 physids_or(apic_id_map, apic_id_map, tmp);
2749
2750 if (reg_00.bits.ID != apic_id) {
2751 reg_00.bits.ID = apic_id;
2752
2753 spin_lock_irqsave(&ioapic_lock, flags);
2754 io_apic_write(ioapic, 0, reg_00.raw);
2755 reg_00.raw = io_apic_read(ioapic, 0);
2756 spin_unlock_irqrestore(&ioapic_lock, flags);
2757
2758 /* Sanity check */
6070f9ec
AD		 2759 if (reg_00.bits.ID != apic_id) {
2760 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2761 return -1;
2762 }
1da177e4
LT		 2763 }
2764
2765 apic_printk(APIC_VERBOSE, KERN_INFO
2766 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2767
2768 return apic_id;
2769}
2770
2771
2772int __init io_apic_get_version (int ioapic)
2773{
2774 union IO_APIC_reg_01 reg_01;
2775 unsigned long flags;
2776
2777 spin_lock_irqsave(&ioapic_lock, flags);
2778 reg_01.raw = io_apic_read(ioapic, 1);
2779 spin_unlock_irqrestore(&ioapic_lock, flags);
2780
2781 return reg_01.bits.version;
2782}
2783
2784
2785int __init io_apic_get_redir_entries (int ioapic)
2786{
2787 union IO_APIC_reg_01 reg_01;
2788 unsigned long flags;
2789
2790 spin_lock_irqsave(&ioapic_lock, flags);
2791 reg_01.raw = io_apic_read(ioapic, 1);
2792 spin_unlock_irqrestore(&ioapic_lock, flags);
2793
2794 return reg_01.bits.entries;
2795}
2796
2797
2798int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2799{
2800 struct IO_APIC_route_entry entry;
2801 unsigned long flags;
2802
2803 if (!IO_APIC_IRQ(irq)) {
2804 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2805 ioapic);
2806 return -EINVAL;
2807 }
2808
2809 /*
2810 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2811 * Note that we mask (disable) IRQs now -- these get enabled when the
2812 * corresponding device driver registers for this IRQ.
2813 */
2814
2815 memset(&entry,0,sizeof(entry));
2816
2817 entry.delivery_mode = INT_DELIVERY_MODE;
2818 entry.dest_mode = INT_DEST_MODE;
2819 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2820 entry.trigger = edge_level;
2821 entry.polarity = active_high_low;
2822 entry.mask = 1;
2823
2824 /*
2825 * IRQs < 16 are already in the irq_2_pin[] map
2826 */
2827 if (irq >= 16)
2828 add_pin_to_irq(irq, ioapic, pin);
2829
2830 entry.vector = assign_irq_vector(irq);
2831
2832 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2833 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2834 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2835 edge_level, active_high_low);
2836
2837 ioapic_register_intr(irq, entry.vector, edge_level);
2838
2839 if (!ioapic && (irq < 16))
2840 disable_8259A_irq(irq);
2841
2842 spin_lock_irqsave(&ioapic_lock, flags);
d15512f4 2843 __ioapic_write_entry(ioapic, pin, entry);
1da177e4
LT		 2844 spin_unlock_irqrestore(&ioapic_lock, flags);
2845
2846 return 0;
2847}
2848
888ba6c6 2849#endif /* CONFIG_ACPI */
1a3f239d
RR		 2850
2851static int __init parse_disable_timer_pin_1(char *arg)
2852{
2853 disable_timer_pin_1 = 1;
2854 return 0;
2855}
2856early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2857
2858static int __init parse_enable_timer_pin_1(char *arg)
2859{
2860 disable_timer_pin_1 = -1;
2861 return 0;
2862}
2863early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2864
2865static int __init parse_noapic(char *arg)
2866{
2867 /* disable IO-APIC */
2868 disable_ioapic_setup();
2869 return 0;
2870}
2871early_param("noapic", parse_noapic);
Linux 6.x block layer and io_uring tree(s)