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Pull define-node-cleanup into release branch
[linux-2.6-block.git] / arch / i386 / kernel / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
28#include <linux/config.h>
29#include <linux/smp_lock.h>
30#include <linux/mc146818rtc.h>
31#include <linux/compiler.h>
32#include <linux/acpi.h>
129f6946 33#include <linux/module.h>
1da177e4 34#include <linux/sysdev.h>
54d5d424 35
1da177e4
LT		 36#include <asm/io.h>
37#include <asm/smp.h>
38#include <asm/desc.h>
39#include <asm/timer.h>
306e440d 40#include <asm/i8259.h>
1da177e4
LT		 41
42#include <mach_apic.h>
43
44#include "io_ports.h"
45
46int (*ioapic_renumber_irq)(int ioapic, int irq);
47atomic_t irq_mis_count;
48
49static DEFINE_SPINLOCK(ioapic_lock);
50
51/*
52 * Is the SiS APIC rmw bug present ?
53 * -1 = don't know, 0 = no, 1 = yes
54 */
55int sis_apic_bug = -1;
56
57/*
58 * # of IRQ routing registers
59 */
60int nr_ioapic_registers[MAX_IO_APICS];
61
66759a01
CE		 62int disable_timer_pin_1 __initdata;
63
1da177e4
LT		 64/*
65 * Rough estimation of how many shared IRQs there are, can
66 * be changed anytime.
67 */
68#define MAX_PLUS_SHARED_IRQS NR_IRQS
69#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
70
71/*
72 * This is performance-critical, we want to do it O(1)
73 *
74 * the indexing order of this array favors 1:1 mappings
75 * between pins and IRQs.
76 */
77
78static struct irq_pin_list {
79 int apic, pin, next;
80} irq_2_pin[PIN_MAP_SIZE];
81
6c231b7b 82int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
1da177e4
LT		 83#ifdef CONFIG_PCI_MSI
84#define vector_to_irq(vector) \
85 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
86#else
87#define vector_to_irq(vector) (vector)
88#endif
89
90/*
91 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
92 * shared ISA-space IRQs, so we have to support them. We are super
93 * fast in the common case, and fast for shared ISA-space IRQs.
94 */
95static void add_pin_to_irq(unsigned int irq, int apic, int pin)
96{
97 static int first_free_entry = NR_IRQS;
98 struct irq_pin_list *entry = irq_2_pin + irq;
99
100 while (entry->next)
101 entry = irq_2_pin + entry->next;
102
103 if (entry->pin != -1) {
104 entry->next = first_free_entry;
105 entry = irq_2_pin + entry->next;
106 if (++first_free_entry >= PIN_MAP_SIZE)
107 panic("io_apic.c: whoops");
108 }
109 entry->apic = apic;
110 entry->pin = pin;
111}
112
113/*
114 * Reroute an IRQ to a different pin.
115 */
116static void __init replace_pin_at_irq(unsigned int irq,
117 int oldapic, int oldpin,
118 int newapic, int newpin)
119{
120 struct irq_pin_list *entry = irq_2_pin + irq;
121
122 while (1) {
123 if (entry->apic == oldapic && entry->pin == oldpin) {
124 entry->apic = newapic;
125 entry->pin = newpin;
126 }
127 if (!entry->next)
128 break;
129 entry = irq_2_pin + entry->next;
130 }
131}
132
133static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
134{
135 struct irq_pin_list *entry = irq_2_pin + irq;
136 unsigned int pin, reg;
137
138 for (;;) {
139 pin = entry->pin;
140 if (pin == -1)
141 break;
142 reg = io_apic_read(entry->apic, 0x10 + pin*2);
143 reg &= ~disable;
144 reg |= enable;
145 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
146 if (!entry->next)
147 break;
148 entry = irq_2_pin + entry->next;
149 }
150}
151
152/* mask = 1 */
153static void __mask_IO_APIC_irq (unsigned int irq)
154{
155 __modify_IO_APIC_irq(irq, 0x00010000, 0);
156}
157
158/* mask = 0 */
159static void __unmask_IO_APIC_irq (unsigned int irq)
160{
161 __modify_IO_APIC_irq(irq, 0, 0x00010000);
162}
163
164/* mask = 1, trigger = 0 */
165static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
166{
167 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
168}
169
170/* mask = 0, trigger = 1 */
171static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
172{
173 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
174}
175
176static void mask_IO_APIC_irq (unsigned int irq)
177{
178 unsigned long flags;
179
180 spin_lock_irqsave(&ioapic_lock, flags);
181 __mask_IO_APIC_irq(irq);
182 spin_unlock_irqrestore(&ioapic_lock, flags);
183}
184
185static void unmask_IO_APIC_irq (unsigned int irq)
186{
187 unsigned long flags;
188
189 spin_lock_irqsave(&ioapic_lock, flags);
190 __unmask_IO_APIC_irq(irq);
191 spin_unlock_irqrestore(&ioapic_lock, flags);
192}
193
194static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
195{
196 struct IO_APIC_route_entry entry;
197 unsigned long flags;
198
199 /* Check delivery_mode to be sure we're not clearing an SMI pin */
200 spin_lock_irqsave(&ioapic_lock, flags);
201 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
202 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
203 spin_unlock_irqrestore(&ioapic_lock, flags);
204 if (entry.delivery_mode == dest_SMI)
205 return;
206
207 /*
208 * Disable it in the IO-APIC irq-routing table:
209 */
210 memset(&entry, 0, sizeof(entry));
211 entry.mask = 1;
212 spin_lock_irqsave(&ioapic_lock, flags);
213 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
214 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
215 spin_unlock_irqrestore(&ioapic_lock, flags);
216}
217
218static void clear_IO_APIC (void)
219{
220 int apic, pin;
221
222 for (apic = 0; apic < nr_ioapics; apic++)
223 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
224 clear_IO_APIC_pin(apic, pin);
225}
226
54d5d424 227#ifdef CONFIG_SMP
1da177e4
LT		 228static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
229{
230 unsigned long flags;
231 int pin;
232 struct irq_pin_list *entry = irq_2_pin + irq;
233 unsigned int apicid_value;
54d5d424 234 cpumask_t tmp;
1da177e4 235
54d5d424
AR		 236 cpus_and(tmp, cpumask, cpu_online_map);
237 if (cpus_empty(tmp))
238 tmp = TARGET_CPUS;
239
240 cpus_and(cpumask, tmp, CPU_MASK_ALL);
241
1da177e4
LT		 242 apicid_value = cpu_mask_to_apicid(cpumask);
243 /* Prepare to do the io_apic_write */
244 apicid_value = apicid_value << 24;
245 spin_lock_irqsave(&ioapic_lock, flags);
246 for (;;) {
247 pin = entry->pin;
248 if (pin == -1)
249 break;
250 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
251 if (!entry->next)
252 break;
253 entry = irq_2_pin + entry->next;
254 }
54d5d424 255 set_irq_info(irq, cpumask);
1da177e4
LT		 256 spin_unlock_irqrestore(&ioapic_lock, flags);
257}
258
259#if defined(CONFIG_IRQBALANCE)
260# include <asm/processor.h> /* kernel_thread() */
261# include <linux/kernel_stat.h> /* kstat */
262# include <linux/slab.h> /* kmalloc() */
263# include <linux/timer.h> /* time_after() */
264
265# ifdef CONFIG_BALANCED_IRQ_DEBUG
266# define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
267# define Dprintk(x...) do { TDprintk(x); } while (0)
268# else
269# define TDprintk(x...)
270# define Dprintk(x...)
271# endif
272
1da177e4
LT		 273
274#define IRQBALANCE_CHECK_ARCH -999
275static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
276static int physical_balance = 0;
277
278static struct irq_cpu_info {
279 unsigned long * last_irq;
280 unsigned long * irq_delta;
281 unsigned long irq;
282} irq_cpu_data[NR_CPUS];
283
284#define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
285#define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
286#define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
287
288#define IDLE_ENOUGH(cpu,now) \
289 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
290
291#define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
292
293#define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
294
295#define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
296#define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
297#define BALANCED_IRQ_MORE_DELTA (HZ/10)
298#define BALANCED_IRQ_LESS_DELTA (HZ)
299
300static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
301
302static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
303 unsigned long now, int direction)
304{
305 int search_idle = 1;
306 int cpu = curr_cpu;
307
308 goto inside;
309
310 do {
311 if (unlikely(cpu == curr_cpu))
312 search_idle = 0;
313inside:
314 if (direction == 1) {
315 cpu++;
316 if (cpu >= NR_CPUS)
317 cpu = 0;
318 } else {
319 cpu--;
320 if (cpu == -1)
321 cpu = NR_CPUS-1;
322 }
323 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
324 (search_idle && !IDLE_ENOUGH(cpu,now)));
325
326 return cpu;
327}
328
329static inline void balance_irq(int cpu, int irq)
330{
331 unsigned long now = jiffies;
332 cpumask_t allowed_mask;
333 unsigned int new_cpu;
334
335 if (irqbalance_disabled)
336 return;
337
338 cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
339 new_cpu = move(cpu, allowed_mask, now, 1);
340 if (cpu != new_cpu) {
54d5d424 341 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
1da177e4
LT		 342 }
343}
344
345static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
346{
347 int i, j;
348 Dprintk("Rotating IRQs among CPUs.\n");
349 for (i = 0; i < NR_CPUS; i++) {
350 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
351 if (!irq_desc[j].action)
352 continue;
353 /* Is it a significant load ? */
354 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
355 useful_load_threshold)
356 continue;
357 balance_irq(i, j);
358 }
359 }
360 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
361 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
362 return;
363}
364
365static void do_irq_balance(void)
366{
367 int i, j;
368 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
369 unsigned long move_this_load = 0;
370 int max_loaded = 0, min_loaded = 0;
371 int load;
372 unsigned long useful_load_threshold = balanced_irq_interval + 10;
373 int selected_irq;
374 int tmp_loaded, first_attempt = 1;
375 unsigned long tmp_cpu_irq;
376 unsigned long imbalance = 0;
377 cpumask_t allowed_mask, target_cpu_mask, tmp;
378
379 for (i = 0; i < NR_CPUS; i++) {
380 int package_index;
381 CPU_IRQ(i) = 0;
382 if (!cpu_online(i))
383 continue;
384 package_index = CPU_TO_PACKAGEINDEX(i);
385 for (j = 0; j < NR_IRQS; j++) {
386 unsigned long value_now, delta;
387 /* Is this an active IRQ? */
388 if (!irq_desc[j].action)
389 continue;
390 if ( package_index == i )
391 IRQ_DELTA(package_index,j) = 0;
392 /* Determine the total count per processor per IRQ */
393 value_now = (unsigned long) kstat_cpu(i).irqs[j];
394
395 /* Determine the activity per processor per IRQ */
396 delta = value_now - LAST_CPU_IRQ(i,j);
397
398 /* Update last_cpu_irq[][] for the next time */
399 LAST_CPU_IRQ(i,j) = value_now;
400
401 /* Ignore IRQs whose rate is less than the clock */
402 if (delta < useful_load_threshold)
403 continue;
404 /* update the load for the processor or package total */
405 IRQ_DELTA(package_index,j) += delta;
406
407 /* Keep track of the higher numbered sibling as well */
408 if (i != package_index)
409 CPU_IRQ(i) += delta;
410 /*
411 * We have sibling A and sibling B in the package
412 *
413 * cpu_irq[A] = load for cpu A + load for cpu B
414 * cpu_irq[B] = load for cpu B
415 */
416 CPU_IRQ(package_index) += delta;
417 }
418 }
419 /* Find the least loaded processor package */
420 for (i = 0; i < NR_CPUS; i++) {
421 if (!cpu_online(i))
422 continue;
423 if (i != CPU_TO_PACKAGEINDEX(i))
424 continue;
425 if (min_cpu_irq > CPU_IRQ(i)) {
426 min_cpu_irq = CPU_IRQ(i);
427 min_loaded = i;
428 }
429 }
430 max_cpu_irq = ULONG_MAX;
431
432tryanothercpu:
433 /* Look for heaviest loaded processor.
434 * We may come back to get the next heaviest loaded processor.
435 * Skip processors with trivial loads.
436 */
437 tmp_cpu_irq = 0;
438 tmp_loaded = -1;
439 for (i = 0; i < NR_CPUS; i++) {
440 if (!cpu_online(i))
441 continue;
442 if (i != CPU_TO_PACKAGEINDEX(i))
443 continue;
444 if (max_cpu_irq <= CPU_IRQ(i))
445 continue;
446 if (tmp_cpu_irq < CPU_IRQ(i)) {
447 tmp_cpu_irq = CPU_IRQ(i);
448 tmp_loaded = i;
449 }
450 }
451
452 if (tmp_loaded == -1) {
453 /* In the case of small number of heavy interrupt sources,
454 * loading some of the cpus too much. We use Ingo's original
455 * approach to rotate them around.
456 */
457 if (!first_attempt && imbalance >= useful_load_threshold) {
458 rotate_irqs_among_cpus(useful_load_threshold);
459 return;
460 }
461 goto not_worth_the_effort;
462 }
463
464 first_attempt = 0; /* heaviest search */
465 max_cpu_irq = tmp_cpu_irq; /* load */
466 max_loaded = tmp_loaded; /* processor */
467 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
468
469 Dprintk("max_loaded cpu = %d\n", max_loaded);
470 Dprintk("min_loaded cpu = %d\n", min_loaded);
471 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
472 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
473 Dprintk("load imbalance = %lu\n", imbalance);
474
475 /* if imbalance is less than approx 10% of max load, then
476 * observe diminishing returns action. - quit
477 */
478 if (imbalance < (max_cpu_irq >> 3)) {
479 Dprintk("Imbalance too trivial\n");
480 goto not_worth_the_effort;
481 }
482
483tryanotherirq:
484 /* if we select an IRQ to move that can't go where we want, then
485 * see if there is another one to try.
486 */
487 move_this_load = 0;
488 selected_irq = -1;
489 for (j = 0; j < NR_IRQS; j++) {
490 /* Is this an active IRQ? */
491 if (!irq_desc[j].action)
492 continue;
493 if (imbalance <= IRQ_DELTA(max_loaded,j))
494 continue;
495 /* Try to find the IRQ that is closest to the imbalance
496 * without going over.
497 */
498 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
499 move_this_load = IRQ_DELTA(max_loaded,j);
500 selected_irq = j;
501 }
502 }
503 if (selected_irq == -1) {
504 goto tryanothercpu;
505 }
506
507 imbalance = move_this_load;
508
509 /* For physical_balance case, we accumlated both load
510 * values in the one of the siblings cpu_irq[],
511 * to use the same code for physical and logical processors
512 * as much as possible.
513 *
514 * NOTE: the cpu_irq[] array holds the sum of the load for
515 * sibling A and sibling B in the slot for the lowest numbered
516 * sibling (A), _AND_ the load for sibling B in the slot for
517 * the higher numbered sibling.
518 *
519 * We seek the least loaded sibling by making the comparison
520 * (A+B)/2 vs B
521 */
522 load = CPU_IRQ(min_loaded) >> 1;
523 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
524 if (load > CPU_IRQ(j)) {
525 /* This won't change cpu_sibling_map[min_loaded] */
526 load = CPU_IRQ(j);
527 min_loaded = j;
528 }
529 }
530
531 cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
532 target_cpu_mask = cpumask_of_cpu(min_loaded);
533 cpus_and(tmp, target_cpu_mask, allowed_mask);
534
535 if (!cpus_empty(tmp)) {
1da177e4
LT		 536
537 Dprintk("irq = %d moved to cpu = %d\n",
538 selected_irq, min_loaded);
539 /* mark for change destination */
54d5d424
AR		 540 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
541
1da177e4
LT		 542 /* Since we made a change, come back sooner to
543 * check for more variation.
544 */
545 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
546 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
547 return;
548 }
549 goto tryanotherirq;
550
551not_worth_the_effort:
552 /*
553 * if we did not find an IRQ to move, then adjust the time interval
554 * upward
555 */
556 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
557 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
558 Dprintk("IRQ worth rotating not found\n");
559 return;
560}
561
562static int balanced_irq(void *unused)
563{
564 int i;
565 unsigned long prev_balance_time = jiffies;
566 long time_remaining = balanced_irq_interval;
567
568 daemonize("kirqd");
569
570 /* push everything to CPU 0 to give us a starting point. */
571 for (i = 0 ; i < NR_IRQS ; i++) {
54d5d424
AR		 572 pending_irq_cpumask[i] = cpumask_of_cpu(0);
573 set_pending_irq(i, cpumask_of_cpu(0));
1da177e4
LT		 574 }
575
576 for ( ; ; ) {
52e6e630 577 time_remaining = schedule_timeout_interruptible(time_remaining);
3e1d1d28 578 try_to_freeze();
1da177e4
LT		 579 if (time_after(jiffies,
580 prev_balance_time+balanced_irq_interval)) {
f3705136 581 preempt_disable();
1da177e4
LT		 582 do_irq_balance();
583 prev_balance_time = jiffies;
584 time_remaining = balanced_irq_interval;
f3705136 585 preempt_enable();
1da177e4
LT		 586 }
587 }
588 return 0;
589}
590
591static int __init balanced_irq_init(void)
592{
593 int i;
594 struct cpuinfo_x86 *c;
595 cpumask_t tmp;
596
597 cpus_shift_right(tmp, cpu_online_map, 2);
598 c = &boot_cpu_data;
599 /* When not overwritten by the command line ask subarchitecture. */
600 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
601 irqbalance_disabled = NO_BALANCE_IRQ;
602 if (irqbalance_disabled)
603 return 0;
604
605 /* disable irqbalance completely if there is only one processor online */
606 if (num_online_cpus() < 2) {
607 irqbalance_disabled = 1;
608 return 0;
609 }
610 /*
611 * Enable physical balance only if more than 1 physical processor
612 * is present
613 */
614 if (smp_num_siblings > 1 && !cpus_empty(tmp))
615 physical_balance = 1;
616
617 for (i = 0; i < NR_CPUS; i++) {
618 if (!cpu_online(i))
619 continue;
620 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
621 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
622 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
623 printk(KERN_ERR "balanced_irq_init: out of memory");
624 goto failed;
625 }
626 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
627 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
628 }
629
630 printk(KERN_INFO "Starting balanced_irq\n");
631 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
632 return 0;
633 else
634 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
635failed:
636 for (i = 0; i < NR_CPUS; i++) {
4ae6673e
JJ		 637 kfree(irq_cpu_data[i].irq_delta);
638 kfree(irq_cpu_data[i].last_irq);
1da177e4
LT		 639 }
640 return 0;
641}
642
643int __init irqbalance_disable(char *str)
644{
645 irqbalance_disabled = 1;
646 return 0;
647}
648
649__setup("noirqbalance", irqbalance_disable);
650
1da177e4 651late_initcall(balanced_irq_init);
1da177e4 652#endif /* CONFIG_IRQBALANCE */
54d5d424 653#endif /* CONFIG_SMP */
1da177e4
LT		 654
655#ifndef CONFIG_SMP
656void fastcall send_IPI_self(int vector)
657{
658 unsigned int cfg;
659
660 /*
661 * Wait for idle.
662 */
663 apic_wait_icr_idle();
664 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
665 /*
666 * Send the IPI. The write to APIC_ICR fires this off.
667 */
668 apic_write_around(APIC_ICR, cfg);
669}
670#endif /* !CONFIG_SMP */
671
672
673/*
674 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
675 * specific CPU-side IRQs.
676 */
677
678#define MAX_PIRQS 8
679static int pirq_entries [MAX_PIRQS];
680static int pirqs_enabled;
681int skip_ioapic_setup;
682
683static int __init ioapic_setup(char *str)
684{
685 skip_ioapic_setup = 1;
686 return 1;
687}
688
689__setup("noapic", ioapic_setup);
690
691static int __init ioapic_pirq_setup(char *str)
692{
693 int i, max;
694 int ints[MAX_PIRQS+1];
695
696 get_options(str, ARRAY_SIZE(ints), ints);
697
698 for (i = 0; i < MAX_PIRQS; i++)
699 pirq_entries[i] = -1;
700
701 pirqs_enabled = 1;
702 apic_printk(APIC_VERBOSE, KERN_INFO
703 "PIRQ redirection, working around broken MP-BIOS.\n");
704 max = MAX_PIRQS;
705 if (ints[0] < MAX_PIRQS)
706 max = ints[0];
707
708 for (i = 0; i < max; i++) {
709 apic_printk(APIC_VERBOSE, KERN_DEBUG
710 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
711 /*
712 * PIRQs are mapped upside down, usually.
713 */
714 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
715 }
716 return 1;
717}
718
719__setup("pirq=", ioapic_pirq_setup);
720
721/*
722 * Find the IRQ entry number of a certain pin.
723 */
724static int find_irq_entry(int apic, int pin, int type)
725{
726 int i;
727
728 for (i = 0; i < mp_irq_entries; i++)
729 if (mp_irqs[i].mpc_irqtype == type &&
730 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
731 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
732 mp_irqs[i].mpc_dstirq == pin)
733 return i;
734
735 return -1;
736}
737
738/*
739 * Find the pin to which IRQ[irq] (ISA) is connected
740 */
741static int find_isa_irq_pin(int irq, int type)
742{
743 int i;
744
745 for (i = 0; i < mp_irq_entries; i++) {
746 int lbus = mp_irqs[i].mpc_srcbus;
747
748 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
749 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
750 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
751 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
752 ) &&
753 (mp_irqs[i].mpc_irqtype == type) &&
754 (mp_irqs[i].mpc_srcbusirq == irq))
755
756 return mp_irqs[i].mpc_dstirq;
757 }
758 return -1;
759}
760
761/*
762 * Find a specific PCI IRQ entry.
763 * Not an __init, possibly needed by modules
764 */
765static int pin_2_irq(int idx, int apic, int pin);
766
767int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
768{
769 int apic, i, best_guess = -1;
770
771 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
772 "slot:%d, pin:%d.\n", bus, slot, pin);
773 if (mp_bus_id_to_pci_bus[bus] == -1) {
774 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
775 return -1;
776 }
777 for (i = 0; i < mp_irq_entries; i++) {
778 int lbus = mp_irqs[i].mpc_srcbus;
779
780 for (apic = 0; apic < nr_ioapics; apic++)
781 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
782 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
783 break;
784
785 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
786 !mp_irqs[i].mpc_irqtype &&
787 (bus == lbus) &&
788 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
789 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
790
791 if (!(apic || IO_APIC_IRQ(irq)))
792 continue;
793
794 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
795 return irq;
796 /*
797 * Use the first all-but-pin matching entry as a
798 * best-guess fuzzy result for broken mptables.
799 */
800 if (best_guess < 0)
801 best_guess = irq;
802 }
803 }
804 return best_guess;
805}
129f6946 806EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1da177e4
LT		 807
808/*
809 * This function currently is only a helper for the i386 smp boot process where
810 * we need to reprogram the ioredtbls to cater for the cpus which have come online
811 * so mask in all cases should simply be TARGET_CPUS
812 */
54d5d424 813#ifdef CONFIG_SMP
1da177e4
LT		 814void __init setup_ioapic_dest(void)
815{
816 int pin, ioapic, irq, irq_entry;
817
818 if (skip_ioapic_setup == 1)
819 return;
820
821 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
822 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
823 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
824 if (irq_entry == -1)
825 continue;
826 irq = pin_2_irq(irq_entry, ioapic, pin);
827 set_ioapic_affinity_irq(irq, TARGET_CPUS);
828 }
829
830 }
831}
54d5d424 832#endif
1da177e4
LT		 833
834/*
835 * EISA Edge/Level control register, ELCR
836 */
837static int EISA_ELCR(unsigned int irq)
838{
839 if (irq < 16) {
840 unsigned int port = 0x4d0 + (irq >> 3);
841 return (inb(port) >> (irq & 7)) & 1;
842 }
843 apic_printk(APIC_VERBOSE, KERN_INFO
844 "Broken MPtable reports ISA irq %d\n", irq);
845 return 0;
846}
847
848/* EISA interrupts are always polarity zero and can be edge or level
849 * trigger depending on the ELCR value. If an interrupt is listed as
850 * EISA conforming in the MP table, that means its trigger type must
851 * be read in from the ELCR */
852
853#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
854#define default_EISA_polarity(idx) (0)
855
856/* ISA interrupts are always polarity zero edge triggered,
857 * when listed as conforming in the MP table. */
858
859#define default_ISA_trigger(idx) (0)
860#define default_ISA_polarity(idx) (0)
861
862/* PCI interrupts are always polarity one level triggered,
863 * when listed as conforming in the MP table. */
864
865#define default_PCI_trigger(idx) (1)
866#define default_PCI_polarity(idx) (1)
867
868/* MCA interrupts are always polarity zero level triggered,
869 * when listed as conforming in the MP table. */
870
871#define default_MCA_trigger(idx) (1)
872#define default_MCA_polarity(idx) (0)
873
874/* NEC98 interrupts are always polarity zero edge triggered,
875 * when listed as conforming in the MP table. */
876
877#define default_NEC98_trigger(idx) (0)
878#define default_NEC98_polarity(idx) (0)
879
880static int __init MPBIOS_polarity(int idx)
881{
882 int bus = mp_irqs[idx].mpc_srcbus;
883 int polarity;
884
885 /*
886 * Determine IRQ line polarity (high active or low active):
887 */
888 switch (mp_irqs[idx].mpc_irqflag & 3)
889 {
890 case 0: /* conforms, ie. bus-type dependent polarity */
891 {
892 switch (mp_bus_id_to_type[bus])
893 {
894 case MP_BUS_ISA: /* ISA pin */
895 {
896 polarity = default_ISA_polarity(idx);
897 break;
898 }
899 case MP_BUS_EISA: /* EISA pin */
900 {
901 polarity = default_EISA_polarity(idx);
902 break;
903 }
904 case MP_BUS_PCI: /* PCI pin */
905 {
906 polarity = default_PCI_polarity(idx);
907 break;
908 }
909 case MP_BUS_MCA: /* MCA pin */
910 {
911 polarity = default_MCA_polarity(idx);
912 break;
913 }
914 case MP_BUS_NEC98: /* NEC 98 pin */
915 {
916 polarity = default_NEC98_polarity(idx);
917 break;
918 }
919 default:
920 {
921 printk(KERN_WARNING "broken BIOS!!\n");
922 polarity = 1;
923 break;
924 }
925 }
926 break;
927 }
928 case 1: /* high active */
929 {
930 polarity = 0;
931 break;
932 }
933 case 2: /* reserved */
934 {
935 printk(KERN_WARNING "broken BIOS!!\n");
936 polarity = 1;
937 break;
938 }
939 case 3: /* low active */
940 {
941 polarity = 1;
942 break;
943 }
944 default: /* invalid */
945 {
946 printk(KERN_WARNING "broken BIOS!!\n");
947 polarity = 1;
948 break;
949 }
950 }
951 return polarity;
952}
953
954static int MPBIOS_trigger(int idx)
955{
956 int bus = mp_irqs[idx].mpc_srcbus;
957 int trigger;
958
959 /*
960 * Determine IRQ trigger mode (edge or level sensitive):
961 */
962 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
963 {
964 case 0: /* conforms, ie. bus-type dependent */
965 {
966 switch (mp_bus_id_to_type[bus])
967 {
968 case MP_BUS_ISA: /* ISA pin */
969 {
970 trigger = default_ISA_trigger(idx);
971 break;
972 }
973 case MP_BUS_EISA: /* EISA pin */
974 {
975 trigger = default_EISA_trigger(idx);
976 break;
977 }
978 case MP_BUS_PCI: /* PCI pin */
979 {
980 trigger = default_PCI_trigger(idx);
981 break;
982 }
983 case MP_BUS_MCA: /* MCA pin */
984 {
985 trigger = default_MCA_trigger(idx);
986 break;
987 }
988 case MP_BUS_NEC98: /* NEC 98 pin */
989 {
990 trigger = default_NEC98_trigger(idx);
991 break;
992 }
993 default:
994 {
995 printk(KERN_WARNING "broken BIOS!!\n");
996 trigger = 1;
997 break;
998 }
999 }
1000 break;
1001 }
1002 case 1: /* edge */
1003 {
1004 trigger = 0;
1005 break;
1006 }
1007 case 2: /* reserved */
1008 {
1009 printk(KERN_WARNING "broken BIOS!!\n");
1010 trigger = 1;
1011 break;
1012 }
1013 case 3: /* level */
1014 {
1015 trigger = 1;
1016 break;
1017 }
1018 default: /* invalid */
1019 {
1020 printk(KERN_WARNING "broken BIOS!!\n");
1021 trigger = 0;
1022 break;
1023 }
1024 }
1025 return trigger;
1026}
1027
1028static inline int irq_polarity(int idx)
1029{
1030 return MPBIOS_polarity(idx);
1031}
1032
1033static inline int irq_trigger(int idx)
1034{
1035 return MPBIOS_trigger(idx);
1036}
1037
1038static int pin_2_irq(int idx, int apic, int pin)
1039{
1040 int irq, i;
1041 int bus = mp_irqs[idx].mpc_srcbus;
1042
1043 /*
1044 * Debugging check, we are in big trouble if this message pops up!
1045 */
1046 if (mp_irqs[idx].mpc_dstirq != pin)
1047 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1048
1049 switch (mp_bus_id_to_type[bus])
1050 {
1051 case MP_BUS_ISA: /* ISA pin */
1052 case MP_BUS_EISA:
1053 case MP_BUS_MCA:
1054 case MP_BUS_NEC98:
1055 {
1056 irq = mp_irqs[idx].mpc_srcbusirq;
1057 break;
1058 }
1059 case MP_BUS_PCI: /* PCI pin */
1060 {
1061 /*
1062 * PCI IRQs are mapped in order
1063 */
1064 i = irq = 0;
1065 while (i < apic)
1066 irq += nr_ioapic_registers[i++];
1067 irq += pin;
1068
1069 /*
1070 * For MPS mode, so far only needed by ES7000 platform
1071 */
1072 if (ioapic_renumber_irq)
1073 irq = ioapic_renumber_irq(apic, irq);
1074
1075 break;
1076 }
1077 default:
1078 {
1079 printk(KERN_ERR "unknown bus type %d.\n",bus);
1080 irq = 0;
1081 break;
1082 }
1083 }
1084
1085 /*
1086 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1087 */
1088 if ((pin >= 16) && (pin <= 23)) {
1089 if (pirq_entries[pin-16] != -1) {
1090 if (!pirq_entries[pin-16]) {
1091 apic_printk(APIC_VERBOSE, KERN_DEBUG
1092 "disabling PIRQ%d\n", pin-16);
1093 } else {
1094 irq = pirq_entries[pin-16];
1095 apic_printk(APIC_VERBOSE, KERN_DEBUG
1096 "using PIRQ%d -> IRQ %d\n",
1097 pin-16, irq);
1098 }
1099 }
1100 }
1101 return irq;
1102}
1103
1104static inline int IO_APIC_irq_trigger(int irq)
1105{
1106 int apic, idx, pin;
1107
1108 for (apic = 0; apic < nr_ioapics; apic++) {
1109 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1110 idx = find_irq_entry(apic,pin,mp_INT);
1111 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1112 return irq_trigger(idx);
1113 }
1114 }
1115 /*
1116 * nonexistent IRQs are edge default
1117 */
1118 return 0;
1119}
1120
1121/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
6c231b7b 1122u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1da177e4
LT		 1123
1124int assign_irq_vector(int irq)
1125{
1126 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1127
1128 BUG_ON(irq >= NR_IRQ_VECTORS);
1129 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1130 return IO_APIC_VECTOR(irq);
1131next:
1132 current_vector += 8;
1133 if (current_vector == SYSCALL_VECTOR)
1134 goto next;
1135
1136 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1137 offset++;
1138 if (!(offset%8))
1139 return -ENOSPC;
1140 current_vector = FIRST_DEVICE_VECTOR + offset;
1141 }
1142
1143 vector_irq[current_vector] = irq;
1144 if (irq != AUTO_ASSIGN)
1145 IO_APIC_VECTOR(irq) = current_vector;
1146
1147 return current_vector;
1148}
1149
1150static struct hw_interrupt_type ioapic_level_type;
1151static struct hw_interrupt_type ioapic_edge_type;
1152
1153#define IOAPIC_AUTO -1
1154#define IOAPIC_EDGE 0
1155#define IOAPIC_LEVEL 1
1156
1157static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1158{
1159 if (use_pci_vector() && !platform_legacy_irq(irq)) {
1160 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1161 trigger == IOAPIC_LEVEL)
1162 irq_desc[vector].handler = &ioapic_level_type;
1163 else
1164 irq_desc[vector].handler = &ioapic_edge_type;
1165 set_intr_gate(vector, interrupt[vector]);
1166 } else {
1167 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1168 trigger == IOAPIC_LEVEL)
1169 irq_desc[irq].handler = &ioapic_level_type;
1170 else
1171 irq_desc[irq].handler = &ioapic_edge_type;
1172 set_intr_gate(vector, interrupt[irq]);
1173 }
1174}
1175
1176static void __init setup_IO_APIC_irqs(void)
1177{
1178 struct IO_APIC_route_entry entry;
1179 int apic, pin, idx, irq, first_notcon = 1, vector;
1180 unsigned long flags;
1181
1182 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1183
1184 for (apic = 0; apic < nr_ioapics; apic++) {
1185 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1186
1187 /*
1188 * add it to the IO-APIC irq-routing table:
1189 */
1190 memset(&entry,0,sizeof(entry));
1191
1192 entry.delivery_mode = INT_DELIVERY_MODE;
1193 entry.dest_mode = INT_DEST_MODE;
1194 entry.mask = 0; /* enable IRQ */
1195 entry.dest.logical.logical_dest =
1196 cpu_mask_to_apicid(TARGET_CPUS);
1197
1198 idx = find_irq_entry(apic,pin,mp_INT);
1199 if (idx == -1) {
1200 if (first_notcon) {
1201 apic_printk(APIC_VERBOSE, KERN_DEBUG
1202 " IO-APIC (apicid-pin) %d-%d",
1203 mp_ioapics[apic].mpc_apicid,
1204 pin);
1205 first_notcon = 0;
1206 } else
1207 apic_printk(APIC_VERBOSE, ", %d-%d",
1208 mp_ioapics[apic].mpc_apicid, pin);
1209 continue;
1210 }
1211
1212 entry.trigger = irq_trigger(idx);
1213 entry.polarity = irq_polarity(idx);
1214
1215 if (irq_trigger(idx)) {
1216 entry.trigger = 1;
1217 entry.mask = 1;
1218 }
1219
1220 irq = pin_2_irq(idx, apic, pin);
1221 /*
1222 * skip adding the timer int on secondary nodes, which causes
1223 * a small but painful rift in the time-space continuum
1224 */
1225 if (multi_timer_check(apic, irq))
1226 continue;
1227 else
1228 add_pin_to_irq(irq, apic, pin);
1229
1230 if (!apic && !IO_APIC_IRQ(irq))
1231 continue;
1232
1233 if (IO_APIC_IRQ(irq)) {
1234 vector = assign_irq_vector(irq);
1235 entry.vector = vector;
1236 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1237
1238 if (!apic && (irq < 16))
1239 disable_8259A_irq(irq);
1240 }
1241 spin_lock_irqsave(&ioapic_lock, flags);
1242 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1243 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
54d5d424 1244 set_native_irq_info(irq, TARGET_CPUS);
1da177e4
LT		 1245 spin_unlock_irqrestore(&ioapic_lock, flags);
1246 }
1247 }
1248
1249 if (!first_notcon)
1250 apic_printk(APIC_VERBOSE, " not connected.\n");
1251}
1252
1253/*
1254 * Set up the 8259A-master output pin:
1255 */
1256static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1257{
1258 struct IO_APIC_route_entry entry;
1259 unsigned long flags;
1260
1261 memset(&entry,0,sizeof(entry));
1262
1263 disable_8259A_irq(0);
1264
1265 /* mask LVT0 */
1266 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1267
1268 /*
1269 * We use logical delivery to get the timer IRQ
1270 * to the first CPU.
1271 */
1272 entry.dest_mode = INT_DEST_MODE;
1273 entry.mask = 0; /* unmask IRQ now */
1274 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1275 entry.delivery_mode = INT_DELIVERY_MODE;
1276 entry.polarity = 0;
1277 entry.trigger = 0;
1278 entry.vector = vector;
1279
1280 /*
1281 * The timer IRQ doesn't have to know that behind the
1282 * scene we have a 8259A-master in AEOI mode ...
1283 */
1284 irq_desc[0].handler = &ioapic_edge_type;
1285
1286 /*
1287 * Add it to the IO-APIC irq-routing table:
1288 */
1289 spin_lock_irqsave(&ioapic_lock, flags);
1290 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1291 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1292 spin_unlock_irqrestore(&ioapic_lock, flags);
1293
1294 enable_8259A_irq(0);
1295}
1296
1297static inline void UNEXPECTED_IO_APIC(void)
1298{
1299}
1300
1301void __init print_IO_APIC(void)
1302{
1303 int apic, i;
1304 union IO_APIC_reg_00 reg_00;
1305 union IO_APIC_reg_01 reg_01;
1306 union IO_APIC_reg_02 reg_02;
1307 union IO_APIC_reg_03 reg_03;
1308 unsigned long flags;
1309
1310 if (apic_verbosity == APIC_QUIET)
1311 return;
1312
1313 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1314 for (i = 0; i < nr_ioapics; i++)
1315 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1316 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1317
1318 /*
1319 * We are a bit conservative about what we expect. We have to
1320 * know about every hardware change ASAP.
1321 */
1322 printk(KERN_INFO "testing the IO APIC.......................\n");
1323
1324 for (apic = 0; apic < nr_ioapics; apic++) {
1325
1326 spin_lock_irqsave(&ioapic_lock, flags);
1327 reg_00.raw = io_apic_read(apic, 0);
1328 reg_01.raw = io_apic_read(apic, 1);
1329 if (reg_01.bits.version >= 0x10)
1330 reg_02.raw = io_apic_read(apic, 2);
1331 if (reg_01.bits.version >= 0x20)
1332 reg_03.raw = io_apic_read(apic, 3);
1333 spin_unlock_irqrestore(&ioapic_lock, flags);
1334
1335 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1336 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1337 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1338 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1339 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1340 if (reg_00.bits.ID >= get_physical_broadcast())
1341 UNEXPECTED_IO_APIC();
1342 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1343 UNEXPECTED_IO_APIC();
1344
1345 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1346 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1347 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1348 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1349 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1350 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1351 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1352 (reg_01.bits.entries != 0x2E) &&
1353 (reg_01.bits.entries != 0x3F)
1354 )
1355 UNEXPECTED_IO_APIC();
1356
1357 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1358 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1359 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1360 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1361 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1362 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1363 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1364 )
1365 UNEXPECTED_IO_APIC();
1366 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1367 UNEXPECTED_IO_APIC();
1368
1369 /*
1370 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1371 * but the value of reg_02 is read as the previous read register
1372 * value, so ignore it if reg_02 == reg_01.
1373 */
1374 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1375 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1376 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1377 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1378 UNEXPECTED_IO_APIC();
1379 }
1380
1381 /*
1382 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1383 * or reg_03, but the value of reg_0[23] is read as the previous read
1384 * register value, so ignore it if reg_03 == reg_0[12].
1385 */
1386 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1387 reg_03.raw != reg_01.raw) {
1388 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1389 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1390 if (reg_03.bits.__reserved_1)
1391 UNEXPECTED_IO_APIC();
1392 }
1393
1394 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1395
1396 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1397 " Stat Dest Deli Vect: \n");
1398
1399 for (i = 0; i <= reg_01.bits.entries; i++) {
1400 struct IO_APIC_route_entry entry;
1401
1402 spin_lock_irqsave(&ioapic_lock, flags);
1403 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1404 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1405 spin_unlock_irqrestore(&ioapic_lock, flags);
1406
1407 printk(KERN_DEBUG " %02x %03X %02X ",
1408 i,
1409 entry.dest.logical.logical_dest,
1410 entry.dest.physical.physical_dest
1411 );
1412
1413 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1414 entry.mask,
1415 entry.trigger,
1416 entry.irr,
1417 entry.polarity,
1418 entry.delivery_status,
1419 entry.dest_mode,
1420 entry.delivery_mode,
1421 entry.vector
1422 );
1423 }
1424 }
1425 if (use_pci_vector())
1426 printk(KERN_INFO "Using vector-based indexing\n");
1427 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1428 for (i = 0; i < NR_IRQS; i++) {
1429 struct irq_pin_list *entry = irq_2_pin + i;
1430 if (entry->pin < 0)
1431 continue;
1432 if (use_pci_vector() && !platform_legacy_irq(i))
1433 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1434 else
1435 printk(KERN_DEBUG "IRQ%d ", i);
1436 for (;;) {
1437 printk("-> %d:%d", entry->apic, entry->pin);
1438 if (!entry->next)
1439 break;
1440 entry = irq_2_pin + entry->next;
1441 }
1442 printk("\n");
1443 }
1444
1445 printk(KERN_INFO ".................................... done.\n");
1446
1447 return;
1448}
1449
1450#if 0
1451
1452static void print_APIC_bitfield (int base)
1453{
1454 unsigned int v;
1455 int i, j;
1456
1457 if (apic_verbosity == APIC_QUIET)
1458 return;
1459
1460 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1461 for (i = 0; i < 8; i++) {
1462 v = apic_read(base + i*0x10);
1463 for (j = 0; j < 32; j++) {
1464 if (v & (1<<j))
1465 printk("1");
1466 else
1467 printk("0");
1468 }
1469 printk("\n");
1470 }
1471}
1472
1473void /*__init*/ print_local_APIC(void * dummy)
1474{
1475 unsigned int v, ver, maxlvt;
1476
1477 if (apic_verbosity == APIC_QUIET)
1478 return;
1479
1480 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1481 smp_processor_id(), hard_smp_processor_id());
1482 v = apic_read(APIC_ID);
1483 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1484 v = apic_read(APIC_LVR);
1485 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1486 ver = GET_APIC_VERSION(v);
1487 maxlvt = get_maxlvt();
1488
1489 v = apic_read(APIC_TASKPRI);
1490 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1491
1492 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1493 v = apic_read(APIC_ARBPRI);
1494 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1495 v & APIC_ARBPRI_MASK);
1496 v = apic_read(APIC_PROCPRI);
1497 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1498 }
1499
1500 v = apic_read(APIC_EOI);
1501 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1502 v = apic_read(APIC_RRR);
1503 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1504 v = apic_read(APIC_LDR);
1505 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1506 v = apic_read(APIC_DFR);
1507 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1508 v = apic_read(APIC_SPIV);
1509 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1510
1511 printk(KERN_DEBUG "... APIC ISR field:\n");
1512 print_APIC_bitfield(APIC_ISR);
1513 printk(KERN_DEBUG "... APIC TMR field:\n");
1514 print_APIC_bitfield(APIC_TMR);
1515 printk(KERN_DEBUG "... APIC IRR field:\n");
1516 print_APIC_bitfield(APIC_IRR);
1517
1518 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1519 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1520 apic_write(APIC_ESR, 0);
1521 v = apic_read(APIC_ESR);
1522 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1523 }
1524
1525 v = apic_read(APIC_ICR);
1526 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1527 v = apic_read(APIC_ICR2);
1528 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1529
1530 v = apic_read(APIC_LVTT);
1531 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1532
1533 if (maxlvt > 3) { /* PC is LVT#4. */
1534 v = apic_read(APIC_LVTPC);
1535 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1536 }
1537 v = apic_read(APIC_LVT0);
1538 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1539 v = apic_read(APIC_LVT1);
1540 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1541
1542 if (maxlvt > 2) { /* ERR is LVT#3. */
1543 v = apic_read(APIC_LVTERR);
1544 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1545 }
1546
1547 v = apic_read(APIC_TMICT);
1548 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1549 v = apic_read(APIC_TMCCT);
1550 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1551 v = apic_read(APIC_TDCR);
1552 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1553 printk("\n");
1554}
1555
1556void print_all_local_APICs (void)
1557{
1558 on_each_cpu(print_local_APIC, NULL, 1, 1);
1559}
1560
1561void /*__init*/ print_PIC(void)
1562{
1da177e4
LT		 1563 unsigned int v;
1564 unsigned long flags;
1565
1566 if (apic_verbosity == APIC_QUIET)
1567 return;
1568
1569 printk(KERN_DEBUG "\nprinting PIC contents\n");
1570
1571 spin_lock_irqsave(&i8259A_lock, flags);
1572
1573 v = inb(0xa1) << 8 | inb(0x21);
1574 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1575
1576 v = inb(0xa0) << 8 | inb(0x20);
1577 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1578
1579 outb(0x0b,0xa0);
1580 outb(0x0b,0x20);
1581 v = inb(0xa0) << 8 | inb(0x20);
1582 outb(0x0a,0xa0);
1583 outb(0x0a,0x20);
1584
1585 spin_unlock_irqrestore(&i8259A_lock, flags);
1586
1587 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1588
1589 v = inb(0x4d1) << 8 | inb(0x4d0);
1590 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1591}
1592
1593#endif /* 0 */
1594
1595static void __init enable_IO_APIC(void)
1596{
1597 union IO_APIC_reg_01 reg_01;
1598 int i;
1599 unsigned long flags;
1600
1601 for (i = 0; i < PIN_MAP_SIZE; i++) {
1602 irq_2_pin[i].pin = -1;
1603 irq_2_pin[i].next = 0;
1604 }
1605 if (!pirqs_enabled)
1606 for (i = 0; i < MAX_PIRQS; i++)
1607 pirq_entries[i] = -1;
1608
1609 /*
1610 * The number of IO-APIC IRQ registers (== #pins):
1611 */
1612 for (i = 0; i < nr_ioapics; i++) {
1613 spin_lock_irqsave(&ioapic_lock, flags);
1614 reg_01.raw = io_apic_read(i, 1);
1615 spin_unlock_irqrestore(&ioapic_lock, flags);
1616 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1617 }
1618
1619 /*
1620 * Do not trust the IO-APIC being empty at bootup
1621 */
1622 clear_IO_APIC();
1623}
1624
1625/*
1626 * Not an __init, needed by the reboot code
1627 */
1628void disable_IO_APIC(void)
1629{
650927ef 1630 int pin;
1da177e4
LT		 1631 /*
1632 * Clear the IO-APIC before rebooting:
1633 */
1634 clear_IO_APIC();
1635
650927ef 1636 /*
0b968d23 1637 * If the i8259 is routed through an IOAPIC
650927ef 1638 * Put that IOAPIC in virtual wire mode
0b968d23 1639 * so legacy interrupts can be delivered.
650927ef
EB		 1640 */
1641 pin = find_isa_irq_pin(0, mp_ExtINT);
1642 if (pin != -1) {
1643 struct IO_APIC_route_entry entry;
1644 unsigned long flags;
1645
1646 memset(&entry, 0, sizeof(entry));
1647 entry.mask = 0; /* Enabled */
1648 entry.trigger = 0; /* Edge */
1649 entry.irr = 0;
1650 entry.polarity = 0; /* High */
1651 entry.delivery_status = 0;
1652 entry.dest_mode = 0; /* Physical */
1653 entry.delivery_mode = 7; /* ExtInt */
1654 entry.vector = 0;
1655 entry.dest.physical.physical_dest = 0;
1656
1657
1658 /*
1659 * Add it to the IO-APIC irq-routing table:
1660 */
1661 spin_lock_irqsave(&ioapic_lock, flags);
1662 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1663 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1664 spin_unlock_irqrestore(&ioapic_lock, flags);
1665 }
1666 disconnect_bsp_APIC(pin != -1);
1da177e4
LT		 1667}
1668
1669/*
1670 * function to set the IO-APIC physical IDs based on the
1671 * values stored in the MPC table.
1672 *
1673 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1674 */
1675
1676#ifndef CONFIG_X86_NUMAQ
1677static void __init setup_ioapic_ids_from_mpc(void)
1678{
1679 union IO_APIC_reg_00 reg_00;
1680 physid_mask_t phys_id_present_map;
1681 int apic;
1682 int i;
1683 unsigned char old_id;
1684 unsigned long flags;
1685
ca05fea6
NP		 1686 /*
1687 * Don't check I/O APIC IDs for xAPIC systems. They have
1688 * no meaning without the serial APIC bus.
1689 */
1690 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
1691 return;
1da177e4
LT		 1692 /*
1693 * This is broken; anything with a real cpu count has to
1694 * circumvent this idiocy regardless.
1695 */
1696 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1697
1698 /*
1699 * Set the IOAPIC ID to the value stored in the MPC table.
1700 */
1701 for (apic = 0; apic < nr_ioapics; apic++) {
1702
1703 /* Read the register 0 value */
1704 spin_lock_irqsave(&ioapic_lock, flags);
1705 reg_00.raw = io_apic_read(apic, 0);
1706 spin_unlock_irqrestore(&ioapic_lock, flags);
1707
1708 old_id = mp_ioapics[apic].mpc_apicid;
1709
1710 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1711 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1712 apic, mp_ioapics[apic].mpc_apicid);
1713 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1714 reg_00.bits.ID);
1715 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1716 }
1717
1da177e4
LT		 1718 /*
1719 * Sanity check, is the ID really free? Every APIC in a
1720 * system must have a unique ID or we get lots of nice
1721 * 'stuck on smp_invalidate_needed IPI wait' messages.
1722 */
1723 if (check_apicid_used(phys_id_present_map,
1724 mp_ioapics[apic].mpc_apicid)) {
1725 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1726 apic, mp_ioapics[apic].mpc_apicid);
1727 for (i = 0; i < get_physical_broadcast(); i++)
1728 if (!physid_isset(i, phys_id_present_map))
1729 break;
1730 if (i >= get_physical_broadcast())
1731 panic("Max APIC ID exceeded!\n");
1732 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1733 i);
1734 physid_set(i, phys_id_present_map);
1735 mp_ioapics[apic].mpc_apicid = i;
1736 } else {
1737 physid_mask_t tmp;
1738 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1739 apic_printk(APIC_VERBOSE, "Setting %d in the "
1740 "phys_id_present_map\n",
1741 mp_ioapics[apic].mpc_apicid);
1742 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1743 }
1744
1745
1746 /*
1747 * We need to adjust the IRQ routing table
1748 * if the ID changed.
1749 */
1750 if (old_id != mp_ioapics[apic].mpc_apicid)
1751 for (i = 0; i < mp_irq_entries; i++)
1752 if (mp_irqs[i].mpc_dstapic == old_id)
1753 mp_irqs[i].mpc_dstapic
1754 = mp_ioapics[apic].mpc_apicid;
1755
1756 /*
1757 * Read the right value from the MPC table and
1758 * write it into the ID register.
1759 */
1760 apic_printk(APIC_VERBOSE, KERN_INFO
1761 "...changing IO-APIC physical APIC ID to %d ...",
1762 mp_ioapics[apic].mpc_apicid);
1763
1764 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1765 spin_lock_irqsave(&ioapic_lock, flags);
1766 io_apic_write(apic, 0, reg_00.raw);
1767 spin_unlock_irqrestore(&ioapic_lock, flags);
1768
1769 /*
1770 * Sanity check
1771 */
1772 spin_lock_irqsave(&ioapic_lock, flags);
1773 reg_00.raw = io_apic_read(apic, 0);
1774 spin_unlock_irqrestore(&ioapic_lock, flags);
1775 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1776 printk("could not set ID!\n");
1777 else
1778 apic_printk(APIC_VERBOSE, " ok.\n");
1779 }
1780}
1781#else
1782static void __init setup_ioapic_ids_from_mpc(void) { }
1783#endif
1784
1785/*
1786 * There is a nasty bug in some older SMP boards, their mptable lies
1787 * about the timer IRQ. We do the following to work around the situation:
1788 *
1789 * - timer IRQ defaults to IO-APIC IRQ
1790 * - if this function detects that timer IRQs are defunct, then we fall
1791 * back to ISA timer IRQs
1792 */
1793static int __init timer_irq_works(void)
1794{
1795 unsigned long t1 = jiffies;
1796
1797 local_irq_enable();
1798 /* Let ten ticks pass... */
1799 mdelay((10 * 1000) / HZ);
1800
1801 /*
1802 * Expect a few ticks at least, to be sure some possible
1803 * glue logic does not lock up after one or two first
1804 * ticks in a non-ExtINT mode. Also the local APIC
1805 * might have cached one ExtINT interrupt. Finally, at
1806 * least one tick may be lost due to delays.
1807 */
1808 if (jiffies - t1 > 4)
1809 return 1;
1810
1811 return 0;
1812}
1813
1814/*
1815 * In the SMP+IOAPIC case it might happen that there are an unspecified
1816 * number of pending IRQ events unhandled. These cases are very rare,
1817 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1818 * better to do it this way as thus we do not have to be aware of
1819 * 'pending' interrupts in the IRQ path, except at this point.
1820 */
1821/*
1822 * Edge triggered needs to resend any interrupt
1823 * that was delayed but this is now handled in the device
1824 * independent code.
1825 */
1826
1827/*
1828 * Starting up a edge-triggered IO-APIC interrupt is
1829 * nasty - we need to make sure that we get the edge.
1830 * If it is already asserted for some reason, we need
1831 * return 1 to indicate that is was pending.
1832 *
1833 * This is not complete - we should be able to fake
1834 * an edge even if it isn't on the 8259A...
1835 */
1836static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1837{
1838 int was_pending = 0;
1839 unsigned long flags;
1840
1841 spin_lock_irqsave(&ioapic_lock, flags);
1842 if (irq < 16) {
1843 disable_8259A_irq(irq);
1844 if (i8259A_irq_pending(irq))
1845 was_pending = 1;
1846 }
1847 __unmask_IO_APIC_irq(irq);
1848 spin_unlock_irqrestore(&ioapic_lock, flags);
1849
1850 return was_pending;
1851}
1852
1853/*
1854 * Once we have recorded IRQ_PENDING already, we can mask the
1855 * interrupt for real. This prevents IRQ storms from unhandled
1856 * devices.
1857 */
1858static void ack_edge_ioapic_irq(unsigned int irq)
1859{
1860 move_irq(irq);
1861 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1862 == (IRQ_PENDING | IRQ_DISABLED))
1863 mask_IO_APIC_irq(irq);
1864 ack_APIC_irq();
1865}
1866
1867/*
1868 * Level triggered interrupts can just be masked,
1869 * and shutting down and starting up the interrupt
1870 * is the same as enabling and disabling them -- except
1871 * with a startup need to return a "was pending" value.
1872 *
1873 * Level triggered interrupts are special because we
1874 * do not touch any IO-APIC register while handling
1875 * them. We ack the APIC in the end-IRQ handler, not
1876 * in the start-IRQ-handler. Protection against reentrance
1877 * from the same interrupt is still provided, both by the
1878 * generic IRQ layer and by the fact that an unacked local
1879 * APIC does not accept IRQs.
1880 */
1881static unsigned int startup_level_ioapic_irq (unsigned int irq)
1882{
1883 unmask_IO_APIC_irq(irq);
1884
1885 return 0; /* don't check for pending */
1886}
1887
1888static void end_level_ioapic_irq (unsigned int irq)
1889{
1890 unsigned long v;
1891 int i;
1892
1893 move_irq(irq);
1894/*
1895 * It appears there is an erratum which affects at least version 0x11
1896 * of I/O APIC (that's the 82093AA and cores integrated into various
1897 * chipsets). Under certain conditions a level-triggered interrupt is
1898 * erroneously delivered as edge-triggered one but the respective IRR
1899 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1900 * message but it will never arrive and further interrupts are blocked
1901 * from the source. The exact reason is so far unknown, but the
1902 * phenomenon was observed when two consecutive interrupt requests
1903 * from a given source get delivered to the same CPU and the source is
1904 * temporarily disabled in between.
1905 *
1906 * A workaround is to simulate an EOI message manually. We achieve it
1907 * by setting the trigger mode to edge and then to level when the edge
1908 * trigger mode gets detected in the TMR of a local APIC for a
1909 * level-triggered interrupt. We mask the source for the time of the
1910 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1911 * The idea is from Manfred Spraul. --macro
1912 */
1913 i = IO_APIC_VECTOR(irq);
1914
1915 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1916
1917 ack_APIC_irq();
1918
1919 if (!(v & (1 << (i & 0x1f)))) {
1920 atomic_inc(&irq_mis_count);
1921 spin_lock(&ioapic_lock);
1922 __mask_and_edge_IO_APIC_irq(irq);
1923 __unmask_and_level_IO_APIC_irq(irq);
1924 spin_unlock(&ioapic_lock);
1925 }
1926}
1927
1928#ifdef CONFIG_PCI_MSI
1929static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1930{
1931 int irq = vector_to_irq(vector);
1932
1933 return startup_edge_ioapic_irq(irq);
1934}
1935
1936static void ack_edge_ioapic_vector(unsigned int vector)
1937{
1938 int irq = vector_to_irq(vector);
1939
54d5d424 1940 move_irq(vector);
1da177e4
LT		 1941 ack_edge_ioapic_irq(irq);
1942}
1943
1944static unsigned int startup_level_ioapic_vector (unsigned int vector)
1945{
1946 int irq = vector_to_irq(vector);
1947
1948 return startup_level_ioapic_irq (irq);
1949}
1950
1951static void end_level_ioapic_vector (unsigned int vector)
1952{
1953 int irq = vector_to_irq(vector);
1954
54d5d424 1955 move_irq(vector);
1da177e4
LT		 1956 end_level_ioapic_irq(irq);
1957}
1958
1959static void mask_IO_APIC_vector (unsigned int vector)
1960{
1961 int irq = vector_to_irq(vector);
1962
1963 mask_IO_APIC_irq(irq);
1964}
1965
1966static void unmask_IO_APIC_vector (unsigned int vector)
1967{
1968 int irq = vector_to_irq(vector);
1969
1970 unmask_IO_APIC_irq(irq);
1971}
1972
54d5d424 1973#ifdef CONFIG_SMP
1da177e4
LT		 1974static void set_ioapic_affinity_vector (unsigned int vector,
1975 cpumask_t cpu_mask)
1976{
1977 int irq = vector_to_irq(vector);
1978
54d5d424 1979 set_native_irq_info(vector, cpu_mask);
1da177e4
LT		 1980 set_ioapic_affinity_irq(irq, cpu_mask);
1981}
1982#endif
54d5d424 1983#endif
1da177e4
LT		 1984
1985/*
1986 * Level and edge triggered IO-APIC interrupts need different handling,
1987 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1988 * handled with the level-triggered descriptor, but that one has slightly
1989 * more overhead. Level-triggered interrupts cannot be handled with the
1990 * edge-triggered handler, without risking IRQ storms and other ugly
1991 * races.
1992 */
6c231b7b 1993static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1da177e4
LT		 1994 .typename = "IO-APIC-edge",
1995 .startup = startup_edge_ioapic,
1996 .shutdown = shutdown_edge_ioapic,
1997 .enable = enable_edge_ioapic,
1998 .disable = disable_edge_ioapic,
1999 .ack = ack_edge_ioapic,
2000 .end = end_edge_ioapic,
54d5d424 2001#ifdef CONFIG_SMP
1da177e4 2002 .set_affinity = set_ioapic_affinity,
54d5d424 2003#endif
1da177e4
LT		 2004};
2005
6c231b7b 2006static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1da177e4
LT		 2007 .typename = "IO-APIC-level",
2008 .startup = startup_level_ioapic,
2009 .shutdown = shutdown_level_ioapic,
2010 .enable = enable_level_ioapic,
2011 .disable = disable_level_ioapic,
2012 .ack = mask_and_ack_level_ioapic,
2013 .end = end_level_ioapic,
54d5d424 2014#ifdef CONFIG_SMP
1da177e4 2015 .set_affinity = set_ioapic_affinity,
54d5d424 2016#endif
1da177e4
LT		 2017};
2018
2019static inline void init_IO_APIC_traps(void)
2020{
2021 int irq;
2022
2023 /*
2024 * NOTE! The local APIC isn't very good at handling
2025 * multiple interrupts at the same interrupt level.
2026 * As the interrupt level is determined by taking the
2027 * vector number and shifting that right by 4, we
2028 * want to spread these out a bit so that they don't
2029 * all fall in the same interrupt level.
2030 *
2031 * Also, we've got to be careful not to trash gate
2032 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2033 */
2034 for (irq = 0; irq < NR_IRQS ; irq++) {
2035 int tmp = irq;
2036 if (use_pci_vector()) {
2037 if (!platform_legacy_irq(tmp))
2038 if ((tmp = vector_to_irq(tmp)) == -1)
2039 continue;
2040 }
2041 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2042 /*
2043 * Hmm.. We don't have an entry for this,
2044 * so default to an old-fashioned 8259
2045 * interrupt if we can..
2046 */
2047 if (irq < 16)
2048 make_8259A_irq(irq);
2049 else
2050 /* Strange. Oh, well.. */
2051 irq_desc[irq].handler = &no_irq_type;
2052 }
2053 }
2054}
2055
2056static void enable_lapic_irq (unsigned int irq)
2057{
2058 unsigned long v;
2059
2060 v = apic_read(APIC_LVT0);
2061 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2062}
2063
2064static void disable_lapic_irq (unsigned int irq)
2065{
2066 unsigned long v;
2067
2068 v = apic_read(APIC_LVT0);
2069 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2070}
2071
2072static void ack_lapic_irq (unsigned int irq)
2073{
2074 ack_APIC_irq();
2075}
2076
2077static void end_lapic_irq (unsigned int i) { /* nothing */ }
2078
6c231b7b 2079static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1da177e4
LT		 2080 .typename = "local-APIC-edge",
2081 .startup = NULL, /* startup_irq() not used for IRQ0 */
2082 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2083 .enable = enable_lapic_irq,
2084 .disable = disable_lapic_irq,
2085 .ack = ack_lapic_irq,
2086 .end = end_lapic_irq
2087};
2088
2089static void setup_nmi (void)
2090{
2091 /*
2092 * Dirty trick to enable the NMI watchdog ...
2093 * We put the 8259A master into AEOI mode and
2094 * unmask on all local APICs LVT0 as NMI.
2095 *
2096 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2097 * is from Maciej W. Rozycki - so we do not have to EOI from
2098 * the NMI handler or the timer interrupt.
2099 */
2100 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2101
2102 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2103
2104 apic_printk(APIC_VERBOSE, " done.\n");
2105}
2106
2107/*
2108 * This looks a bit hackish but it's about the only one way of sending
2109 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2110 * not support the ExtINT mode, unfortunately. We need to send these
2111 * cycles as some i82489DX-based boards have glue logic that keeps the
2112 * 8259A interrupt line asserted until INTA. --macro
2113 */
2114static inline void unlock_ExtINT_logic(void)
2115{
2116 int pin, i;
2117 struct IO_APIC_route_entry entry0, entry1;
2118 unsigned char save_control, save_freq_select;
2119 unsigned long flags;
2120
2121 pin = find_isa_irq_pin(8, mp_INT);
2122 if (pin == -1)
2123 return;
2124
2125 spin_lock_irqsave(&ioapic_lock, flags);
2126 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2127 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2128 spin_unlock_irqrestore(&ioapic_lock, flags);
2129 clear_IO_APIC_pin(0, pin);
2130
2131 memset(&entry1, 0, sizeof(entry1));
2132
2133 entry1.dest_mode = 0; /* physical delivery */
2134 entry1.mask = 0; /* unmask IRQ now */
2135 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2136 entry1.delivery_mode = dest_ExtINT;
2137 entry1.polarity = entry0.polarity;
2138 entry1.trigger = 0;
2139 entry1.vector = 0;
2140
2141 spin_lock_irqsave(&ioapic_lock, flags);
2142 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2143 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2144 spin_unlock_irqrestore(&ioapic_lock, flags);
2145
2146 save_control = CMOS_READ(RTC_CONTROL);
2147 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2148 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2149 RTC_FREQ_SELECT);
2150 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2151
2152 i = 100;
2153 while (i-- > 0) {
2154 mdelay(10);
2155 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2156 i -= 10;
2157 }
2158
2159 CMOS_WRITE(save_control, RTC_CONTROL);
2160 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2161 clear_IO_APIC_pin(0, pin);
2162
2163 spin_lock_irqsave(&ioapic_lock, flags);
2164 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2165 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2166 spin_unlock_irqrestore(&ioapic_lock, flags);
2167}
2168
2169/*
2170 * This code may look a bit paranoid, but it's supposed to cooperate with
2171 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2172 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2173 * fanatically on his truly buggy board.
2174 */
2175static inline void check_timer(void)
2176{
2177 int pin1, pin2;
2178 int vector;
2179
2180 /*
2181 * get/set the timer IRQ vector:
2182 */
2183 disable_8259A_irq(0);
2184 vector = assign_irq_vector(0);
2185 set_intr_gate(vector, interrupt[0]);
2186
2187 /*
2188 * Subtle, code in do_timer_interrupt() expects an AEOI
2189 * mode for the 8259A whenever interrupts are routed
2190 * through I/O APICs. Also IRQ0 has to be enabled in
2191 * the 8259A which implies the virtual wire has to be
2192 * disabled in the local APIC.
2193 */
2194 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2195 init_8259A(1);
2196 timer_ack = 1;
2197 enable_8259A_irq(0);
2198
2199 pin1 = find_isa_irq_pin(0, mp_INT);
2200 pin2 = find_isa_irq_pin(0, mp_ExtINT);
2201
2202 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2203
2204 if (pin1 != -1) {
2205 /*
2206 * Ok, does IRQ0 through the IOAPIC work?
2207 */
2208 unmask_IO_APIC_irq(0);
2209 if (timer_irq_works()) {
2210 if (nmi_watchdog == NMI_IO_APIC) {
2211 disable_8259A_irq(0);
2212 setup_nmi();
2213 enable_8259A_irq(0);
1da177e4 2214 }
66759a01
CE		 2215 if (disable_timer_pin_1 > 0)
2216 clear_IO_APIC_pin(0, pin1);
1da177e4
LT		 2217 return;
2218 }
2219 clear_IO_APIC_pin(0, pin1);
2220 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2221 }
2222
2223 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2224 if (pin2 != -1) {
2225 printk("\n..... (found pin %d) ...", pin2);
2226 /*
2227 * legacy devices should be connected to IO APIC #0
2228 */
2229 setup_ExtINT_IRQ0_pin(pin2, vector);
2230 if (timer_irq_works()) {
2231 printk("works.\n");
2232 if (pin1 != -1)
2233 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2234 else
2235 add_pin_to_irq(0, 0, pin2);
2236 if (nmi_watchdog == NMI_IO_APIC) {
2237 setup_nmi();
1da177e4
LT		 2238 }
2239 return;
2240 }
2241 /*
2242 * Cleanup, just in case ...
2243 */
2244 clear_IO_APIC_pin(0, pin2);
2245 }
2246 printk(" failed.\n");
2247
2248 if (nmi_watchdog == NMI_IO_APIC) {
2249 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2250 nmi_watchdog = 0;
2251 }
2252
2253 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2254
2255 disable_8259A_irq(0);
2256 irq_desc[0].handler = &lapic_irq_type;
2257 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2258 enable_8259A_irq(0);
2259
2260 if (timer_irq_works()) {
2261 printk(" works.\n");
2262 return;
2263 }
2264 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2265 printk(" failed.\n");
2266
2267 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2268
2269 timer_ack = 0;
2270 init_8259A(0);
2271 make_8259A_irq(0);
2272 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2273
2274 unlock_ExtINT_logic();
2275
2276 if (timer_irq_works()) {
2277 printk(" works.\n");
2278 return;
2279 }
2280 printk(" failed :(.\n");
2281 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2282 "report. Then try booting with the 'noapic' option");
2283}
2284
2285/*
2286 *
2287 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2288 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2289 * Linux doesn't really care, as it's not actually used
2290 * for any interrupt handling anyway.
2291 */
2292#define PIC_IRQS (1 << PIC_CASCADE_IR)
2293
2294void __init setup_IO_APIC(void)
2295{
2296 enable_IO_APIC();
2297
2298 if (acpi_ioapic)
2299 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2300 else
2301 io_apic_irqs = ~PIC_IRQS;
2302
2303 printk("ENABLING IO-APIC IRQs\n");
2304
2305 /*
2306 * Set up IO-APIC IRQ routing.
2307 */
2308 if (!acpi_ioapic)
2309 setup_ioapic_ids_from_mpc();
2310 sync_Arb_IDs();
2311 setup_IO_APIC_irqs();
2312 init_IO_APIC_traps();
2313 check_timer();
2314 if (!acpi_ioapic)
2315 print_IO_APIC();
2316}
2317
2318/*
2319 * Called after all the initialization is done. If we didnt find any
2320 * APIC bugs then we can allow the modify fast path
2321 */
2322
2323static int __init io_apic_bug_finalize(void)
2324{
2325 if(sis_apic_bug == -1)
2326 sis_apic_bug = 0;
2327 return 0;
2328}
2329
2330late_initcall(io_apic_bug_finalize);
2331
2332struct sysfs_ioapic_data {
2333 struct sys_device dev;
2334 struct IO_APIC_route_entry entry[0];
2335};
2336static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2337
438510f6 2338static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 2339{
2340 struct IO_APIC_route_entry *entry;
2341 struct sysfs_ioapic_data *data;
2342 unsigned long flags;
2343 int i;
2344
2345 data = container_of(dev, struct sysfs_ioapic_data, dev);
2346 entry = data->entry;
2347 spin_lock_irqsave(&ioapic_lock, flags);
2348 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2349 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2350 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2351 }
2352 spin_unlock_irqrestore(&ioapic_lock, flags);
2353
2354 return 0;
2355}
2356
2357static int ioapic_resume(struct sys_device *dev)
2358{
2359 struct IO_APIC_route_entry *entry;
2360 struct sysfs_ioapic_data *data;
2361 unsigned long flags;
2362 union IO_APIC_reg_00 reg_00;
2363 int i;
2364
2365 data = container_of(dev, struct sysfs_ioapic_data, dev);
2366 entry = data->entry;
2367
2368 spin_lock_irqsave(&ioapic_lock, flags);
2369 reg_00.raw = io_apic_read(dev->id, 0);
2370 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2371 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2372 io_apic_write(dev->id, 0, reg_00.raw);
2373 }
2374 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2375 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2376 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2377 }
2378 spin_unlock_irqrestore(&ioapic_lock, flags);
2379
2380 return 0;
2381}
2382
2383static struct sysdev_class ioapic_sysdev_class = {
2384 set_kset_name("ioapic"),
2385 .suspend = ioapic_suspend,
2386 .resume = ioapic_resume,
2387};
2388
2389static int __init ioapic_init_sysfs(void)
2390{
2391 struct sys_device * dev;
2392 int i, size, error = 0;
2393
2394 error = sysdev_class_register(&ioapic_sysdev_class);
2395 if (error)
2396 return error;
2397
2398 for (i = 0; i < nr_ioapics; i++ ) {
2399 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2400 * sizeof(struct IO_APIC_route_entry);
2401 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2402 if (!mp_ioapic_data[i]) {
2403 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2404 continue;
2405 }
2406 memset(mp_ioapic_data[i], 0, size);
2407 dev = &mp_ioapic_data[i]->dev;
2408 dev->id = i;
2409 dev->cls = &ioapic_sysdev_class;
2410 error = sysdev_register(dev);
2411 if (error) {
2412 kfree(mp_ioapic_data[i]);
2413 mp_ioapic_data[i] = NULL;
2414 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2415 continue;
2416 }
2417 }
2418
2419 return 0;
2420}
2421
2422device_initcall(ioapic_init_sysfs);
2423
2424/* --------------------------------------------------------------------------
2425 ACPI-based IOAPIC Configuration
2426 -------------------------------------------------------------------------- */
2427
888ba6c6 2428#ifdef CONFIG_ACPI
1da177e4
LT		 2429
2430int __init io_apic_get_unique_id (int ioapic, int apic_id)
2431{
2432 union IO_APIC_reg_00 reg_00;
2433 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2434 physid_mask_t tmp;
2435 unsigned long flags;
2436 int i = 0;
2437
2438 /*
2439 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2440 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2441 * supports up to 16 on one shared APIC bus.
2442 *
2443 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2444 * advantage of new APIC bus architecture.
2445 */
2446
2447 if (physids_empty(apic_id_map))
2448 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2449
2450 spin_lock_irqsave(&ioapic_lock, flags);
2451 reg_00.raw = io_apic_read(ioapic, 0);
2452 spin_unlock_irqrestore(&ioapic_lock, flags);
2453
2454 if (apic_id >= get_physical_broadcast()) {
2455 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2456 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2457 apic_id = reg_00.bits.ID;
2458 }
2459
2460 /*
2461 * Every APIC in a system must have a unique ID or we get lots of nice
2462 * 'stuck on smp_invalidate_needed IPI wait' messages.
2463 */
2464 if (check_apicid_used(apic_id_map, apic_id)) {
2465
2466 for (i = 0; i < get_physical_broadcast(); i++) {
2467 if (!check_apicid_used(apic_id_map, i))
2468 break;
2469 }
2470
2471 if (i == get_physical_broadcast())
2472 panic("Max apic_id exceeded!\n");
2473
2474 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2475 "trying %d\n", ioapic, apic_id, i);
2476
2477 apic_id = i;
2478 }
2479
2480 tmp = apicid_to_cpu_present(apic_id);
2481 physids_or(apic_id_map, apic_id_map, tmp);
2482
2483 if (reg_00.bits.ID != apic_id) {
2484 reg_00.bits.ID = apic_id;
2485
2486 spin_lock_irqsave(&ioapic_lock, flags);
2487 io_apic_write(ioapic, 0, reg_00.raw);
2488 reg_00.raw = io_apic_read(ioapic, 0);
2489 spin_unlock_irqrestore(&ioapic_lock, flags);
2490
2491 /* Sanity check */
2492 if (reg_00.bits.ID != apic_id)
2493 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2494 }
2495
2496 apic_printk(APIC_VERBOSE, KERN_INFO
2497 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2498
2499 return apic_id;
2500}
2501
2502
2503int __init io_apic_get_version (int ioapic)
2504{
2505 union IO_APIC_reg_01 reg_01;
2506 unsigned long flags;
2507
2508 spin_lock_irqsave(&ioapic_lock, flags);
2509 reg_01.raw = io_apic_read(ioapic, 1);
2510 spin_unlock_irqrestore(&ioapic_lock, flags);
2511
2512 return reg_01.bits.version;
2513}
2514
2515
2516int __init io_apic_get_redir_entries (int ioapic)
2517{
2518 union IO_APIC_reg_01 reg_01;
2519 unsigned long flags;
2520
2521 spin_lock_irqsave(&ioapic_lock, flags);
2522 reg_01.raw = io_apic_read(ioapic, 1);
2523 spin_unlock_irqrestore(&ioapic_lock, flags);
2524
2525 return reg_01.bits.entries;
2526}
2527
2528
2529int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2530{
2531 struct IO_APIC_route_entry entry;
2532 unsigned long flags;
2533
2534 if (!IO_APIC_IRQ(irq)) {
2535 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2536 ioapic);
2537 return -EINVAL;
2538 }
2539
2540 /*
2541 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2542 * Note that we mask (disable) IRQs now -- these get enabled when the
2543 * corresponding device driver registers for this IRQ.
2544 */
2545
2546 memset(&entry,0,sizeof(entry));
2547
2548 entry.delivery_mode = INT_DELIVERY_MODE;
2549 entry.dest_mode = INT_DEST_MODE;
2550 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2551 entry.trigger = edge_level;
2552 entry.polarity = active_high_low;
2553 entry.mask = 1;
2554
2555 /*
2556 * IRQs < 16 are already in the irq_2_pin[] map
2557 */
2558 if (irq >= 16)
2559 add_pin_to_irq(irq, ioapic, pin);
2560
2561 entry.vector = assign_irq_vector(irq);
2562
2563 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2564 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2565 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2566 edge_level, active_high_low);
2567
2568 ioapic_register_intr(irq, entry.vector, edge_level);
2569
2570 if (!ioapic && (irq < 16))
2571 disable_8259A_irq(irq);
2572
2573 spin_lock_irqsave(&ioapic_lock, flags);
2574 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2575 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
54d5d424 2576 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
1da177e4
LT		 2577 spin_unlock_irqrestore(&ioapic_lock, flags);
2578
2579 return 0;
2580}
2581
888ba6c6 2582#endif /* CONFIG_ACPI */
Linux 6.x block layer and io_uring tree(s)