[linux-2.6-block.git] / arch / i386 / kernel / cpu / cpufreq / cpufreq-nforce2.c

/*
 * (C) 2004  Sebastian Witt <se.witt@gmx.net>
 *
 *  Licensed under the terms of the GNU GPL License version 2.
 *  Based upon reverse engineered information
 *
 *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/pci.h>
#include <linux/delay.h>

#define NFORCE2_XTAL 25
#define NFORCE2_BOOTFSB 0x48
#define NFORCE2_PLLENABLE 0xa8
#define NFORCE2_PLLREG 0xa4
#define NFORCE2_PLLADR 0xa0
#define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)

#define NFORCE2_MIN_FSB 50
#define NFORCE2_SAFE_DISTANCE 50

/* Delay in ms between FSB changes */
//#define NFORCE2_DELAY 10

/* nforce2_chipset:
 * FSB is changed using the chipset
 */
static struct pci_dev *nforce2_chipset_dev;

/* fid:
 * multiplier * 10
 */
static int fid = 0;

/* min_fsb, max_fsb:
 * minimum and maximum FSB (= FSB at boot time) 
 */
static int min_fsb = 0;
static int max_fsb = 0;

MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
MODULE_LICENSE("GPL");

module_param(fid, int, 0444);
module_param(min_fsb, int, 0444);

MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
MODULE_PARM_DESC(min_fsb,
                 "Minimum FSB to use, if not defined: current FSB - 50");

#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)

/*
 * nforce2_calc_fsb - calculate FSB
 * @pll: PLL value
 * 
 *   Calculates FSB from PLL value
 */
static int nforce2_calc_fsb(int pll)
{
	unsigned char mul, div;

	mul = (pll >> 8) & 0xff;
	div = pll & 0xff;

	if (div > 0)
		return NFORCE2_XTAL * mul / div;

	return 0;
}

/*
 * nforce2_calc_pll - calculate PLL value
 * @fsb: FSB
 * 
 *   Calculate PLL value for given FSB
 */
static int nforce2_calc_pll(unsigned int fsb)
{
	unsigned char xmul, xdiv;
	unsigned char mul = 0, div = 0;
	int tried = 0;

	/* Try to calculate multiplier and divider up to 4 times */
	while (((mul == 0) || (div == 0)) && (tried <= 3)) {
		for (xdiv = 1; xdiv <= 0x80; xdiv++)
			for (xmul = 1; xmul <= 0xfe; xmul++)
				if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
				    fsb + tried) {
					mul = xmul;
					div = xdiv;
				}
		tried++;
	}

	if ((mul == 0) || (div == 0))
		return -1;

	return NFORCE2_PLL(mul, div);
}

/*
 * nforce2_write_pll - write PLL value to chipset
 * @pll: PLL value
 * 
 *   Writes new FSB PLL value to chipset
 */
static void nforce2_write_pll(int pll)
{
	int temp;

	/* Set the pll addr. to 0x00 */
	temp = 0x00;
	pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);

	/* Now write the value in all 64 registers */
	for (temp = 0; temp <= 0x3f; temp++) {
		pci_write_config_dword(nforce2_chipset_dev, 
                                       NFORCE2_PLLREG, pll);
	}

	return;
}

/*
 * nforce2_fsb_read - Read FSB
 *
 *   Read FSB from chipset
 *   If bootfsb != 0, return FSB at boot-time
 */
static unsigned int nforce2_fsb_read(int bootfsb)
{
	struct pci_dev *nforce2_sub5;
	u32 fsb, temp = 0;

	
	/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
	nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
                                      0x01EF,
                                      PCI_ANY_ID,
                                      PCI_ANY_ID,
                                      NULL);
	
	if (!nforce2_sub5)
		return 0;

	pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
	fsb /= 1000000;
	
	/* Check if PLL register is already set */
	pci_read_config_byte(nforce2_chipset_dev, 
                             NFORCE2_PLLENABLE, (u8 *)&temp);
	
	if(bootfsb || !temp)
		return fsb;
		
	/* Use PLL register FSB value */
	pci_read_config_dword(nforce2_chipset_dev, 
                              NFORCE2_PLLREG, &temp);
	fsb = nforce2_calc_fsb(temp);

	return fsb;
}

/*
 * nforce2_set_fsb - set new FSB
 * @fsb: New FSB
 * 
 *   Sets new FSB
 */
static int nforce2_set_fsb(unsigned int fsb)
{
	u32 temp = 0;
	unsigned int tfsb;
	int diff;
	int pll = 0;

	if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
		printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
		return -EINVAL;
	}
	
	tfsb = nforce2_fsb_read(0);
	if (!tfsb) {
		printk(KERN_ERR "cpufreq: Error while reading the FSB\n");
		return -EINVAL;
	}

	/* First write? Then set actual value */
	pci_read_config_byte(nforce2_chipset_dev, 
                             NFORCE2_PLLENABLE, (u8 *)&temp);
	if (!temp) {
		pll = nforce2_calc_pll(tfsb);

		if (pll < 0)
			return -EINVAL;

		nforce2_write_pll(pll);
	}

	/* Enable write access */
	temp = 0x01;
	pci_write_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8)temp);

	diff = tfsb - fsb;

	if (!diff)
		return 0;

	while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
		if (diff < 0)
			tfsb++;
		else
			tfsb--;

		/* Calculate the PLL reg. value */
		if ((pll = nforce2_calc_pll(tfsb)) == -1)
			return -EINVAL;
		
		nforce2_write_pll(pll);
#ifdef NFORCE2_DELAY
		mdelay(NFORCE2_DELAY);
#endif
	}

	temp = 0x40;
	pci_write_config_byte(nforce2_chipset_dev, NFORCE2_PLLADR, (u8)temp);

	return 0;
}

/**
 * nforce2_get - get the CPU frequency
 * @cpu: CPU number
 * 
 * Returns the CPU frequency
 */
static unsigned int nforce2_get(unsigned int cpu)
{
	if (cpu)
		return 0;
	return nforce2_fsb_read(0) * fid * 100;
}

/**
 * nforce2_target - set a new CPUFreq policy
 * @policy: new policy
 * @target_freq: the target frequency
 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 *
 * Sets a new CPUFreq policy.
 */
static int nforce2_target(struct cpufreq_policy *policy,
			  unsigned int target_freq, unsigned int relation)
{
//        unsigned long         flags;
	struct cpufreq_freqs freqs;
	unsigned int target_fsb;

	if ((target_freq > policy->max) || (target_freq < policy->min))
		return -EINVAL;

	target_fsb = target_freq / (fid * 100);

	freqs.old = nforce2_get(policy->cpu);
	freqs.new = target_fsb * fid * 100;
	freqs.cpu = 0;		/* Only one CPU on nForce2 plattforms */

	if (freqs.old == freqs.new)
		return 0;

	dprintk(KERN_INFO "cpufreq: Old CPU frequency %d kHz, new %d kHz\n",
	       freqs.old, freqs.new);

	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);

	/* Disable IRQs */
	//local_irq_save(flags);

	if (nforce2_set_fsb(target_fsb) < 0)
		printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n",
                       target_fsb);
	else
		dprintk(KERN_INFO "cpufreq: Changed FSB successfully to %d\n",
                       target_fsb);

	/* Enable IRQs */
	//local_irq_restore(flags);

	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);

	return 0;
}

/**
 * nforce2_verify - verifies a new CPUFreq policy
 * @policy: new policy
 */
static int nforce2_verify(struct cpufreq_policy *policy)
{
	unsigned int fsb_pol_max;

	fsb_pol_max = policy->max / (fid * 100);

	if (policy->min < (fsb_pol_max * fid * 100))
		policy->max = (fsb_pol_max + 1) * fid * 100;

	cpufreq_verify_within_limits(policy,
                                     policy->cpuinfo.min_freq,
                                     policy->cpuinfo.max_freq);
	return 0;
}

static int nforce2_cpu_init(struct cpufreq_policy *policy)
{
	unsigned int fsb;
	unsigned int rfid;

	/* capability check */
	if (policy->cpu != 0)
		return -ENODEV;

	/* Get current FSB */
	fsb = nforce2_fsb_read(0);

	if (!fsb)
		return -EIO;

	/* FIX: Get FID from CPU */
	if (!fid) {
		if (!cpu_khz) {
			printk(KERN_WARNING
			       "cpufreq: cpu_khz not set, can't calculate multiplier!\n");
			return -ENODEV;
		}

		fid = cpu_khz / (fsb * 100);
		rfid = fid % 5;

		if (rfid) {
			if (rfid > 2)
				fid += 5 - rfid;
			else
				fid -= rfid;
		}
	}

	printk(KERN_INFO "cpufreq: FSB currently at %i MHz, FID %d.%d\n", fsb,
	       fid / 10, fid % 10);
	
	/* Set maximum FSB to FSB at boot time */
	max_fsb = nforce2_fsb_read(1);
	
	if(!max_fsb)
		return -EIO;

	if (!min_fsb)
		min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;

	if (min_fsb < NFORCE2_MIN_FSB)
		min_fsb = NFORCE2_MIN_FSB;

	/* cpuinfo and default policy values */
	policy->cpuinfo.min_freq = min_fsb * fid * 100;
	policy->cpuinfo.max_freq = max_fsb * fid * 100;
	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
	policy->cur = nforce2_get(policy->cpu);
	policy->min = policy->cpuinfo.min_freq;
	policy->max = policy->cpuinfo.max_freq;
	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;

	return 0;
}

static int nforce2_cpu_exit(struct cpufreq_policy *policy)
{
	return 0;
}

static struct cpufreq_driver nforce2_driver = {
	.name = "nforce2",
	.verify = nforce2_verify,
	.target = nforce2_target,
	.get = nforce2_get,
	.init = nforce2_cpu_init,
	.exit = nforce2_cpu_exit,
	.owner = THIS_MODULE,
};

/**
 * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
 *
 * Detects nForce2 A2 and C1 stepping
 * 
 */
static unsigned int nforce2_detect_chipset(void)
{
	u8 revision;

	nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
                                             PCI_DEVICE_ID_NVIDIA_NFORCE2,
                                             PCI_ANY_ID,
                                             PCI_ANY_ID,
                                             NULL);

	if (nforce2_chipset_dev == NULL)
		return -ENODEV;

	pci_read_config_byte(nforce2_chipset_dev, PCI_REVISION_ID, &revision);

	printk(KERN_INFO "cpufreq: Detected nForce2 chipset revision %X\n",
	       revision);
	printk(KERN_INFO
	       "cpufreq: FSB changing is maybe unstable and can lead to crashes and data loss.\n");

	return 0;
}

/**
 * nforce2_init - initializes the nForce2 CPUFreq driver
 *
 * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
 * devices, -EINVAL on problems during initiatization, and zero on
 * success.
 */
static int __init nforce2_init(void)
{
	/* TODO: do we need to detect the processor? */

	/* detect chipset */
	if (nforce2_detect_chipset()) {
		printk(KERN_ERR "cpufreq: No nForce2 chipset.\n");
		return -ENODEV;
	}

	return cpufreq_register_driver(&nforce2_driver);
}

/**
 * nforce2_exit - unregisters cpufreq module
 *
 *   Unregisters nForce2 FSB change support.
 */
static void __exit nforce2_exit(void)
{
	cpufreq_unregister_driver(&nforce2_driver);
}

module_init(nforce2_init);
module_exit(nforce2_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* (C) 2004 Sebastian Witt <se.witt@gmx.net>
	3	*
	4	* Licensed under the terms of the GNU GPL License version 2.
	5	* Based upon reverse engineered information
	6	*
	7	* BIG FAT DISCLAIMER: Work in progress code. Possibly dangerous
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/moduleparam.h>
	13	#include <linux/init.h>
	14	#include <linux/cpufreq.h>
	15	#include <linux/pci.h>
	16	#include <linux/delay.h>
	17
	18	#define NFORCE2_XTAL 25
	19	#define NFORCE2_BOOTFSB 0x48
	20	#define NFORCE2_PLLENABLE 0xa8
	21	#define NFORCE2_PLLREG 0xa4
	22	#define NFORCE2_PLLADR 0xa0
	23	#define NFORCE2_PLL(mul, div) (0x100000 \| (mul << 8) \| div)
	24
	25	#define NFORCE2_MIN_FSB 50
	26	#define NFORCE2_SAFE_DISTANCE 50
	27
	28	/* Delay in ms between FSB changes */
	29	//#define NFORCE2_DELAY 10
	30
	31	/* nforce2_chipset:
	32	* FSB is changed using the chipset
	33	*/
	34	static struct pci_dev *nforce2_chipset_dev;
	35
	36	/* fid:
	37	* multiplier * 10
	38	*/
	39	static int fid = 0;
	40
	41	/* min_fsb, max_fsb:
	42	* minimum and maximum FSB (= FSB at boot time)
	43	*/
	44	static int min_fsb = 0;
	45	static int max_fsb = 0;
	46
	47	MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
	48	MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
	49	MODULE_LICENSE("GPL");
	50
	51	module_param(fid, int, 0444);
	52	module_param(min_fsb, int, 0444);
	53
	54	MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
	55	MODULE_PARM_DESC(min_fsb,
	56	"Minimum FSB to use, if not defined: current FSB - 50");
	57
	58	#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
	59
	60	/*
	61	* nforce2_calc_fsb - calculate FSB
	62	* @pll: PLL value
	63	*
	64	* Calculates FSB from PLL value
65	*/
66	static int nforce2_calc_fsb(int pll)
67	{
68	unsigned char mul, div;
69
70	mul = (pll >> 8) & 0xff;
71	div = pll & 0xff;
72
73	if (div > 0)
74	return NFORCE2_XTAL * mul / div;
75
76	return 0;
77	}
78
79	/*
80	* nforce2_calc_pll - calculate PLL value
81	* @fsb: FSB
82	*
83	* Calculate PLL value for given FSB
84	*/
85	static int nforce2_calc_pll(unsigned int fsb)
86	{
87	unsigned char xmul, xdiv;
88	unsigned char mul = 0, div = 0;
89	int tried = 0;
90
91	/* Try to calculate multiplier and divider up to 4 times */
92	while (((mul == 0) \|\| (div == 0)) && (tried <= 3)) {
93	for (xdiv = 1; xdiv <= 0x80; xdiv++)
94	for (xmul = 1; xmul <= 0xfe; xmul++)
95	if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
96	fsb + tried) {
97	mul = xmul;
98	div = xdiv;
99	}
100	tried++;
101	}
102
103	if ((mul == 0) \|\| (div == 0))
104	return -1;
105
106	return NFORCE2_PLL(mul, div);
107	}
108
109	/*
110	* nforce2_write_pll - write PLL value to chipset
111	* @pll: PLL value
112	*
113	* Writes new FSB PLL value to chipset
114	*/
115	static void nforce2_write_pll(int pll)
116	{
117	int temp;
118
119	/* Set the pll addr. to 0x00 */
120	temp = 0x00;
121	pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
122
123	/* Now write the value in all 64 registers */
124	for (temp = 0; temp <= 0x3f; temp++) {
125	pci_write_config_dword(nforce2_chipset_dev,
126	NFORCE2_PLLREG, pll);
127	}
128
129	return;
130	}
131
132	/*
133	* nforce2_fsb_read - Read FSB
134	*
135	* Read FSB from chipset
136	* If bootfsb != 0, return FSB at boot-time
137	*/
138	static unsigned int nforce2_fsb_read(int bootfsb)
139	{
140	struct pci_dev *nforce2_sub5;
141	u32 fsb, temp = 0;
142
143
144	/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
145	nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
146	0x01EF,
147	PCI_ANY_ID,
148	PCI_ANY_ID,
149	NULL);
150
151	if (!nforce2_sub5)
152	return 0;
153
154	pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
155	fsb /= 1000000;
156
157	/* Check if PLL register is already set */
158	pci_read_config_byte(nforce2_chipset_dev,
159	NFORCE2_PLLENABLE, (u8 *)&temp);
160
161	if(bootfsb \|\| !temp)
162	return fsb;
163
164	/* Use PLL register FSB value */
165	pci_read_config_dword(nforce2_chipset_dev,
166	NFORCE2_PLLREG, &temp);
167	fsb = nforce2_calc_fsb(temp);
168
169	return fsb;
170	}
171
172	/*
173	* nforce2_set_fsb - set new FSB
174	* @fsb: New FSB
175	*
176	* Sets new FSB
177	*/
178	static int nforce2_set_fsb(unsigned int fsb)
179	{
d4921914	180	u32 temp = 0;
1da177e4 LT	181	unsigned int tfsb;
1da177e4 LT	182	int diff;
d4921914	183	int pll = 0;
1da177e4 LT	184
	185	if ((fsb > max_fsb) \|\| (fsb < NFORCE2_MIN_FSB)) {
	186	printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
	187	return -EINVAL;
	188	}
	189
	190	tfsb = nforce2_fsb_read(0);
	191	if (!tfsb) {
	192	printk(KERN_ERR "cpufreq: Error while reading the FSB\n");
	193	return -EINVAL;
	194	}
	195
	196	/* First write? Then set actual value */
	197	pci_read_config_byte(nforce2_chipset_dev,
	198	NFORCE2_PLLENABLE, (u8 *)&temp);
	199	if (!temp) {
	200	pll = nforce2_calc_pll(tfsb);
	201
	202	if (pll < 0)
	203	return -EINVAL;
	204
	205	nforce2_write_pll(pll);
	206	}
	207
	208	/* Enable write access */
	209	temp = 0x01;
	210	pci_write_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8)temp);
	211
	212	diff = tfsb - fsb;
	213
	214	if (!diff)
	215	return 0;
	216
	217	while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
	218	if (diff < 0)
	219	tfsb++;
	220	else
	221	tfsb--;
	222
	223	/* Calculate the PLL reg. value */
	224	if ((pll = nforce2_calc_pll(tfsb)) == -1)
	225	return -EINVAL;
	226
	227	nforce2_write_pll(pll);
	228	#ifdef NFORCE2_DELAY
	229	mdelay(NFORCE2_DELAY);
	230	#endif
	231	}
	232
	233	temp = 0x40;
	234	pci_write_config_byte(nforce2_chipset_dev, NFORCE2_PLLADR, (u8)temp);
	235
	236	return 0;
	237	}
	238
	239	/**
	240	* nforce2_get - get the CPU frequency
	241	* @cpu: CPU number
	242	*
	243	* Returns the CPU frequency
	244	*/
	245	static unsigned int nforce2_get(unsigned int cpu)
	246	{
	247	if (cpu)
248	return 0;
249	return nforce2_fsb_read(0) * fid * 100;
250	}
251
252	/**
253	* nforce2_target - set a new CPUFreq policy
254	* @policy: new policy
255	* @target_freq: the target frequency
256	* @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
257	*
258	* Sets a new CPUFreq policy.
259	*/
260	static int nforce2_target(struct cpufreq_policy *policy,
261	unsigned int target_freq, unsigned int relation)
262	{
263	// unsigned long flags;
264	struct cpufreq_freqs freqs;
265	unsigned int target_fsb;
266
267	if ((target_freq > policy->max) \|\| (target_freq < policy->min))
268	return -EINVAL;
269
270	target_fsb = target_freq / (fid * 100);
271
272	freqs.old = nforce2_get(policy->cpu);
273	freqs.new = target_fsb * fid * 100;
274	freqs.cpu = 0; /* Only one CPU on nForce2 plattforms */
275
276	if (freqs.old == freqs.new)
277	return 0;
278
279	dprintk(KERN_INFO "cpufreq: Old CPU frequency %d kHz, new %d kHz\n",
280	freqs.old, freqs.new);
281
282	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
283
284	/* Disable IRQs */
285	//local_irq_save(flags);
286
287	if (nforce2_set_fsb(target_fsb) < 0)
288	printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n",
289	target_fsb);
290	else
291	dprintk(KERN_INFO "cpufreq: Changed FSB successfully to %d\n",
292	target_fsb);
293
294	/* Enable IRQs */
295	//local_irq_restore(flags);
296
297	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
298
299	return 0;
300	}
301
302	/**
303	* nforce2_verify - verifies a new CPUFreq policy
304	* @policy: new policy
305	*/
306	static int nforce2_verify(struct cpufreq_policy *policy)
307	{
308	unsigned int fsb_pol_max;
309
310	fsb_pol_max = policy->max / (fid * 100);
311
312	if (policy->min < (fsb_pol_max * fid * 100))
313	policy->max = (fsb_pol_max + 1) * fid * 100;
314
315	cpufreq_verify_within_limits(policy,
316	policy->cpuinfo.min_freq,
317	policy->cpuinfo.max_freq);
318	return 0;
319	}
320
321	static int nforce2_cpu_init(struct cpufreq_policy *policy)
322	{
323	unsigned int fsb;
324	unsigned int rfid;
325
326	/* capability check */
327	if (policy->cpu != 0)
328	return -ENODEV;
329
330	/* Get current FSB */
331	fsb = nforce2_fsb_read(0);
332
333	if (!fsb)
334	return -EIO;
335
336	/* FIX: Get FID from CPU */
337	if (!fid) {
338	if (!cpu_khz) {
339	printk(KERN_WARNING
340	"cpufreq: cpu_khz not set, can't calculate multiplier!\n");
341	return -ENODEV;
342	}
343
344	fid = cpu_khz / (fsb * 100);
345	rfid = fid % 5;
346
347	if (rfid) {
348	if (rfid > 2)
349	fid += 5 - rfid;
350	else
351	fid -= rfid;
352	}
353	}
354
355	printk(KERN_INFO "cpufreq: FSB currently at %i MHz, FID %d.%d\n", fsb,
356	fid / 10, fid % 10);
357
358	/* Set maximum FSB to FSB at boot time */
359	max_fsb = nforce2_fsb_read(1);
360
361	if(!max_fsb)
362	return -EIO;
363
364	if (!min_fsb)
365	min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;
366
367	if (min_fsb < NFORCE2_MIN_FSB)
368	min_fsb = NFORCE2_MIN_FSB;
369
370	/* cpuinfo and default policy values */
371	policy->cpuinfo.min_freq = min_fsb * fid * 100;
372	policy->cpuinfo.max_freq = max_fsb * fid * 100;
373	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
374	policy->cur = nforce2_get(policy->cpu);
375	policy->min = policy->cpuinfo.min_freq;
376	policy->max = policy->cpuinfo.max_freq;
377	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
378
379	return 0;
380	}
381
382	static int nforce2_cpu_exit(struct cpufreq_policy *policy)
383	{
384	return 0;
385	}
386
387	static struct cpufreq_driver nforce2_driver = {
388	.name = "nforce2",
389	.verify = nforce2_verify,
390	.target = nforce2_target,
391	.get = nforce2_get,
392	.init = nforce2_cpu_init,
393	.exit = nforce2_cpu_exit,
394	.owner = THIS_MODULE,
395	};
396
397	/**
398	* nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
399	*
400	* Detects nForce2 A2 and C1 stepping
401	*
402	*/
403	static unsigned int nforce2_detect_chipset(void)
404	{
405	u8 revision;
406
407	nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
408	PCI_DEVICE_ID_NVIDIA_NFORCE2,
409	PCI_ANY_ID,
410	PCI_ANY_ID,
411	NULL);
412
413	if (nforce2_chipset_dev == NULL)
414	return -ENODEV;
415
416	pci_read_config_byte(nforce2_chipset_dev, PCI_REVISION_ID, &revision);
417
418	printk(KERN_INFO "cpufreq: Detected nForce2 chipset revision %X\n",
419	revision);
420	printk(KERN_INFO
421	"cpufreq: FSB changing is maybe unstable and can lead to crashes and data loss.\n");
422
423	return 0;
424	}
425
426	/**
427	* nforce2_init - initializes the nForce2 CPUFreq driver
428	*
429	* Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
430	* devices, -EINVAL on problems during initiatization, and zero on
431	* success.
432	*/
433	static int __init nforce2_init(void)
434	{
435	/* TODO: do we need to detect the processor? */
436
437	/* detect chipset */
438	if (nforce2_detect_chipset()) {
439	printk(KERN_ERR "cpufreq: No nForce2 chipset.\n");
440	return -ENODEV;
441	}
442
443	return cpufreq_register_driver(&nforce2_driver);
444	}
445
446	/**
447	* nforce2_exit - unregisters cpufreq module
448	*
449	* Unregisters nForce2 FSB change support.
450	*/
451	static void __exit nforce2_exit(void)
452	{
453	cpufreq_unregister_driver(&nforce2_driver);
454	}
455
456	module_init(nforce2_init);
457	module_exit(nforce2_exit);
458