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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/string.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
7 | #include <asm/semaphore.h> | |
8 | #include <asm/processor.h> | |
9 | #include <asm/i387.h> | |
10 | #include <asm/msr.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/mmu_context.h> | |
13 | #ifdef CONFIG_X86_LOCAL_APIC | |
14 | #include <asm/mpspec.h> | |
15 | #include <asm/apic.h> | |
16 | #include <mach_apic.h> | |
17 | #endif | |
18 | ||
19 | #include "cpu.h" | |
20 | ||
21 | DEFINE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]); | |
22 | EXPORT_PER_CPU_SYMBOL(cpu_gdt_table); | |
23 | ||
24 | DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]); | |
25 | EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack); | |
26 | ||
0bb3184d LS |
27 | static int cachesize_override __devinitdata = -1; |
28 | static int disable_x86_fxsr __devinitdata = 0; | |
29 | static int disable_x86_serial_nr __devinitdata = 1; | |
1da177e4 LT |
30 | |
31 | struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {}; | |
32 | ||
33 | extern void mcheck_init(struct cpuinfo_x86 *c); | |
34 | ||
35 | extern int disable_pse; | |
36 | ||
37 | static void default_init(struct cpuinfo_x86 * c) | |
38 | { | |
39 | /* Not much we can do here... */ | |
40 | /* Check if at least it has cpuid */ | |
41 | if (c->cpuid_level == -1) { | |
42 | /* No cpuid. It must be an ancient CPU */ | |
43 | if (c->x86 == 4) | |
44 | strcpy(c->x86_model_id, "486"); | |
45 | else if (c->x86 == 3) | |
46 | strcpy(c->x86_model_id, "386"); | |
47 | } | |
48 | } | |
49 | ||
50 | static struct cpu_dev default_cpu = { | |
51 | .c_init = default_init, | |
52 | }; | |
53 | static struct cpu_dev * this_cpu = &default_cpu; | |
54 | ||
55 | static int __init cachesize_setup(char *str) | |
56 | { | |
57 | get_option (&str, &cachesize_override); | |
58 | return 1; | |
59 | } | |
60 | __setup("cachesize=", cachesize_setup); | |
61 | ||
0bb3184d | 62 | int __devinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
63 | { |
64 | unsigned int *v; | |
65 | char *p, *q; | |
66 | ||
67 | if (cpuid_eax(0x80000000) < 0x80000004) | |
68 | return 0; | |
69 | ||
70 | v = (unsigned int *) c->x86_model_id; | |
71 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
72 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
73 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
74 | c->x86_model_id[48] = 0; | |
75 | ||
76 | /* Intel chips right-justify this string for some dumb reason; | |
77 | undo that brain damage */ | |
78 | p = q = &c->x86_model_id[0]; | |
79 | while ( *p == ' ' ) | |
80 | p++; | |
81 | if ( p != q ) { | |
82 | while ( *p ) | |
83 | *q++ = *p++; | |
84 | while ( q <= &c->x86_model_id[48] ) | |
85 | *q++ = '\0'; /* Zero-pad the rest */ | |
86 | } | |
87 | ||
88 | return 1; | |
89 | } | |
90 | ||
91 | ||
0bb3184d | 92 | void __devinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 LT |
93 | { |
94 | unsigned int n, dummy, ecx, edx, l2size; | |
95 | ||
96 | n = cpuid_eax(0x80000000); | |
97 | ||
98 | if (n >= 0x80000005) { | |
99 | cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); | |
100 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", | |
101 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
102 | c->x86_cache_size=(ecx>>24)+(edx>>24); | |
103 | } | |
104 | ||
105 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
106 | return; | |
107 | ||
108 | ecx = cpuid_ecx(0x80000006); | |
109 | l2size = ecx >> 16; | |
110 | ||
111 | /* do processor-specific cache resizing */ | |
112 | if (this_cpu->c_size_cache) | |
113 | l2size = this_cpu->c_size_cache(c,l2size); | |
114 | ||
115 | /* Allow user to override all this if necessary. */ | |
116 | if (cachesize_override != -1) | |
117 | l2size = cachesize_override; | |
118 | ||
119 | if ( l2size == 0 ) | |
120 | return; /* Again, no L2 cache is possible */ | |
121 | ||
122 | c->x86_cache_size = l2size; | |
123 | ||
124 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
125 | l2size, ecx & 0xFF); | |
126 | } | |
127 | ||
128 | /* Naming convention should be: <Name> [(<Codename>)] */ | |
129 | /* This table only is used unless init_<vendor>() below doesn't set it; */ | |
130 | /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */ | |
131 | ||
132 | /* Look up CPU names by table lookup. */ | |
0bb3184d | 133 | static char __devinit *table_lookup_model(struct cpuinfo_x86 *c) |
1da177e4 LT |
134 | { |
135 | struct cpu_model_info *info; | |
136 | ||
137 | if ( c->x86_model >= 16 ) | |
138 | return NULL; /* Range check */ | |
139 | ||
140 | if (!this_cpu) | |
141 | return NULL; | |
142 | ||
143 | info = this_cpu->c_models; | |
144 | ||
145 | while (info && info->family) { | |
146 | if (info->family == c->x86) | |
147 | return info->model_names[c->x86_model]; | |
148 | info++; | |
149 | } | |
150 | return NULL; /* Not found */ | |
151 | } | |
152 | ||
153 | ||
672289e9 | 154 | static void __devinit get_cpu_vendor(struct cpuinfo_x86 *c, int early) |
1da177e4 LT |
155 | { |
156 | char *v = c->x86_vendor_id; | |
157 | int i; | |
158 | ||
159 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
160 | if (cpu_devs[i]) { | |
161 | if (!strcmp(v,cpu_devs[i]->c_ident[0]) || | |
162 | (cpu_devs[i]->c_ident[1] && | |
163 | !strcmp(v,cpu_devs[i]->c_ident[1]))) { | |
164 | c->x86_vendor = i; | |
165 | if (!early) | |
166 | this_cpu = cpu_devs[i]; | |
167 | break; | |
168 | } | |
169 | } | |
170 | } | |
171 | } | |
172 | ||
173 | ||
174 | static int __init x86_fxsr_setup(char * s) | |
175 | { | |
176 | disable_x86_fxsr = 1; | |
177 | return 1; | |
178 | } | |
179 | __setup("nofxsr", x86_fxsr_setup); | |
180 | ||
181 | ||
182 | /* Standard macro to see if a specific flag is changeable */ | |
183 | static inline int flag_is_changeable_p(u32 flag) | |
184 | { | |
185 | u32 f1, f2; | |
186 | ||
187 | asm("pushfl\n\t" | |
188 | "pushfl\n\t" | |
189 | "popl %0\n\t" | |
190 | "movl %0,%1\n\t" | |
191 | "xorl %2,%0\n\t" | |
192 | "pushl %0\n\t" | |
193 | "popfl\n\t" | |
194 | "pushfl\n\t" | |
195 | "popl %0\n\t" | |
196 | "popfl\n\t" | |
197 | : "=&r" (f1), "=&r" (f2) | |
198 | : "ir" (flag)); | |
199 | ||
200 | return ((f1^f2) & flag) != 0; | |
201 | } | |
202 | ||
203 | ||
204 | /* Probe for the CPUID instruction */ | |
0bb3184d | 205 | static int __devinit have_cpuid_p(void) |
1da177e4 LT |
206 | { |
207 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
208 | } | |
209 | ||
210 | /* Do minimum CPU detection early. | |
211 | Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment. | |
212 | The others are not touched to avoid unwanted side effects. */ | |
213 | static void __init early_cpu_detect(void) | |
214 | { | |
215 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
216 | ||
217 | c->x86_cache_alignment = 32; | |
218 | ||
219 | if (!have_cpuid_p()) | |
220 | return; | |
221 | ||
222 | /* Get vendor name */ | |
223 | cpuid(0x00000000, &c->cpuid_level, | |
224 | (int *)&c->x86_vendor_id[0], | |
225 | (int *)&c->x86_vendor_id[8], | |
226 | (int *)&c->x86_vendor_id[4]); | |
227 | ||
228 | get_cpu_vendor(c, 1); | |
229 | ||
230 | c->x86 = 4; | |
231 | if (c->cpuid_level >= 0x00000001) { | |
232 | u32 junk, tfms, cap0, misc; | |
233 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
234 | c->x86 = (tfms >> 8) & 15; | |
235 | c->x86_model = (tfms >> 4) & 15; | |
236 | if (c->x86 == 0xf) { | |
237 | c->x86 += (tfms >> 20) & 0xff; | |
238 | c->x86_model += ((tfms >> 16) & 0xF) << 4; | |
239 | } | |
240 | c->x86_mask = tfms & 15; | |
241 | if (cap0 & (1<<19)) | |
242 | c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8; | |
243 | } | |
244 | ||
245 | early_intel_workaround(c); | |
a158608b | 246 | |
a158608b | 247 | #ifdef CONFIG_X86_HT |
b41e2939 | 248 | phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff; |
a158608b | 249 | #endif |
1da177e4 LT |
250 | } |
251 | ||
0bb3184d | 252 | void __devinit generic_identify(struct cpuinfo_x86 * c) |
1da177e4 LT |
253 | { |
254 | u32 tfms, xlvl; | |
255 | int junk; | |
256 | ||
257 | if (have_cpuid_p()) { | |
258 | /* Get vendor name */ | |
259 | cpuid(0x00000000, &c->cpuid_level, | |
260 | (int *)&c->x86_vendor_id[0], | |
261 | (int *)&c->x86_vendor_id[8], | |
262 | (int *)&c->x86_vendor_id[4]); | |
263 | ||
264 | get_cpu_vendor(c, 0); | |
265 | /* Initialize the standard set of capabilities */ | |
266 | /* Note that the vendor-specific code below might override */ | |
267 | ||
268 | /* Intel-defined flags: level 0x00000001 */ | |
269 | if ( c->cpuid_level >= 0x00000001 ) { | |
270 | u32 capability, excap; | |
271 | cpuid(0x00000001, &tfms, &junk, &excap, &capability); | |
272 | c->x86_capability[0] = capability; | |
273 | c->x86_capability[4] = excap; | |
274 | c->x86 = (tfms >> 8) & 15; | |
275 | c->x86_model = (tfms >> 4) & 15; | |
276 | if (c->x86 == 0xf) { | |
277 | c->x86 += (tfms >> 20) & 0xff; | |
278 | c->x86_model += ((tfms >> 16) & 0xF) << 4; | |
279 | } | |
280 | c->x86_mask = tfms & 15; | |
281 | } else { | |
282 | /* Have CPUID level 0 only - unheard of */ | |
283 | c->x86 = 4; | |
284 | } | |
285 | ||
286 | /* AMD-defined flags: level 0x80000001 */ | |
287 | xlvl = cpuid_eax(0x80000000); | |
288 | if ( (xlvl & 0xffff0000) == 0x80000000 ) { | |
289 | if ( xlvl >= 0x80000001 ) { | |
290 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
291 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
292 | } | |
293 | if ( xlvl >= 0x80000004 ) | |
294 | get_model_name(c); /* Default name */ | |
295 | } | |
296 | } | |
297 | } | |
298 | ||
0bb3184d | 299 | static void __devinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
1da177e4 LT |
300 | { |
301 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) { | |
302 | /* Disable processor serial number */ | |
303 | unsigned long lo,hi; | |
304 | rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
305 | lo |= 0x200000; | |
306 | wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
307 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
308 | clear_bit(X86_FEATURE_PN, c->x86_capability); | |
309 | ||
310 | /* Disabling the serial number may affect the cpuid level */ | |
311 | c->cpuid_level = cpuid_eax(0); | |
312 | } | |
313 | } | |
314 | ||
315 | static int __init x86_serial_nr_setup(char *s) | |
316 | { | |
317 | disable_x86_serial_nr = 0; | |
318 | return 1; | |
319 | } | |
320 | __setup("serialnumber", x86_serial_nr_setup); | |
321 | ||
322 | ||
323 | ||
324 | /* | |
325 | * This does the hard work of actually picking apart the CPU stuff... | |
326 | */ | |
0bb3184d | 327 | void __devinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
328 | { |
329 | int i; | |
330 | ||
331 | c->loops_per_jiffy = loops_per_jiffy; | |
332 | c->x86_cache_size = -1; | |
333 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
334 | c->cpuid_level = -1; /* CPUID not detected */ | |
335 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
336 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
337 | c->x86_model_id[0] = '\0'; /* Unset */ | |
338 | c->x86_num_cores = 1; | |
339 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
340 | ||
341 | if (!have_cpuid_p()) { | |
342 | /* First of all, decide if this is a 486 or higher */ | |
343 | /* It's a 486 if we can modify the AC flag */ | |
344 | if ( flag_is_changeable_p(X86_EFLAGS_AC) ) | |
345 | c->x86 = 4; | |
346 | else | |
347 | c->x86 = 3; | |
348 | } | |
349 | ||
350 | generic_identify(c); | |
351 | ||
352 | printk(KERN_DEBUG "CPU: After generic identify, caps:"); | |
353 | for (i = 0; i < NCAPINTS; i++) | |
354 | printk(" %08lx", c->x86_capability[i]); | |
355 | printk("\n"); | |
356 | ||
357 | if (this_cpu->c_identify) { | |
358 | this_cpu->c_identify(c); | |
359 | ||
360 | printk(KERN_DEBUG "CPU: After vendor identify, caps:"); | |
361 | for (i = 0; i < NCAPINTS; i++) | |
362 | printk(" %08lx", c->x86_capability[i]); | |
363 | printk("\n"); | |
364 | } | |
365 | ||
366 | /* | |
367 | * Vendor-specific initialization. In this section we | |
368 | * canonicalize the feature flags, meaning if there are | |
369 | * features a certain CPU supports which CPUID doesn't | |
370 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
371 | * we handle them here. | |
372 | * | |
373 | * At the end of this section, c->x86_capability better | |
374 | * indicate the features this CPU genuinely supports! | |
375 | */ | |
376 | if (this_cpu->c_init) | |
377 | this_cpu->c_init(c); | |
378 | ||
379 | /* Disable the PN if appropriate */ | |
380 | squash_the_stupid_serial_number(c); | |
381 | ||
382 | /* | |
383 | * The vendor-specific functions might have changed features. Now | |
384 | * we do "generic changes." | |
385 | */ | |
386 | ||
387 | /* TSC disabled? */ | |
388 | if ( tsc_disable ) | |
389 | clear_bit(X86_FEATURE_TSC, c->x86_capability); | |
390 | ||
391 | /* FXSR disabled? */ | |
392 | if (disable_x86_fxsr) { | |
393 | clear_bit(X86_FEATURE_FXSR, c->x86_capability); | |
394 | clear_bit(X86_FEATURE_XMM, c->x86_capability); | |
395 | } | |
396 | ||
397 | if (disable_pse) | |
398 | clear_bit(X86_FEATURE_PSE, c->x86_capability); | |
399 | ||
400 | /* If the model name is still unset, do table lookup. */ | |
401 | if ( !c->x86_model_id[0] ) { | |
402 | char *p; | |
403 | p = table_lookup_model(c); | |
404 | if ( p ) | |
405 | strcpy(c->x86_model_id, p); | |
406 | else | |
407 | /* Last resort... */ | |
408 | sprintf(c->x86_model_id, "%02x/%02x", | |
409 | c->x86_vendor, c->x86_model); | |
410 | } | |
411 | ||
412 | /* Now the feature flags better reflect actual CPU features! */ | |
413 | ||
414 | printk(KERN_DEBUG "CPU: After all inits, caps:"); | |
415 | for (i = 0; i < NCAPINTS; i++) | |
416 | printk(" %08lx", c->x86_capability[i]); | |
417 | printk("\n"); | |
418 | ||
419 | /* | |
420 | * On SMP, boot_cpu_data holds the common feature set between | |
421 | * all CPUs; so make sure that we indicate which features are | |
422 | * common between the CPUs. The first time this routine gets | |
423 | * executed, c == &boot_cpu_data. | |
424 | */ | |
425 | if ( c != &boot_cpu_data ) { | |
426 | /* AND the already accumulated flags with these */ | |
427 | for ( i = 0 ; i < NCAPINTS ; i++ ) | |
428 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
429 | } | |
430 | ||
431 | /* Init Machine Check Exception if available. */ | |
432 | #ifdef CONFIG_X86_MCE | |
433 | mcheck_init(c); | |
434 | #endif | |
6fe940d6 LS |
435 | if (c == &boot_cpu_data) |
436 | sysenter_setup(); | |
437 | enable_sep_cpu(); | |
3b520b23 SL |
438 | |
439 | if (c == &boot_cpu_data) | |
440 | mtrr_bp_init(); | |
441 | else | |
442 | mtrr_ap_init(); | |
1da177e4 LT |
443 | } |
444 | ||
445 | #ifdef CONFIG_X86_HT | |
0bb3184d | 446 | void __devinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 LT |
447 | { |
448 | u32 eax, ebx, ecx, edx; | |
3dd9d514 | 449 | int index_msb, tmp; |
1da177e4 LT |
450 | int cpu = smp_processor_id(); |
451 | ||
63518644 | 452 | if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
1da177e4 LT |
453 | return; |
454 | ||
455 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
456 | smp_num_siblings = (ebx & 0xff0000) >> 16; | |
457 | ||
458 | if (smp_num_siblings == 1) { | |
459 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
460 | } else if (smp_num_siblings > 1 ) { | |
1da177e4 LT |
461 | index_msb = 31; |
462 | ||
463 | if (smp_num_siblings > NR_CPUS) { | |
464 | printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings); | |
465 | smp_num_siblings = 1; | |
466 | return; | |
467 | } | |
468 | tmp = smp_num_siblings; | |
1da177e4 LT |
469 | while ((tmp & 0x80000000 ) == 0) { |
470 | tmp <<=1 ; | |
471 | index_msb--; | |
472 | } | |
3dd9d514 | 473 | if (smp_num_siblings & (smp_num_siblings - 1)) |
1da177e4 LT |
474 | index_msb++; |
475 | phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb); | |
476 | ||
477 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
478 | phys_proc_id[cpu]); | |
3dd9d514 AK |
479 | |
480 | smp_num_siblings = smp_num_siblings / c->x86_num_cores; | |
481 | ||
482 | tmp = smp_num_siblings; | |
483 | index_msb = 31; | |
484 | while ((tmp & 0x80000000) == 0) { | |
485 | tmp <<=1 ; | |
486 | index_msb--; | |
487 | } | |
488 | ||
489 | if (smp_num_siblings & (smp_num_siblings - 1)) | |
490 | index_msb++; | |
491 | ||
492 | cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb); | |
493 | ||
494 | if (c->x86_num_cores > 1) | |
495 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
496 | cpu_core_id[cpu]); | |
1da177e4 LT |
497 | } |
498 | } | |
499 | #endif | |
500 | ||
0bb3184d | 501 | void __devinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
502 | { |
503 | char *vendor = NULL; | |
504 | ||
505 | if (c->x86_vendor < X86_VENDOR_NUM) | |
506 | vendor = this_cpu->c_vendor; | |
507 | else if (c->cpuid_level >= 0) | |
508 | vendor = c->x86_vendor_id; | |
509 | ||
510 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
511 | printk("%s ", vendor); | |
512 | ||
513 | if (!c->x86_model_id[0]) | |
514 | printk("%d86", c->x86); | |
515 | else | |
516 | printk("%s", c->x86_model_id); | |
517 | ||
518 | if (c->x86_mask || c->cpuid_level >= 0) | |
519 | printk(" stepping %02x\n", c->x86_mask); | |
520 | else | |
521 | printk("\n"); | |
522 | } | |
523 | ||
0bb3184d | 524 | cpumask_t cpu_initialized __devinitdata = CPU_MASK_NONE; |
1da177e4 LT |
525 | |
526 | /* This is hacky. :) | |
527 | * We're emulating future behavior. | |
528 | * In the future, the cpu-specific init functions will be called implicitly | |
529 | * via the magic of initcalls. | |
530 | * They will insert themselves into the cpu_devs structure. | |
531 | * Then, when cpu_init() is called, we can just iterate over that array. | |
532 | */ | |
533 | ||
534 | extern int intel_cpu_init(void); | |
535 | extern int cyrix_init_cpu(void); | |
536 | extern int nsc_init_cpu(void); | |
537 | extern int amd_init_cpu(void); | |
538 | extern int centaur_init_cpu(void); | |
539 | extern int transmeta_init_cpu(void); | |
540 | extern int rise_init_cpu(void); | |
541 | extern int nexgen_init_cpu(void); | |
542 | extern int umc_init_cpu(void); | |
543 | ||
544 | void __init early_cpu_init(void) | |
545 | { | |
546 | intel_cpu_init(); | |
547 | cyrix_init_cpu(); | |
548 | nsc_init_cpu(); | |
549 | amd_init_cpu(); | |
550 | centaur_init_cpu(); | |
551 | transmeta_init_cpu(); | |
552 | rise_init_cpu(); | |
553 | nexgen_init_cpu(); | |
554 | umc_init_cpu(); | |
555 | early_cpu_detect(); | |
556 | ||
557 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
558 | /* pse is not compatible with on-the-fly unmapping, | |
559 | * disable it even if the cpus claim to support it. | |
560 | */ | |
561 | clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability); | |
562 | disable_pse = 1; | |
563 | #endif | |
564 | } | |
565 | /* | |
566 | * cpu_init() initializes state that is per-CPU. Some data is already | |
567 | * initialized (naturally) in the bootstrap process, such as the GDT | |
568 | * and IDT. We reload them nevertheless, this function acts as a | |
569 | * 'CPU state barrier', nothing should get across. | |
570 | */ | |
0bb3184d | 571 | void __devinit cpu_init(void) |
1da177e4 LT |
572 | { |
573 | int cpu = smp_processor_id(); | |
574 | struct tss_struct * t = &per_cpu(init_tss, cpu); | |
575 | struct thread_struct *thread = ¤t->thread; | |
251e6912 | 576 | struct desc_struct *gdt = get_cpu_gdt_table(cpu); |
1da177e4 LT |
577 | __u32 stk16_off = (__u32)&per_cpu(cpu_16bit_stack, cpu); |
578 | ||
579 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
580 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
581 | for (;;) local_irq_enable(); | |
582 | } | |
583 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
584 | ||
585 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
586 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
587 | if (tsc_disable && cpu_has_tsc) { | |
588 | printk(KERN_NOTICE "Disabling TSC...\n"); | |
589 | /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/ | |
590 | clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability); | |
591 | set_in_cr4(X86_CR4_TSD); | |
592 | } | |
593 | ||
594 | /* | |
595 | * Initialize the per-CPU GDT with the boot GDT, | |
596 | * and set up the GDT descriptor: | |
597 | */ | |
251e6912 | 598 | memcpy(gdt, cpu_gdt_table, GDT_SIZE); |
1da177e4 LT |
599 | |
600 | /* Set up GDT entry for 16bit stack */ | |
251e6912 | 601 | *(__u64 *)(&gdt[GDT_ENTRY_ESPFIX_SS]) |= |
1da177e4 LT |
602 | ((((__u64)stk16_off) << 16) & 0x000000ffffff0000ULL) | |
603 | ((((__u64)stk16_off) << 32) & 0xff00000000000000ULL) | | |
604 | (CPU_16BIT_STACK_SIZE - 1); | |
605 | ||
606 | cpu_gdt_descr[cpu].size = GDT_SIZE - 1; | |
251e6912 | 607 | cpu_gdt_descr[cpu].address = (unsigned long)gdt; |
1da177e4 | 608 | |
4d37e7e3 ZA |
609 | load_gdt(&cpu_gdt_descr[cpu]); |
610 | load_idt(&idt_descr); | |
1da177e4 LT |
611 | |
612 | /* | |
613 | * Delete NT | |
614 | */ | |
615 | __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl"); | |
616 | ||
617 | /* | |
618 | * Set up and load the per-CPU TSS and LDT | |
619 | */ | |
620 | atomic_inc(&init_mm.mm_count); | |
621 | current->active_mm = &init_mm; | |
622 | if (current->mm) | |
623 | BUG(); | |
624 | enter_lazy_tlb(&init_mm, current); | |
625 | ||
626 | load_esp0(t, thread); | |
627 | set_tss_desc(cpu,t); | |
628 | load_TR_desc(); | |
629 | load_LDT(&init_mm.context); | |
630 | ||
631 | /* Set up doublefault TSS pointer in the GDT */ | |
632 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
633 | ||
634 | /* Clear %fs and %gs. */ | |
635 | asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs"); | |
636 | ||
637 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
638 | set_debugreg(0, 0); |
639 | set_debugreg(0, 1); | |
640 | set_debugreg(0, 2); | |
641 | set_debugreg(0, 3); | |
642 | set_debugreg(0, 6); | |
643 | set_debugreg(0, 7); | |
1da177e4 LT |
644 | |
645 | /* | |
646 | * Force FPU initialization: | |
647 | */ | |
648 | current_thread_info()->status = 0; | |
649 | clear_used_math(); | |
650 | mxcsr_feature_mask_init(); | |
651 | } | |
e1367daf LS |
652 | |
653 | #ifdef CONFIG_HOTPLUG_CPU | |
654 | void __devinit cpu_uninit(void) | |
655 | { | |
656 | int cpu = raw_smp_processor_id(); | |
657 | cpu_clear(cpu, cpu_initialized); | |
658 | ||
659 | /* lazy TLB state */ | |
660 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
661 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
662 | } | |
663 | #endif |