Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
f3705136 | 26 | #include <linux/cpu.h> |
e9e2cdb4 | 27 | #include <linux/clockchips.h> |
d36b49b9 | 28 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 29 | #include <linux/module.h> |
ad62ca2b | 30 | #include <linux/dmi.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/arch_hooks.h> | |
38 | #include <asm/hpet.h> | |
306e440d | 39 | #include <asm/i8253.h> |
3e4ff115 | 40 | #include <asm/nmi.h> |
1da177e4 LT |
41 | |
42 | #include <mach_apic.h> | |
382dbd07 | 43 | #include <mach_apicdef.h> |
6eb0a0fd | 44 | #include <mach_ipi.h> |
1da177e4 LT |
45 | |
46 | #include "io_ports.h" | |
47 | ||
e05d723f TG |
48 | /* |
49 | * Sanity check | |
50 | */ | |
51 | #if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F | |
52 | # error SPURIOUS_APIC_VECTOR definition error | |
53 | #endif | |
54 | ||
9635b47d EB |
55 | /* |
56 | * Knob to control our willingness to enable the local APIC. | |
e05d723f TG |
57 | * |
58 | * -1=force-disable, +1=force-enable | |
9635b47d | 59 | */ |
e05d723f | 60 | static int enable_local_apic __initdata = 0; |
9635b47d | 61 | |
d36b49b9 TG |
62 | /* Local APIC timer verification ok */ |
63 | static int local_apic_timer_verify_ok; | |
d3f7eae1 AK |
64 | /* Disable local APIC timer from the kernel commandline or via dmi quirk |
65 | or using CPU MSR check */ | |
66 | int local_apic_timer_disabled; | |
e585bef8 TG |
67 | /* Local APIC timer works in C2 */ |
68 | int local_apic_timer_c2_ok; | |
69 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
e9e2cdb4 | 70 | |
1da177e4 | 71 | /* |
e05d723f | 72 | * Debug level, exported for io_apic.c |
1da177e4 LT |
73 | */ |
74 | int apic_verbosity; | |
75 | ||
e9e2cdb4 | 76 | static unsigned int calibration_result; |
1da177e4 | 77 | |
e9e2cdb4 TG |
78 | static int lapic_next_event(unsigned long delta, |
79 | struct clock_event_device *evt); | |
80 | static void lapic_timer_setup(enum clock_event_mode mode, | |
81 | struct clock_event_device *evt); | |
82 | static void lapic_timer_broadcast(cpumask_t mask); | |
83 | static void apic_pm_activate(void); | |
e05d723f | 84 | |
e9e2cdb4 TG |
85 | /* |
86 | * The local apic timer can be used for any function which is CPU local. | |
87 | */ | |
88 | static struct clock_event_device lapic_clockevent = { | |
89 | .name = "lapic", | |
90 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 91 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
92 | .shift = 32, |
93 | .set_mode = lapic_timer_setup, | |
94 | .set_next_event = lapic_next_event, | |
95 | .broadcast = lapic_timer_broadcast, | |
96 | .rating = 100, | |
97 | .irq = -1, | |
98 | }; | |
99 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f TG |
100 | |
101 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
102 | static int enabled_via_apicbase; | |
103 | ||
104 | /* | |
105 | * Get the LAPIC version | |
106 | */ | |
107 | static inline int lapic_get_version(void) | |
95d769aa | 108 | { |
e05d723f | 109 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
110 | } |
111 | ||
1da177e4 | 112 | /* |
e05d723f | 113 | * Check, if the APIC is integrated or a seperate chip |
1da177e4 | 114 | */ |
e05d723f | 115 | static inline int lapic_is_integrated(void) |
1da177e4 | 116 | { |
e05d723f | 117 | return APIC_INTEGRATED(lapic_get_version()); |
1da177e4 LT |
118 | } |
119 | ||
e05d723f TG |
120 | /* |
121 | * Check, whether this is a modern or a first generation APIC | |
122 | */ | |
123 | static int modern_apic(void) | |
1da177e4 | 124 | { |
e05d723f TG |
125 | /* AMD systems use old APIC versions, so check the CPU */ |
126 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
127 | boot_cpu_data.x86 >= 0xf) | |
128 | return 1; | |
129 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
130 | } |
131 | ||
f2b218dd FLV |
132 | void apic_wait_icr_idle(void) |
133 | { | |
134 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
135 | cpu_relax(); | |
136 | } | |
137 | ||
138 | unsigned long safe_apic_wait_icr_idle(void) | |
139 | { | |
140 | unsigned long send_status; | |
141 | int timeout; | |
142 | ||
143 | timeout = 0; | |
144 | do { | |
145 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
146 | if (!send_status) | |
147 | break; | |
148 | udelay(100); | |
149 | } while (timeout++ < 1000); | |
150 | ||
151 | return send_status; | |
152 | } | |
153 | ||
e05d723f TG |
154 | /** |
155 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
156 | */ | |
1da177e4 LT |
157 | void enable_NMI_through_LVT0 (void * dummy) |
158 | { | |
e05d723f | 159 | unsigned int v = APIC_DM_NMI; |
1da177e4 | 160 | |
e05d723f TG |
161 | /* Level triggered for 82489DX */ |
162 | if (!lapic_is_integrated()) | |
1da177e4 LT |
163 | v |= APIC_LVT_LEVEL_TRIGGER; |
164 | apic_write_around(APIC_LVT0, v); | |
165 | } | |
166 | ||
e05d723f TG |
167 | /** |
168 | * get_physical_broadcast - Get number of physical broadcast IDs | |
169 | */ | |
1da177e4 LT |
170 | int get_physical_broadcast(void) |
171 | { | |
e05d723f | 172 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
173 | } |
174 | ||
e05d723f TG |
175 | /** |
176 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
177 | */ | |
178 | int lapic_get_maxlvt(void) | |
1da177e4 | 179 | { |
e05d723f | 180 | unsigned int v = apic_read(APIC_LVR); |
1da177e4 | 181 | |
1da177e4 | 182 | /* 82489DXs do not report # of LVT entries. */ |
e05d723f | 183 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
184 | } |
185 | ||
e05d723f TG |
186 | /* |
187 | * Local APIC timer | |
188 | */ | |
189 | ||
d36b49b9 TG |
190 | /* Clock divisor is set to 16 */ |
191 | #define APIC_DIVISOR 16 | |
e05d723f TG |
192 | |
193 | /* | |
194 | * This function sets up the local APIC timer, with a timeout of | |
195 | * 'clocks' APIC bus clock. During calibration we actually call | |
196 | * this function twice on the boot CPU, once with a bogus timeout | |
197 | * value, second time for real. The other (noncalibrating) CPUs | |
198 | * call this function only once, with the real, calibrated value. | |
199 | * | |
200 | * We do reads before writes even if unnecessary, to get around the | |
201 | * P5 APIC double write bug. | |
202 | */ | |
e9e2cdb4 | 203 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 204 | { |
e05d723f | 205 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 206 | |
e9e2cdb4 TG |
207 | lvtt_value = LOCAL_TIMER_VECTOR; |
208 | if (!oneshot) | |
209 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
210 | if (!lapic_is_integrated()) |
211 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
212 | ||
e9e2cdb4 | 213 | if (!irqen) |
e05d723f TG |
214 | lvtt_value |= APIC_LVT_MASKED; |
215 | ||
216 | apic_write_around(APIC_LVTT, lvtt_value); | |
1da177e4 LT |
217 | |
218 | /* | |
e05d723f | 219 | * Divide PICLK by 16 |
1da177e4 | 220 | */ |
e05d723f TG |
221 | tmp_value = apic_read(APIC_TDCR); |
222 | apic_write_around(APIC_TDCR, (tmp_value | |
223 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
224 | | APIC_TDR_DIV_16); | |
1da177e4 | 225 | |
e9e2cdb4 TG |
226 | if (!oneshot) |
227 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
228 | } | |
229 | ||
230 | /* | |
231 | * Program the next event, relative to now | |
232 | */ | |
233 | static int lapic_next_event(unsigned long delta, | |
234 | struct clock_event_device *evt) | |
235 | { | |
236 | apic_write_around(APIC_TMICT, delta); | |
237 | return 0; | |
1da177e4 LT |
238 | } |
239 | ||
e9e2cdb4 TG |
240 | /* |
241 | * Setup the lapic timer in periodic or oneshot mode | |
242 | */ | |
243 | static void lapic_timer_setup(enum clock_event_mode mode, | |
244 | struct clock_event_device *evt) | |
1da177e4 | 245 | { |
e05d723f | 246 | unsigned long flags; |
e9e2cdb4 | 247 | unsigned int v; |
e05d723f | 248 | |
d36b49b9 TG |
249 | /* Lapic used for broadcast ? */ |
250 | if (!local_apic_timer_verify_ok) | |
251 | return; | |
252 | ||
e05d723f | 253 | local_irq_save(flags); |
1da177e4 | 254 | |
e9e2cdb4 TG |
255 | switch (mode) { |
256 | case CLOCK_EVT_MODE_PERIODIC: | |
257 | case CLOCK_EVT_MODE_ONESHOT: | |
258 | __setup_APIC_LVTT(calibration_result, | |
259 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
260 | break; | |
261 | case CLOCK_EVT_MODE_UNUSED: | |
262 | case CLOCK_EVT_MODE_SHUTDOWN: | |
263 | v = apic_read(APIC_LVTT); | |
264 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
265 | apic_write_around(APIC_LVTT, v); | |
266 | break; | |
18de5bc4 TG |
267 | case CLOCK_EVT_MODE_RESUME: |
268 | /* Nothing to do here */ | |
269 | break; | |
e9e2cdb4 | 270 | } |
e05d723f TG |
271 | |
272 | local_irq_restore(flags); | |
273 | } | |
274 | ||
e9e2cdb4 TG |
275 | /* |
276 | * Local APIC timer broadcast function | |
277 | */ | |
278 | static void lapic_timer_broadcast(cpumask_t mask) | |
279 | { | |
280 | #ifdef CONFIG_SMP | |
281 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
282 | #endif | |
283 | } | |
284 | ||
285 | /* | |
286 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
287 | * of the boot CPU and register the clock event in the framework. | |
288 | */ | |
289 | static void __devinit setup_APIC_timer(void) | |
290 | { | |
291 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
292 | ||
293 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
294 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
295 | ||
296 | clockevents_register_device(levt); | |
297 | } | |
298 | ||
e05d723f | 299 | /* |
d36b49b9 TG |
300 | * In this functions we calibrate APIC bus clocks to the external timer. |
301 | * | |
302 | * We want to do the calibration only once since we want to have local timer | |
303 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
304 | * frequency. | |
305 | * | |
306 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
307 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
308 | * readout is broken, so it never gets out of the wait loop again. This was | |
309 | * also reported by others. | |
e05d723f | 310 | * |
d36b49b9 TG |
311 | * Monitoring the jiffies value is inaccurate and the clockevents |
312 | * infrastructure allows us to do a simple substitution of the interrupt | |
313 | * handler. | |
e9e2cdb4 | 314 | * |
d36b49b9 TG |
315 | * The calibration routine also uses the pm_timer when possible, as the PIT |
316 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
317 | * back to normal later in the boot process). | |
e05d723f TG |
318 | */ |
319 | ||
d36b49b9 | 320 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 321 | |
f5352fd0 | 322 | static __initdata int lapic_cal_loops = -1; |
d36b49b9 TG |
323 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
324 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
325 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
326 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 327 | |
d36b49b9 TG |
328 | /* |
329 | * Temporary interrupt handler. | |
330 | */ | |
331 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
332 | { | |
333 | unsigned long long tsc = 0; | |
334 | long tapic = apic_read(APIC_TMCCT); | |
335 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 336 | |
d36b49b9 TG |
337 | if (cpu_has_tsc) |
338 | rdtscll(tsc); | |
339 | ||
340 | switch (lapic_cal_loops++) { | |
341 | case 0: | |
342 | lapic_cal_t1 = tapic; | |
343 | lapic_cal_tsc1 = tsc; | |
344 | lapic_cal_pm1 = pm; | |
345 | lapic_cal_j1 = jiffies; | |
346 | break; | |
e05d723f | 347 | |
d36b49b9 TG |
348 | case LAPIC_CAL_LOOPS: |
349 | lapic_cal_t2 = tapic; | |
350 | lapic_cal_tsc2 = tsc; | |
351 | if (pm < lapic_cal_pm1) | |
352 | pm += ACPI_PM_OVRRUN; | |
353 | lapic_cal_pm2 = pm; | |
354 | lapic_cal_j2 = jiffies; | |
355 | break; | |
356 | } | |
357 | } | |
1da177e4 | 358 | |
d36b49b9 TG |
359 | /* |
360 | * Setup the boot APIC | |
361 | * | |
362 | * Calibrate and verify the result. | |
363 | */ | |
364 | void __init setup_boot_APIC_clock(void) | |
365 | { | |
366 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
367 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
368 | const long pm_thresh = pm_100ms/100; | |
369 | void (*real_handler)(struct clock_event_device *dev); | |
370 | unsigned long deltaj; | |
371 | long delta, deltapm; | |
ca1b940c | 372 | int pm_referenced = 0; |
1da177e4 | 373 | |
ad62ca2b TG |
374 | /* |
375 | * The local apic timer can be disabled via the kernel | |
d3f7eae1 | 376 | * commandline or from the CPU detection code. Register the lapic |
ad62ca2b TG |
377 | * timer as a dummy clock event source on SMP systems, so the |
378 | * broadcast mechanism is used. On UP systems simply ignore it. | |
379 | */ | |
380 | if (local_apic_timer_disabled) { | |
381 | /* No broadcast on UP ! */ | |
382 | if (num_possible_cpus() > 1) | |
383 | setup_APIC_timer(); | |
384 | return; | |
385 | } | |
386 | ||
d36b49b9 TG |
387 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
388 | "calibrating APIC timer ...\n"); | |
1da177e4 | 389 | |
d36b49b9 TG |
390 | local_irq_disable(); |
391 | ||
392 | /* Replace the global interrupt handler */ | |
393 | real_handler = global_clock_event->event_handler; | |
394 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 395 | |
1da177e4 | 396 | /* |
d36b49b9 TG |
397 | * Setup the APIC counter to 1e9. There is no way the lapic |
398 | * can underflow in the 100ms detection time frame | |
1da177e4 | 399 | */ |
d36b49b9 | 400 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 401 | |
d36b49b9 TG |
402 | /* Let the interrupts run */ |
403 | local_irq_enable(); | |
404 | ||
ca1b940c TG |
405 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
406 | cpu_relax(); | |
d36b49b9 TG |
407 | |
408 | local_irq_disable(); | |
409 | ||
410 | /* Restore the real event handler */ | |
411 | global_clock_event->event_handler = real_handler; | |
412 | ||
413 | /* Build delta t1-t2 as apic timer counts down */ | |
414 | delta = lapic_cal_t1 - lapic_cal_t2; | |
415 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
416 | ||
417 | /* Check, if the PM timer is available */ | |
418 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
419 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
420 | ||
421 | if (deltapm) { | |
422 | unsigned long mult; | |
423 | u64 res; | |
424 | ||
425 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
426 | ||
427 | if (deltapm > (pm_100ms - pm_thresh) && | |
428 | deltapm < (pm_100ms + pm_thresh)) { | |
429 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
430 | } else { | |
431 | res = (((u64) deltapm) * mult) >> 22; | |
432 | do_div(res, 1000000); | |
433 | printk(KERN_WARNING "APIC calibration not consistent " | |
434 | "with PM Timer: %ldms instead of 100ms\n", | |
435 | (long)res); | |
436 | /* Correct the lapic counter value */ | |
437 | res = (((u64) delta ) * pm_100ms); | |
438 | do_div(res, deltapm); | |
439 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
440 | "%lu (%ld)\n", (unsigned long) res, delta); | |
441 | delta = (long) res; | |
442 | } | |
ca1b940c | 443 | pm_referenced = 1; |
d36b49b9 | 444 | } |
e05d723f | 445 | |
e9e2cdb4 | 446 | /* Calculate the scaled math multiplication factor */ |
d36b49b9 | 447 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 32); |
e9e2cdb4 TG |
448 | lapic_clockevent.max_delta_ns = |
449 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
450 | lapic_clockevent.min_delta_ns = | |
451 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
452 | ||
d36b49b9 TG |
453 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
454 | ||
455 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 456 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
457 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
458 | calibration_result); | |
e9e2cdb4 | 459 | |
d36b49b9 TG |
460 | if (cpu_has_tsc) { |
461 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 462 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
463 | "%ld.%04ld MHz.\n", |
464 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
465 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
466 | } | |
e05d723f TG |
467 | |
468 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
469 | "%u.%04u MHz.\n", |
470 | calibration_result / (1000000 / HZ), | |
471 | calibration_result % (1000000 / HZ)); | |
e05d723f | 472 | |
d36b49b9 | 473 | local_apic_timer_verify_ok = 1; |
d36b49b9 | 474 | |
ca1b940c TG |
475 | /* We trust the pm timer based calibration */ |
476 | if (!pm_referenced) { | |
477 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
d36b49b9 | 478 | |
ca1b940c TG |
479 | /* |
480 | * Setup the apic timer manually | |
481 | */ | |
482 | levt->event_handler = lapic_cal_handler; | |
483 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
484 | lapic_cal_loops = -1; | |
d36b49b9 | 485 | |
ca1b940c TG |
486 | /* Let the interrupts run */ |
487 | local_irq_enable(); | |
d36b49b9 | 488 | |
f5352fd0 | 489 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
ca1b940c | 490 | cpu_relax(); |
d36b49b9 | 491 | |
ca1b940c | 492 | local_irq_disable(); |
d36b49b9 | 493 | |
ca1b940c TG |
494 | /* Stop the lapic timer */ |
495 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
d36b49b9 | 496 | |
ca1b940c | 497 | local_irq_enable(); |
d36b49b9 | 498 | |
ca1b940c TG |
499 | /* Jiffies delta */ |
500 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
501 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
d36b49b9 | 502 | |
d36b49b9 | 503 | /* Check, if the jiffies result is consistent */ |
ca1b940c | 504 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
d36b49b9 | 505 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
ca1b940c TG |
506 | else |
507 | local_apic_timer_verify_ok = 0; | |
4edc5db8 IM |
508 | } else |
509 | local_irq_enable(); | |
e05d723f | 510 | |
d36b49b9 TG |
511 | if (!local_apic_timer_verify_ok) { |
512 | printk(KERN_WARNING | |
513 | "APIC timer disabled due to verification failure.\n"); | |
514 | /* No broadcast on UP ! */ | |
515 | if (num_possible_cpus() == 1) | |
516 | return; | |
a5f5e43e TG |
517 | } else { |
518 | /* | |
519 | * If nmi_watchdog is set to IO_APIC, we need the | |
520 | * PIT/HPET going. Otherwise register lapic as a dummy | |
521 | * device. | |
522 | */ | |
523 | if (nmi_watchdog != NMI_IO_APIC) | |
524 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
820de5c3 IM |
525 | else |
526 | printk(KERN_WARNING "APIC timer registered as dummy," | |
527 | " due to nmi_watchdog=1!\n"); | |
a5f5e43e | 528 | } |
d36b49b9 TG |
529 | |
530 | /* Setup the lapic or request the broadcast */ | |
531 | setup_APIC_timer(); | |
e05d723f | 532 | } |
1da177e4 | 533 | |
e05d723f TG |
534 | void __devinit setup_secondary_APIC_clock(void) |
535 | { | |
e9e2cdb4 | 536 | setup_APIC_timer(); |
e05d723f | 537 | } |
1da177e4 | 538 | |
e05d723f | 539 | /* |
e9e2cdb4 | 540 | * The guts of the apic timer interrupt |
e05d723f | 541 | */ |
e9e2cdb4 | 542 | static void local_apic_timer_interrupt(void) |
e05d723f | 543 | { |
e9e2cdb4 TG |
544 | int cpu = smp_processor_id(); |
545 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
546 | |
547 | /* | |
d36b49b9 TG |
548 | * Normally we should not be here till LAPIC has been initialized but |
549 | * in some cases like kdump, its possible that there is a pending LAPIC | |
550 | * timer interrupt from previous kernel's context and is delivered in | |
551 | * new kernel the moment interrupts are enabled. | |
e05d723f | 552 | * |
d36b49b9 TG |
553 | * Interrupts are enabled early and LAPIC is setup much later, hence |
554 | * its possible that when we get here evt->event_handler is NULL. | |
555 | * Check for event_handler being NULL and discard the interrupt as | |
556 | * spurious. | |
1da177e4 | 557 | */ |
e9e2cdb4 TG |
558 | if (!evt->event_handler) { |
559 | printk(KERN_WARNING | |
560 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
561 | /* Switch it off */ | |
562 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
563 | return; | |
564 | } | |
565 | ||
566 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
567 | ||
568 | evt->event_handler(evt); | |
e05d723f TG |
569 | } |
570 | ||
571 | /* | |
572 | * Local APIC timer interrupt. This is the most natural way for doing | |
573 | * local interrupts, but local timer interrupts can be emulated by | |
574 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
575 | * | |
576 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
577 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
578 | */ | |
579 | ||
e9e2cdb4 | 580 | void fastcall smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
581 | { |
582 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
583 | |
584 | /* | |
e05d723f TG |
585 | * NOTE! We'd better ACK the irq immediately, |
586 | * because timer handling can be slow. | |
1da177e4 | 587 | */ |
e05d723f | 588 | ack_APIC_irq(); |
1a75a3f0 | 589 | /* |
e05d723f TG |
590 | * update_process_times() expects us to have done irq_enter(). |
591 | * Besides, if we don't timer interrupts ignore the global | |
592 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 593 | */ |
e05d723f | 594 | irq_enter(); |
e9e2cdb4 | 595 | local_apic_timer_interrupt(); |
e05d723f | 596 | irq_exit(); |
1a75a3f0 | 597 | |
e9e2cdb4 | 598 | set_irq_regs(old_regs); |
e05d723f TG |
599 | } |
600 | ||
601 | int setup_profiling_timer(unsigned int multiplier) | |
602 | { | |
603 | return -EINVAL; | |
604 | } | |
605 | ||
606 | /* | |
607 | * Local APIC start and shutdown | |
608 | */ | |
609 | ||
610 | /** | |
611 | * clear_local_APIC - shutdown the local APIC | |
612 | * | |
613 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
614 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
615 | * leftovers during boot. | |
616 | */ | |
617 | void clear_local_APIC(void) | |
618 | { | |
619 | int maxlvt = lapic_get_maxlvt(); | |
620 | unsigned long v; | |
1da177e4 LT |
621 | |
622 | /* | |
e05d723f TG |
623 | * Masking an LVT entry can trigger a local APIC error |
624 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 625 | */ |
e05d723f TG |
626 | if (maxlvt >= 3) { |
627 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
628 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
629 | } | |
1da177e4 | 630 | /* |
e05d723f TG |
631 | * Careful: we have to set masks only first to deassert |
632 | * any level-triggered sources. | |
1da177e4 | 633 | */ |
e05d723f TG |
634 | v = apic_read(APIC_LVTT); |
635 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
636 | v = apic_read(APIC_LVT0); | |
637 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
638 | v = apic_read(APIC_LVT1); | |
639 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
640 | if (maxlvt >= 4) { | |
641 | v = apic_read(APIC_LVTPC); | |
642 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1da177e4 | 643 | } |
1da177e4 | 644 | |
e05d723f TG |
645 | /* lets not touch this if we didn't frob it */ |
646 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
647 | if (maxlvt >= 5) { | |
648 | v = apic_read(APIC_LVTTHMR); | |
649 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
650 | } | |
651 | #endif | |
1da177e4 | 652 | /* |
e05d723f | 653 | * Clean APIC state for other OSs: |
1da177e4 | 654 | */ |
e05d723f TG |
655 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); |
656 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
657 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
658 | if (maxlvt >= 3) | |
659 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
660 | if (maxlvt >= 4) | |
661 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
1da177e4 | 662 | |
e05d723f TG |
663 | #ifdef CONFIG_X86_MCE_P4THERMAL |
664 | if (maxlvt >= 5) | |
665 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
666 | #endif | |
667 | /* Integrated APIC (!82489DX) ? */ | |
668 | if (lapic_is_integrated()) { | |
1da177e4 | 669 | if (maxlvt > 3) |
e05d723f | 670 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 671 | apic_write(APIC_ESR, 0); |
e05d723f | 672 | apic_read(APIC_ESR); |
1da177e4 | 673 | } |
e05d723f | 674 | } |
1da177e4 | 675 | |
e05d723f TG |
676 | /** |
677 | * disable_local_APIC - clear and disable the local APIC | |
678 | */ | |
679 | void disable_local_APIC(void) | |
680 | { | |
681 | unsigned long value; | |
682 | ||
683 | clear_local_APIC(); | |
684 | ||
685 | /* | |
686 | * Disable APIC (implies clearing of registers | |
687 | * for 82489DX!). | |
688 | */ | |
689 | value = apic_read(APIC_SPIV); | |
690 | value &= ~APIC_SPIV_APIC_ENABLED; | |
691 | apic_write_around(APIC_SPIV, value); | |
692 | ||
693 | /* | |
694 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
695 | * restore the disabled state. | |
696 | */ | |
697 | if (enabled_via_apicbase) { | |
698 | unsigned int l, h; | |
699 | ||
700 | rdmsr(MSR_IA32_APICBASE, l, h); | |
701 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
702 | wrmsr(MSR_IA32_APICBASE, l, h); | |
703 | } | |
1da177e4 LT |
704 | } |
705 | ||
706 | /* | |
e05d723f TG |
707 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
708 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
709 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 710 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
711 | */ |
712 | void lapic_shutdown(void) | |
713 | { | |
67963132 MS |
714 | unsigned long flags; |
715 | ||
77f72b19 | 716 | if (!cpu_has_apic) |
1da177e4 LT |
717 | return; |
718 | ||
67963132 | 719 | local_irq_save(flags); |
77f72b19 ZM |
720 | clear_local_APIC(); |
721 | ||
722 | if (enabled_via_apicbase) | |
723 | disable_local_APIC(); | |
724 | ||
67963132 | 725 | local_irq_restore(flags); |
1da177e4 LT |
726 | } |
727 | ||
e05d723f TG |
728 | /* |
729 | * This is to verify that we're looking at a real local APIC. | |
730 | * Check these against your board if the CPUs aren't getting | |
731 | * started for no apparent reason. | |
732 | */ | |
733 | int __init verify_local_APIC(void) | |
1da177e4 | 734 | { |
e05d723f | 735 | unsigned int reg0, reg1; |
1da177e4 | 736 | |
e05d723f TG |
737 | /* |
738 | * The version register is read-only in a real APIC. | |
739 | */ | |
740 | reg0 = apic_read(APIC_LVR); | |
741 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
742 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
743 | reg1 = apic_read(APIC_LVR); | |
744 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
745 | ||
746 | /* | |
747 | * The two version reads above should print the same | |
748 | * numbers. If the second one is different, then we | |
749 | * poke at a non-APIC. | |
750 | */ | |
751 | if (reg1 != reg0) | |
1da177e4 LT |
752 | return 0; |
753 | ||
e05d723f TG |
754 | /* |
755 | * Check if the version looks reasonably. | |
756 | */ | |
757 | reg1 = GET_APIC_VERSION(reg0); | |
758 | if (reg1 == 0x00 || reg1 == 0xff) | |
759 | return 0; | |
760 | reg1 = lapic_get_maxlvt(); | |
761 | if (reg1 < 0x02 || reg1 == 0xff) | |
762 | return 0; | |
f990fff4 | 763 | |
e05d723f TG |
764 | /* |
765 | * The ID register is read/write in a real APIC. | |
766 | */ | |
767 | reg0 = apic_read(APIC_ID); | |
768 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
769 | ||
770 | /* | |
771 | * The next two are just to see if we have sane values. | |
772 | * They're only really relevant if we're in Virtual Wire | |
773 | * compatibility mode, but most boxes are anymore. | |
774 | */ | |
775 | reg0 = apic_read(APIC_LVT0); | |
776 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
777 | reg1 = apic_read(APIC_LVT1); | |
778 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
779 | ||
780 | return 1; | |
1da177e4 LT |
781 | } |
782 | ||
e05d723f TG |
783 | /** |
784 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
785 | */ | |
786 | void __init sync_Arb_IDs(void) | |
1da177e4 | 787 | { |
e05d723f TG |
788 | /* |
789 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
790 | * needed on AMD. | |
791 | */ | |
792 | if (modern_apic()) | |
793 | return; | |
794 | /* | |
795 | * Wait for idle. | |
796 | */ | |
797 | apic_wait_icr_idle(); | |
1da177e4 | 798 | |
e05d723f TG |
799 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
800 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
801 | | APIC_DM_INIT); | |
802 | } | |
1da177e4 | 803 | |
e05d723f TG |
804 | /* |
805 | * An initial setup of the virtual wire mode. | |
806 | */ | |
807 | void __init init_bsp_APIC(void) | |
808 | { | |
809 | unsigned long value; | |
f990fff4 | 810 | |
e05d723f TG |
811 | /* |
812 | * Don't do the setup now if we have a SMP BIOS as the | |
813 | * through-I/O-APIC virtual wire mode might be active. | |
814 | */ | |
815 | if (smp_found_config || !cpu_has_apic) | |
816 | return; | |
1da177e4 LT |
817 | |
818 | /* | |
e05d723f | 819 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 820 | */ |
e05d723f | 821 | clear_local_APIC(); |
1da177e4 | 822 | |
e05d723f TG |
823 | /* |
824 | * Enable APIC. | |
825 | */ | |
826 | value = apic_read(APIC_SPIV); | |
827 | value &= ~APIC_VECTOR_MASK; | |
828 | value |= APIC_SPIV_APIC_ENABLED; | |
829 | ||
830 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
831 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
832 | (boot_cpu_data.x86 == 15)) | |
833 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
834 | else | |
835 | value |= APIC_SPIV_FOCUS_DISABLED; | |
836 | value |= SPURIOUS_APIC_VECTOR; | |
837 | apic_write_around(APIC_SPIV, value); | |
838 | ||
839 | /* | |
840 | * Set up the virtual wire mode. | |
841 | */ | |
842 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
843 | value = APIC_DM_NMI; | |
844 | if (!lapic_is_integrated()) /* 82489DX */ | |
845 | value |= APIC_LVT_LEVEL_TRIGGER; | |
846 | apic_write_around(APIC_LVT1, value); | |
1da177e4 LT |
847 | } |
848 | ||
e05d723f TG |
849 | /** |
850 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 851 | */ |
e05d723f TG |
852 | void __devinit setup_local_APIC(void) |
853 | { | |
854 | unsigned long oldvalue, value, maxlvt, integrated; | |
855 | int i, j; | |
1da177e4 | 856 | |
e05d723f TG |
857 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
858 | if (esr_disable) { | |
859 | apic_write(APIC_ESR, 0); | |
860 | apic_write(APIC_ESR, 0); | |
861 | apic_write(APIC_ESR, 0); | |
862 | apic_write(APIC_ESR, 0); | |
863 | } | |
1da177e4 | 864 | |
e05d723f | 865 | integrated = lapic_is_integrated(); |
1da177e4 | 866 | |
e05d723f TG |
867 | /* |
868 | * Double-check whether this APIC is really registered. | |
869 | */ | |
870 | if (!apic_id_registered()) | |
871 | BUG(); | |
1da177e4 | 872 | |
e05d723f TG |
873 | /* |
874 | * Intel recommends to set DFR, LDR and TPR before enabling | |
875 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
876 | * document number 292116). So here it goes... | |
877 | */ | |
878 | init_apic_ldr(); | |
1da177e4 | 879 | |
e05d723f TG |
880 | /* |
881 | * Set Task Priority to 'accept all'. We never change this | |
882 | * later on. | |
883 | */ | |
884 | value = apic_read(APIC_TASKPRI); | |
885 | value &= ~APIC_TPRI_MASK; | |
886 | apic_write_around(APIC_TASKPRI, value); | |
1da177e4 | 887 | |
e05d723f TG |
888 | /* |
889 | * After a crash, we no longer service the interrupts and a pending | |
890 | * interrupt from previous kernel might still have ISR bit set. | |
891 | * | |
892 | * Most probably by now CPU has serviced that pending interrupt and | |
893 | * it might not have done the ack_APIC_irq() because it thought, | |
894 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
895 | * does not clear the ISR bit and cpu thinks it has already serivced | |
896 | * the interrupt. Hence a vector might get locked. It was noticed | |
897 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
898 | */ | |
899 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
900 | value = apic_read(APIC_ISR + i*0x10); | |
901 | for (j = 31; j >= 0; j--) { | |
902 | if (value & (1<<j)) | |
903 | ack_APIC_irq(); | |
904 | } | |
905 | } | |
1da177e4 | 906 | |
e05d723f TG |
907 | /* |
908 | * Now that we are all set up, enable the APIC | |
909 | */ | |
910 | value = apic_read(APIC_SPIV); | |
911 | value &= ~APIC_VECTOR_MASK; | |
912 | /* | |
913 | * Enable APIC | |
914 | */ | |
915 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 916 | |
e05d723f TG |
917 | /* |
918 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
919 | * certain networking cards. If high frequency interrupts are | |
920 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
921 | * entry is masked/unmasked at a high rate as well then sooner or | |
922 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
923 | * from the device. If focus CPU is disabled then the hang goes | |
924 | * away, oh well :-( | |
925 | * | |
926 | * [ This bug can be reproduced easily with a level-triggered | |
927 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
928 | * BX chipset. ] | |
929 | */ | |
930 | /* | |
931 | * Actually disabling the focus CPU check just makes the hang less | |
932 | * frequent as it makes the interrupt distributon model be more | |
933 | * like LRU than MRU (the short-term load is more even across CPUs). | |
934 | * See also the comment in end_level_ioapic_irq(). --macro | |
935 | */ | |
1da177e4 | 936 | |
e05d723f TG |
937 | /* Enable focus processor (bit==0) */ |
938 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 939 | |
e05d723f TG |
940 | /* |
941 | * Set spurious IRQ vector | |
942 | */ | |
943 | value |= SPURIOUS_APIC_VECTOR; | |
944 | apic_write_around(APIC_SPIV, value); | |
945 | ||
946 | /* | |
947 | * Set up LVT0, LVT1: | |
948 | * | |
949 | * set up through-local-APIC on the BP's LINT0. This is not | |
950 | * strictly necessery in pure symmetric-IO mode, but sometimes | |
951 | * we delegate interrupts to the 8259A. | |
952 | */ | |
953 | /* | |
954 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
955 | */ | |
956 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
957 | if (!smp_processor_id() && (pic_mode || !value)) { | |
958 | value = APIC_DM_EXTINT; | |
959 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
960 | smp_processor_id()); | |
961 | } else { | |
962 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
963 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
964 | smp_processor_id()); | |
965 | } | |
966 | apic_write_around(APIC_LVT0, value); | |
967 | ||
968 | /* | |
969 | * only the BP should see the LINT1 NMI signal, obviously. | |
970 | */ | |
971 | if (!smp_processor_id()) | |
972 | value = APIC_DM_NMI; | |
973 | else | |
974 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
975 | if (!integrated) /* 82489DX */ | |
976 | value |= APIC_LVT_LEVEL_TRIGGER; | |
977 | apic_write_around(APIC_LVT1, value); | |
978 | ||
979 | if (integrated && !esr_disable) { /* !82489DX */ | |
980 | maxlvt = lapic_get_maxlvt(); | |
981 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
982 | apic_write(APIC_ESR, 0); | |
983 | oldvalue = apic_read(APIC_ESR); | |
984 | ||
985 | /* enables sending errors */ | |
986 | value = ERROR_APIC_VECTOR; | |
987 | apic_write_around(APIC_LVTERR, value); | |
988 | /* | |
989 | * spec says clear errors after enabling vector. | |
990 | */ | |
991 | if (maxlvt > 3) | |
992 | apic_write(APIC_ESR, 0); | |
993 | value = apic_read(APIC_ESR); | |
994 | if (value != oldvalue) | |
995 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
996 | "vector: 0x%08lx after: 0x%08lx\n", | |
997 | oldvalue, value); | |
998 | } else { | |
999 | if (esr_disable) | |
1000 | /* | |
1001 | * Something untraceble is creating bad interrupts on | |
1002 | * secondary quads ... for the moment, just leave the | |
1003 | * ESR disabled - we can't do anything useful with the | |
1004 | * errors anyway - mbligh | |
1005 | */ | |
1006 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
1007 | else | |
1008 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
1009 | } | |
1da177e4 | 1010 | |
e9e2cdb4 TG |
1011 | /* Disable the local apic timer */ |
1012 | value = apic_read(APIC_LVTT); | |
1013 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1014 | apic_write_around(APIC_LVTT, value); | |
1015 | ||
e05d723f TG |
1016 | setup_apic_nmi_watchdog(NULL); |
1017 | apic_pm_activate(); | |
1da177e4 LT |
1018 | } |
1019 | ||
e05d723f TG |
1020 | /* |
1021 | * Detect and initialize APIC | |
1022 | */ | |
1da177e4 LT |
1023 | static int __init detect_init_APIC (void) |
1024 | { | |
1025 | u32 h, l, features; | |
1da177e4 LT |
1026 | |
1027 | /* Disabled by kernel option? */ | |
1028 | if (enable_local_apic < 0) | |
1029 | return -1; | |
1030 | ||
1da177e4 LT |
1031 | switch (boot_cpu_data.x86_vendor) { |
1032 | case X86_VENDOR_AMD: | |
1033 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1034 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1035 | break; |
1036 | goto no_apic; | |
1037 | case X86_VENDOR_INTEL: | |
1038 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1039 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1040 | break; | |
1041 | goto no_apic; | |
1042 | default: | |
1043 | goto no_apic; | |
1044 | } | |
1045 | ||
1046 | if (!cpu_has_apic) { | |
1047 | /* | |
e05d723f TG |
1048 | * Over-ride BIOS and try to enable the local APIC only if |
1049 | * "lapic" specified. | |
1da177e4 LT |
1050 | */ |
1051 | if (enable_local_apic <= 0) { | |
e05d723f | 1052 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1053 | "you can enable it with \"lapic\"\n"); |
1054 | return -1; | |
1055 | } | |
1056 | /* | |
e05d723f TG |
1057 | * Some BIOSes disable the local APIC in the APIC_BASE |
1058 | * MSR. This can only be done in software for Intel P6 or later | |
1059 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1060 | */ |
1061 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1062 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1063 | printk(KERN_INFO |
1064 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1065 | l &= ~MSR_IA32_APICBASE_BASE; |
1066 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1067 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1068 | enabled_via_apicbase = 1; | |
1069 | } | |
1070 | } | |
1071 | /* | |
1072 | * The APIC feature bit should now be enabled | |
1073 | * in `cpuid' | |
1074 | */ | |
1075 | features = cpuid_edx(1); | |
1076 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1077 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1078 | return -1; |
1079 | } | |
1080 | set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1081 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1082 | ||
1083 | /* The BIOS may have set up the APIC at some other address */ | |
1084 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1085 | if (l & MSR_IA32_APICBASE_ENABLE) |
1086 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1087 | |
e05d723f TG |
1088 | if (nmi_watchdog != NMI_NONE) |
1089 | nmi_watchdog = NMI_LOCAL_APIC; | |
1da177e4 | 1090 | |
e05d723f | 1091 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1092 | |
e05d723f | 1093 | apic_pm_activate(); |
1da177e4 | 1094 | |
e05d723f | 1095 | return 0; |
1da177e4 | 1096 | |
e05d723f TG |
1097 | no_apic: |
1098 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1099 | return -1; | |
1100 | } | |
1da177e4 | 1101 | |
e05d723f TG |
1102 | /** |
1103 | * init_apic_mappings - initialize APIC mappings | |
1104 | */ | |
1105 | void __init init_apic_mappings(void) | |
1da177e4 | 1106 | { |
e05d723f | 1107 | unsigned long apic_phys; |
1da177e4 | 1108 | |
1da177e4 | 1109 | /* |
e05d723f TG |
1110 | * If no local APIC can be found then set up a fake all |
1111 | * zeroes page to simulate the local APIC and another | |
1112 | * one for the IO-APIC. | |
1da177e4 | 1113 | */ |
e05d723f TG |
1114 | if (!smp_found_config && detect_init_APIC()) { |
1115 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1116 | apic_phys = __pa(apic_phys); | |
1117 | } else | |
1118 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1119 | |
e05d723f TG |
1120 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1121 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1122 | apic_phys); | |
1da177e4 | 1123 | |
e05d723f TG |
1124 | /* |
1125 | * Fetch the APIC ID of the BSP in case we have a | |
1126 | * default configuration (or the MP table is broken). | |
1127 | */ | |
1128 | if (boot_cpu_physical_apicid == -1U) | |
1129 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 | 1130 | |
e05d723f TG |
1131 | #ifdef CONFIG_X86_IO_APIC |
1132 | { | |
1133 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
1134 | int i; | |
1da177e4 | 1135 | |
e05d723f TG |
1136 | for (i = 0; i < nr_ioapics; i++) { |
1137 | if (smp_found_config) { | |
1138 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
1139 | if (!ioapic_phys) { | |
1140 | printk(KERN_ERR | |
1141 | "WARNING: bogus zero IO-APIC " | |
1142 | "address found in MPTABLE, " | |
1143 | "disabling IO/APIC support!\n"); | |
1144 | smp_found_config = 0; | |
1145 | skip_ioapic_setup = 1; | |
1146 | goto fake_ioapic_page; | |
1147 | } | |
1148 | } else { | |
1149 | fake_ioapic_page: | |
1150 | ioapic_phys = (unsigned long) | |
1151 | alloc_bootmem_pages(PAGE_SIZE); | |
1152 | ioapic_phys = __pa(ioapic_phys); | |
1153 | } | |
1154 | set_fixmap_nocache(idx, ioapic_phys); | |
1155 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
1156 | __fix_to_virt(idx), ioapic_phys); | |
1157 | idx++; | |
1158 | } | |
1da177e4 | 1159 | } |
e05d723f | 1160 | #endif |
1da177e4 LT |
1161 | } |
1162 | ||
e05d723f TG |
1163 | /* |
1164 | * This initializes the IO-APIC and APIC hardware if this is | |
1165 | * a UP kernel. | |
1166 | */ | |
1167 | int __init APIC_init_uniprocessor (void) | |
1da177e4 | 1168 | { |
e05d723f TG |
1169 | if (enable_local_apic < 0) |
1170 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1da177e4 | 1171 | |
e05d723f TG |
1172 | if (!smp_found_config && !cpu_has_apic) |
1173 | return -1; | |
6eb0a0fd | 1174 | |
e05d723f TG |
1175 | /* |
1176 | * Complain if the BIOS pretends there is one. | |
1177 | */ | |
1178 | if (!cpu_has_apic && | |
1179 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1180 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1181 | boot_cpu_physical_apicid); | |
1182 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1183 | return -1; | |
6eb0a0fd | 1184 | } |
6eb0a0fd | 1185 | |
e05d723f | 1186 | verify_local_APIC(); |
6eb0a0fd | 1187 | |
e05d723f | 1188 | connect_bsp_APIC(); |
6eb0a0fd | 1189 | |
e05d723f TG |
1190 | /* |
1191 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1192 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1193 | * might be zero if read from MP tables. Get it from LAPIC. | |
1194 | */ | |
1195 | #ifdef CONFIG_CRASH_DUMP | |
1196 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1197 | #endif | |
1198 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
1da177e4 | 1199 | |
e05d723f | 1200 | setup_local_APIC(); |
1da177e4 | 1201 | |
e05d723f TG |
1202 | #ifdef CONFIG_X86_IO_APIC |
1203 | if (smp_found_config) | |
1204 | if (!skip_ioapic_setup && nr_ioapics) | |
1205 | setup_IO_APIC(); | |
1da177e4 | 1206 | #endif |
e05d723f | 1207 | setup_boot_clock(); |
1da177e4 | 1208 | |
e05d723f | 1209 | return 0; |
1da177e4 LT |
1210 | } |
1211 | ||
1212 | /* | |
e05d723f | 1213 | * APIC command line parameters |
1da177e4 | 1214 | */ |
e05d723f | 1215 | static int __init parse_lapic(char *arg) |
6eb0a0fd | 1216 | { |
e05d723f TG |
1217 | enable_local_apic = 1; |
1218 | return 0; | |
6eb0a0fd | 1219 | } |
e05d723f | 1220 | early_param("lapic", parse_lapic); |
6eb0a0fd | 1221 | |
e05d723f | 1222 | static int __init parse_nolapic(char *arg) |
6eb0a0fd | 1223 | { |
e05d723f TG |
1224 | enable_local_apic = -1; |
1225 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1226 | return 0; | |
6eb0a0fd | 1227 | } |
e05d723f | 1228 | early_param("nolapic", parse_nolapic); |
6eb0a0fd | 1229 | |
ad62ca2b TG |
1230 | static int __init parse_disable_lapic_timer(char *arg) |
1231 | { | |
1232 | local_apic_timer_disabled = 1; | |
1233 | return 0; | |
1234 | } | |
1235 | early_param("nolapic_timer", parse_disable_lapic_timer); | |
1236 | ||
e585bef8 TG |
1237 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1238 | { | |
1239 | local_apic_timer_c2_ok = 1; | |
1240 | return 0; | |
1241 | } | |
1242 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1243 | ||
e05d723f | 1244 | static int __init apic_set_verbosity(char *str) |
5a07a30c | 1245 | { |
e05d723f TG |
1246 | if (strcmp("debug", str) == 0) |
1247 | apic_verbosity = APIC_DEBUG; | |
1248 | else if (strcmp("verbose", str) == 0) | |
1249 | apic_verbosity = APIC_VERBOSE; | |
1250 | return 1; | |
5a07a30c VP |
1251 | } |
1252 | ||
e05d723f TG |
1253 | __setup("apic=", apic_set_verbosity); |
1254 | ||
1255 | ||
1256 | /* | |
1257 | * Local APIC interrupts | |
1258 | */ | |
1259 | ||
1da177e4 LT |
1260 | /* |
1261 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1262 | */ | |
e9e2cdb4 | 1263 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1264 | { |
1265 | unsigned long v; | |
1266 | ||
1267 | irq_enter(); | |
1268 | /* | |
1269 | * Check if this really is a spurious interrupt and ACK it | |
1270 | * if it is a vectored one. Just in case... | |
1271 | * Spurious interrupts should not be ACKed. | |
1272 | */ | |
1273 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1274 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1275 | ack_APIC_irq(); | |
1276 | ||
1277 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1278 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1279 | "should never happen.\n", smp_processor_id()); | |
1da177e4 LT |
1280 | irq_exit(); |
1281 | } | |
1282 | ||
1283 | /* | |
1284 | * This interrupt should never happen with our APIC/SMP architecture | |
1285 | */ | |
e9e2cdb4 | 1286 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1287 | { |
1288 | unsigned long v, v1; | |
1289 | ||
1290 | irq_enter(); | |
1291 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1292 | v = apic_read(APIC_ESR); | |
1293 | apic_write(APIC_ESR, 0); | |
1294 | v1 = apic_read(APIC_ESR); | |
1295 | ack_APIC_irq(); | |
1296 | atomic_inc(&irq_err_count); | |
1297 | ||
1298 | /* Here is what the APIC error bits mean: | |
1299 | 0: Send CS error | |
1300 | 1: Receive CS error | |
1301 | 2: Send accept error | |
1302 | 3: Receive accept error | |
1303 | 4: Reserved | |
1304 | 5: Send illegal vector | |
1305 | 6: Received illegal vector | |
1306 | 7: Illegal register address | |
1307 | */ | |
1308 | printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", | |
e05d723f | 1309 | smp_processor_id(), v , v1); |
1da177e4 LT |
1310 | irq_exit(); |
1311 | } | |
1312 | ||
1313 | /* | |
e05d723f | 1314 | * Initialize APIC interrupts |
1da177e4 | 1315 | */ |
e05d723f | 1316 | void __init apic_intr_init(void) |
1da177e4 | 1317 | { |
e05d723f TG |
1318 | #ifdef CONFIG_SMP |
1319 | smp_intr_init(); | |
1320 | #endif | |
1321 | /* self generated IPI for local APIC timer */ | |
1322 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
1da177e4 | 1323 | |
e05d723f TG |
1324 | /* IPI vectors for APIC spurious and error interrupts */ |
1325 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
1326 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
1da177e4 | 1327 | |
e05d723f TG |
1328 | /* thermal monitor LVT interrupt */ |
1329 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1330 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
1331 | #endif | |
1332 | } | |
1333 | ||
1334 | /** | |
1335 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1336 | */ | |
1337 | void __init connect_bsp_APIC(void) | |
1338 | { | |
1339 | if (pic_mode) { | |
1340 | /* | |
1341 | * Do not trust the local APIC being empty at bootup. | |
1342 | */ | |
1343 | clear_local_APIC(); | |
1344 | /* | |
1345 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1346 | * local APIC to INT and NMI lines. | |
1347 | */ | |
1348 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1349 | "enabling APIC mode.\n"); | |
1350 | outb(0x70, 0x22); | |
1351 | outb(0x01, 0x23); | |
1da177e4 | 1352 | } |
e05d723f TG |
1353 | enable_apic_mode(); |
1354 | } | |
1da177e4 | 1355 | |
e05d723f TG |
1356 | /** |
1357 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1358 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1359 | * | |
1360 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1361 | * APIC is disabled. | |
1362 | */ | |
1363 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1364 | { | |
1365 | if (pic_mode) { | |
1366 | /* | |
1367 | * Put the board back into PIC mode (has an effect only on | |
1368 | * certain older boards). Note that APIC interrupts, including | |
1369 | * IPIs, won't work beyond this point! The only exception are | |
1370 | * INIT IPIs. | |
1371 | */ | |
1372 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1373 | "entering PIC mode.\n"); | |
1374 | outb(0x70, 0x22); | |
1375 | outb(0x00, 0x23); | |
1376 | } else { | |
1377 | /* Go back to Virtual Wire compatibility mode */ | |
1378 | unsigned long value; | |
1da177e4 | 1379 | |
e05d723f TG |
1380 | /* For the spurious interrupt use vector F, and enable it */ |
1381 | value = apic_read(APIC_SPIV); | |
1382 | value &= ~APIC_VECTOR_MASK; | |
1383 | value |= APIC_SPIV_APIC_ENABLED; | |
1384 | value |= 0xf; | |
1385 | apic_write_around(APIC_SPIV, value); | |
1da177e4 | 1386 | |
e05d723f TG |
1387 | if (!virt_wire_setup) { |
1388 | /* | |
1389 | * For LVT0 make it edge triggered, active high, | |
1390 | * external and enabled | |
1391 | */ | |
1392 | value = apic_read(APIC_LVT0); | |
1393 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1394 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1395 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
1396 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1397 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1398 | apic_write_around(APIC_LVT0, value); | |
1399 | } else { | |
1400 | /* Disable LVT0 */ | |
1401 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
1402 | } | |
1da177e4 | 1403 | |
e05d723f TG |
1404 | /* |
1405 | * For LVT1 make it edge triggered, active high, nmi and | |
1406 | * enabled | |
1407 | */ | |
1408 | value = apic_read(APIC_LVT1); | |
1409 | value &= ~( | |
1410 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
1411 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1412 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1413 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1414 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1415 | apic_write_around(APIC_LVT1, value); | |
1416 | } | |
1417 | } | |
1da177e4 | 1418 | |
e05d723f TG |
1419 | /* |
1420 | * Power management | |
1421 | */ | |
1422 | #ifdef CONFIG_PM | |
1423 | ||
1424 | static struct { | |
1425 | int active; | |
1426 | /* r/w apic fields */ | |
1427 | unsigned int apic_id; | |
1428 | unsigned int apic_taskpri; | |
1429 | unsigned int apic_ldr; | |
1430 | unsigned int apic_dfr; | |
1431 | unsigned int apic_spiv; | |
1432 | unsigned int apic_lvtt; | |
1433 | unsigned int apic_lvtpc; | |
1434 | unsigned int apic_lvt0; | |
1435 | unsigned int apic_lvt1; | |
1436 | unsigned int apic_lvterr; | |
1437 | unsigned int apic_tmict; | |
1438 | unsigned int apic_tdcr; | |
1439 | unsigned int apic_thmr; | |
1440 | } apic_pm_state; | |
1441 | ||
1442 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1443 | { | |
1444 | unsigned long flags; | |
1445 | int maxlvt; | |
1446 | ||
1447 | if (!apic_pm_state.active) | |
1448 | return 0; | |
1449 | ||
1450 | maxlvt = lapic_get_maxlvt(); | |
1451 | ||
1452 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1453 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1454 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1455 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1456 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1457 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1458 | if (maxlvt >= 4) | |
1459 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1460 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1461 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1462 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1463 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1464 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1465 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1466 | if (maxlvt >= 5) | |
1467 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1468 | #endif |
1e4c85f9 | 1469 | |
e05d723f TG |
1470 | local_irq_save(flags); |
1471 | disable_local_APIC(); | |
1472 | local_irq_restore(flags); | |
1e4c85f9 | 1473 | return 0; |
1da177e4 | 1474 | } |
1a3f239d | 1475 | |
e05d723f | 1476 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1477 | { |
e05d723f TG |
1478 | unsigned int l, h; |
1479 | unsigned long flags; | |
1480 | int maxlvt; | |
1481 | ||
1482 | if (!apic_pm_state.active) | |
1483 | return 0; | |
1484 | ||
1485 | maxlvt = lapic_get_maxlvt(); | |
1486 | ||
1487 | local_irq_save(flags); | |
1488 | ||
1489 | /* | |
1490 | * Make sure the APICBASE points to the right address | |
1491 | * | |
1492 | * FIXME! This will be wrong if we ever support suspend on | |
1493 | * SMP! We'll need to do this as part of the CPU restore! | |
1494 | */ | |
1495 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1496 | l &= ~MSR_IA32_APICBASE_BASE; | |
1497 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1498 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1499 | ||
1500 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1501 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1502 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1503 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1504 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1505 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1506 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1507 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1508 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1509 | if (maxlvt >= 5) | |
1510 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1511 | #endif | |
1512 | if (maxlvt >= 4) | |
1513 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1514 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1515 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1516 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1517 | apic_write(APIC_ESR, 0); | |
1518 | apic_read(APIC_ESR); | |
1519 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1520 | apic_write(APIC_ESR, 0); | |
1521 | apic_read(APIC_ESR); | |
1522 | local_irq_restore(flags); | |
1a3f239d RR |
1523 | return 0; |
1524 | } | |
1a3f239d | 1525 | |
e05d723f TG |
1526 | /* |
1527 | * This device has no shutdown method - fully functioning local APICs | |
1528 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1529 | */ | |
1530 | ||
1531 | static struct sysdev_class lapic_sysclass = { | |
1532 | set_kset_name("lapic"), | |
1533 | .resume = lapic_resume, | |
1534 | .suspend = lapic_suspend, | |
1535 | }; | |
1536 | ||
1537 | static struct sys_device device_lapic = { | |
1538 | .id = 0, | |
1539 | .cls = &lapic_sysclass, | |
1540 | }; | |
1541 | ||
1542 | static void __devinit apic_pm_activate(void) | |
1a3f239d | 1543 | { |
e05d723f | 1544 | apic_pm_state.active = 1; |
1a3f239d | 1545 | } |
1a3f239d | 1546 | |
e05d723f TG |
1547 | static int __init init_lapic_sysfs(void) |
1548 | { | |
1549 | int error; | |
1550 | ||
1551 | if (!cpu_has_apic) | |
1552 | return 0; | |
1553 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1554 | ||
1555 | error = sysdev_class_register(&lapic_sysclass); | |
1556 | if (!error) | |
1557 | error = sysdev_register(&device_lapic); | |
1558 | return error; | |
1559 | } | |
1560 | device_initcall(init_lapic_sysfs); | |
1561 | ||
1562 | #else /* CONFIG_PM */ | |
1563 | ||
1564 | static void apic_pm_activate(void) { } | |
1565 | ||
1566 | #endif /* CONFIG_PM */ |