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1da177e4 LT |
1 | /* pci-frv.c: low-level PCI access routines |
2 | * | |
3 | * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * - Derived from the i386 equivalent stuff | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/types.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/errno.h> | |
19 | ||
20 | #include "pci-frv.h" | |
21 | ||
22 | #if 0 | |
23 | void | |
24 | pcibios_update_resource(struct pci_dev *dev, struct resource *root, | |
25 | struct resource *res, int resource) | |
26 | { | |
27 | u32 new, check; | |
28 | int reg; | |
29 | ||
30 | new = res->start | (res->flags & PCI_REGION_FLAG_MASK); | |
31 | if (resource < 6) { | |
32 | reg = PCI_BASE_ADDRESS_0 + 4*resource; | |
33 | } else if (resource == PCI_ROM_RESOURCE) { | |
34 | res->flags |= IORESOURCE_ROM_ENABLE; | |
35 | new |= PCI_ROM_ADDRESS_ENABLE; | |
36 | reg = dev->rom_base_reg; | |
37 | } else { | |
38 | /* Somebody might have asked allocation of a non-standard resource */ | |
39 | return; | |
40 | } | |
41 | ||
42 | pci_write_config_dword(dev, reg, new); | |
43 | pci_read_config_dword(dev, reg, &check); | |
44 | if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) { | |
45 | printk(KERN_ERR "PCI: Error while updating region " | |
46 | "%s/%d (%08x != %08x)\n", pci_name(dev), resource, | |
47 | new, check); | |
48 | } | |
49 | } | |
50 | #endif | |
51 | ||
52 | /* | |
53 | * We need to avoid collisions with `mirrored' VGA ports | |
54 | * and other strange ISA hardware, so we always want the | |
55 | * addresses to be allocated in the 0x000-0x0ff region | |
56 | * modulo 0x400. | |
57 | * | |
58 | * Why? Because some silly external IO cards only decode | |
59 | * the low 10 bits of the IO address. The 0x00-0xff region | |
60 | * is reserved for motherboard devices that decode all 16 | |
61 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
62 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
63 | * which might have be mirrored at 0x0100-0x03ff.. | |
64 | */ | |
65 | void | |
66 | pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 67 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
68 | { |
69 | if (res->flags & IORESOURCE_IO) { | |
e31dd6e4 | 70 | resource_size_t start = res->start; |
1da177e4 LT |
71 | |
72 | if (start & 0x300) { | |
73 | start = (start + 0x3ff) & ~0x3ff; | |
74 | res->start = start; | |
75 | } | |
76 | } | |
77 | } | |
78 | ||
79 | ||
80 | /* | |
81 | * Handle resources of PCI devices. If the world were perfect, we could | |
82 | * just allocate all the resource regions and do nothing more. It isn't. | |
83 | * On the other hand, we cannot just re-allocate all devices, as it would | |
84 | * require us to know lots of host bridge internals. So we attempt to | |
85 | * keep as much of the original configuration as possible, but tweak it | |
86 | * when it's found to be wrong. | |
87 | * | |
88 | * Known BIOS problems we have to work around: | |
89 | * - I/O or memory regions not configured | |
90 | * - regions configured, but not enabled in the command register | |
91 | * - bogus I/O addresses above 64K used | |
92 | * - expansion ROMs left enabled (this may sound harmless, but given | |
93 | * the fact the PCI specs explicitly allow address decoders to be | |
94 | * shared between expansion ROMs and other resource regions, it's | |
95 | * at least dangerous) | |
96 | * | |
97 | * Our solution: | |
98 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
99 | * This gives us fixed barriers on where we can allocate. | |
100 | * (2) Allocate resources for all enabled devices. If there is | |
101 | * a collision, just mark the resource as unallocated. Also | |
102 | * disable expansion ROMs during this step. | |
103 | * (3) Try to allocate resources for disabled devices. If the | |
104 | * resources were assigned correctly, everything goes well, | |
105 | * if they weren't, they won't disturb allocation of other | |
106 | * resources. | |
107 | * (4) Assign new addresses to resources which were either | |
108 | * not configured at all or misconfigured. If explicitly | |
109 | * requested by the user, configure expansion ROM address | |
110 | * as well. | |
111 | */ | |
112 | ||
113 | static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) | |
114 | { | |
115 | struct list_head *ln; | |
116 | struct pci_bus *bus; | |
117 | struct pci_dev *dev; | |
118 | int idx; | |
119 | struct resource *r, *pr; | |
120 | ||
121 | /* Depth-First Search on bus tree */ | |
122 | for (ln=bus_list->next; ln != bus_list; ln=ln->next) { | |
123 | bus = pci_bus_b(ln); | |
124 | if ((dev = bus->self)) { | |
125 | for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) { | |
126 | r = &dev->resource[idx]; | |
127 | if (!r->start) | |
128 | continue; | |
129 | pr = pci_find_parent_resource(dev, r); | |
130 | if (!pr || request_resource(pr, r) < 0) | |
131 | printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, pci_name(dev)); | |
132 | } | |
133 | } | |
134 | pcibios_allocate_bus_resources(&bus->children); | |
135 | } | |
136 | } | |
137 | ||
138 | static void __init pcibios_allocate_resources(int pass) | |
139 | { | |
140 | struct pci_dev *dev = NULL; | |
141 | int idx, disabled; | |
142 | u16 command; | |
143 | struct resource *r, *pr; | |
144 | ||
619daa2e | 145 | for_each_pci_dev(dev) { |
1da177e4 LT |
146 | pci_read_config_word(dev, PCI_COMMAND, &command); |
147 | for(idx = 0; idx < 6; idx++) { | |
148 | r = &dev->resource[idx]; | |
149 | if (r->parent) /* Already allocated */ | |
150 | continue; | |
151 | if (!r->start) /* Address not assigned at all */ | |
152 | continue; | |
153 | if (r->flags & IORESOURCE_IO) | |
154 | disabled = !(command & PCI_COMMAND_IO); | |
155 | else | |
156 | disabled = !(command & PCI_COMMAND_MEMORY); | |
157 | if (pass == disabled) { | |
158 | DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n", | |
159 | r->start, r->end, r->flags, disabled, pass); | |
160 | pr = pci_find_parent_resource(dev, r); | |
161 | if (!pr || request_resource(pr, r) < 0) { | |
162 | printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, pci_name(dev)); | |
163 | /* We'll assign a new address later */ | |
164 | r->end -= r->start; | |
165 | r->start = 0; | |
166 | } | |
167 | } | |
168 | } | |
169 | if (!pass) { | |
170 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
171 | if (r->flags & IORESOURCE_ROM_ENABLE) { | |
172 | /* Turn the ROM off, leave the resource region, but keep it unregistered. */ | |
173 | u32 reg; | |
174 | DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); | |
175 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
176 | pci_read_config_dword(dev, dev->rom_base_reg, ®); | |
177 | pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE); | |
178 | } | |
179 | } | |
180 | } | |
181 | } | |
182 | ||
183 | static void __init pcibios_assign_resources(void) | |
184 | { | |
185 | struct pci_dev *dev = NULL; | |
186 | int idx; | |
187 | struct resource *r; | |
188 | ||
619daa2e | 189 | for_each_pci_dev(dev) { |
1da177e4 LT |
190 | int class = dev->class >> 8; |
191 | ||
192 | /* Don't touch classless devices and host bridges */ | |
193 | if (!class || class == PCI_CLASS_BRIDGE_HOST) | |
194 | continue; | |
195 | ||
196 | for(idx=0; idx<6; idx++) { | |
197 | r = &dev->resource[idx]; | |
198 | ||
199 | /* | |
200 | * Don't touch IDE controllers and I/O ports of video cards! | |
201 | */ | |
202 | if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) || | |
203 | (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO))) | |
204 | continue; | |
205 | ||
206 | /* | |
207 | * We shall assign a new address to this resource, either because | |
208 | * the BIOS forgot to do so or because we have decided the old | |
209 | * address was unusable for some reason. | |
210 | */ | |
211 | if (!r->start && r->end) | |
212 | pci_assign_resource(dev, idx); | |
213 | } | |
214 | ||
215 | if (pci_probe & PCI_ASSIGN_ROMS) { | |
216 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
217 | r->end -= r->start; | |
218 | r->start = 0; | |
219 | if (r->end) | |
220 | pci_assign_resource(dev, PCI_ROM_RESOURCE); | |
221 | } | |
222 | } | |
223 | } | |
224 | ||
225 | void __init pcibios_resource_survey(void) | |
226 | { | |
227 | DBG("PCI: Allocating resources\n"); | |
228 | pcibios_allocate_bus_resources(&pci_root_buses); | |
229 | pcibios_allocate_resources(0); | |
230 | pcibios_allocate_resources(1); | |
231 | pcibios_assign_resources(); | |
232 | } | |
233 | ||
234 | int pcibios_enable_resources(struct pci_dev *dev, int mask) | |
235 | { | |
236 | u16 cmd, old_cmd; | |
237 | int idx; | |
238 | struct resource *r; | |
239 | ||
240 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
241 | old_cmd = cmd; | |
242 | for(idx=0; idx<6; idx++) { | |
243 | /* Only set up the requested stuff */ | |
244 | if (!(mask & (1<<idx))) | |
245 | continue; | |
246 | ||
247 | r = &dev->resource[idx]; | |
248 | if (!r->start && r->end) { | |
249 | printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); | |
250 | return -EINVAL; | |
251 | } | |
252 | if (r->flags & IORESOURCE_IO) | |
253 | cmd |= PCI_COMMAND_IO; | |
254 | if (r->flags & IORESOURCE_MEM) | |
255 | cmd |= PCI_COMMAND_MEMORY; | |
256 | } | |
257 | if (dev->resource[PCI_ROM_RESOURCE].start) | |
258 | cmd |= PCI_COMMAND_MEMORY; | |
259 | if (cmd != old_cmd) { | |
260 | printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); | |
261 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
262 | } | |
263 | return 0; | |
264 | } | |
265 | ||
266 | /* | |
267 | * If we set up a device for bus mastering, we need to check the latency | |
268 | * timer as certain crappy BIOSes forget to set it properly. | |
269 | */ | |
270 | unsigned int pcibios_max_latency = 255; | |
271 | ||
272 | void pcibios_set_master(struct pci_dev *dev) | |
273 | { | |
274 | u8 lat; | |
275 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); | |
276 | if (lat < 16) | |
277 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
278 | else if (lat > pcibios_max_latency) | |
279 | lat = pcibios_max_latency; | |
280 | else | |
281 | return; | |
282 | printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat); | |
283 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); | |
284 | } |