[linux-2.6-block.git] / arch / csky / Kconfig

config CSKY
	def_bool y
	select ARCH_HAS_SYNC_DMA_FOR_CPU
	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
	select ARCH_USE_BUILTIN_BSWAP
	select ARCH_USE_QUEUED_RWLOCKS if NR_CPUS>2
	select COMMON_CLK
	select CLKSRC_MMIO
	select CLKSRC_OF
	select DMA_DIRECT_OPS
	select DMA_NONCOHERENT_OPS
	select IRQ_DOMAIN
	select HANDLE_DOMAIN_IRQ
	select DW_APB_TIMER_OF
	select GENERIC_LIB_ASHLDI3
	select GENERIC_LIB_ASHRDI3
	select GENERIC_LIB_LSHRDI3
	select GENERIC_LIB_MULDI3
	select GENERIC_LIB_CMPDI2
	select GENERIC_LIB_UCMPDI2
	select GENERIC_ALLOCATOR
	select GENERIC_ATOMIC64
	select GENERIC_CLOCKEVENTS
	select GENERIC_CPU_DEVICES
	select GENERIC_IRQ_CHIP
	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
	select GENERIC_IRQ_MULTI_HANDLER
	select GENERIC_SCHED_CLOCK
	select GENERIC_SMP_IDLE_THREAD
	select HAVE_ARCH_TRACEHOOK
	select HAVE_GENERIC_DMA_COHERENT
	select HAVE_KERNEL_GZIP
	select HAVE_KERNEL_LZO
	select HAVE_KERNEL_LZMA
	select HAVE_C_RECORDMCOUNT
	select HAVE_DMA_API_DEBUG
	select HAVE_DMA_CONTIGUOUS
	select HAVE_MEMBLOCK
	select MAY_HAVE_SPARSE_IRQ
	select MODULES_USE_ELF_RELA if MODULES
	select OF
	select OF_EARLY_FLATTREE
	select OF_RESERVED_MEM
	select PERF_USE_VMALLOC
	select RTC_LIB
	select TIMER_OF
	select USB_ARCH_HAS_EHCI
	select USB_ARCH_HAS_OHCI

config CPU_HAS_CACHEV2
	bool

config CPU_HAS_FPUV2
	bool

config CPU_HAS_HILO
	bool

config CPU_HAS_TLBI
	bool

config CPU_HAS_LDSTEX
	bool
	help
	  For SMP, CPU needs "ldex&stex" instrcutions to atomic operations.

config CPU_NEED_TLBSYNC
	bool

config CPU_NEED_SOFTALIGN
	bool

config CPU_NO_USER_BKPT
	bool
	help
	  For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because
	  abiv2 is 16/32bit instruction set and "trap 1" is 32bit.
	  So we need a 16bit instruction as user space bkpt, and it will cause an illegal
	  instruction exception.
	  In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.

config GENERIC_CALIBRATE_DELAY
	def_bool y

config GENERIC_CSUM
	def_bool y

config GENERIC_HWEIGHT
	def_bool y

config MMU
	def_bool y

config RWSEM_GENERIC_SPINLOCK
	def_bool y

config TIME_LOW_RES
	def_bool y

config TRACE_IRQFLAGS_SUPPORT
	def_bool y

config CPU_TLB_SIZE
	int
	default "128"	if (CPU_CK610 || CPU_CK807 || CPU_CK810)
	default "1024"	if (CPU_CK860)

config CPU_ASID_BITS
	int
	default "8"	if (CPU_CK610 || CPU_CK807 || CPU_CK810)
	default "12"	if (CPU_CK860)

config L1_CACHE_SHIFT
	int
	default "4"	if (CPU_CK610)
	default "5"	if (CPU_CK807 || CPU_CK810)
	default "6"	if (CPU_CK860)

menu "Processor type and features"

choice
	prompt "CPU MODEL"
	default CPU_CK807

config CPU_CK610
	bool "CSKY CPU ck610"
	select CPU_NEED_TLBSYNC
	select CPU_NEED_SOFTALIGN
	select CPU_NO_USER_BKPT

config CPU_CK810
	bool "CSKY CPU ck810"
	select CPU_HAS_HILO
	select CPU_NEED_TLBSYNC

config CPU_CK807
	bool "CSKY CPU ck807"
	select CPU_HAS_HILO

config CPU_CK860
	bool "CSKY CPU ck860"
	select CPU_HAS_TLBI
	select CPU_HAS_CACHEV2
	select CPU_HAS_LDSTEX
	select CPU_HAS_FPUV2
endchoice

choice
	prompt "Power Manager Instruction (wait/doze/stop)"
	default CPU_PM_NONE

config CPU_PM_NONE
	bool "None"

config CPU_PM_WAIT
	bool "wait"

config CPU_PM_DOZE
	bool "doze"

config CPU_PM_STOP
	bool "stop"
endchoice

config CPU_HAS_VDSP
	bool "CPU has VDSP coprocessor"
	depends on CPU_HAS_FPU && CPU_HAS_FPUV2

config CPU_HAS_FPU
	bool "CPU has FPU coprocessor"
	depends on CPU_CK807 || CPU_CK810 || CPU_CK860

config CPU_HAS_TEE
	bool "CPU has Trusted Execution Environment"
	depends on CPU_CK810

config SMP
	bool "Symmetric Multi-Processing (SMP) support for C-SKY"
	depends on CPU_CK860
	default n

config NR_CPUS
	int "Maximum number of CPUs (2-32)"
	range 2 32
	depends on SMP
	default "2"

config HIGHMEM
	bool "High Memory Support"
	depends on !CPU_CK610
	default y

config FORCE_MAX_ZONEORDER
	int "Maximum zone order"
	default "11"

config RAM_BASE
	hex "DRAM start addr (the same with memory-section in dts)"
	default 0x0

endmenu

source "kernel/Kconfig.hz"
Commit	Line	Data
c32e64e8 GR	1	config CSKY
	2	def_bool y
	3	select ARCH_HAS_SYNC_DMA_FOR_CPU
	4	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
	5	select ARCH_USE_BUILTIN_BSWAP
	6	select ARCH_USE_QUEUED_RWLOCKS if NR_CPUS>2
	7	select COMMON_CLK
	8	select CLKSRC_MMIO
	9	select CLKSRC_OF
	10	select DMA_DIRECT_OPS
	11	select DMA_NONCOHERENT_OPS
	12	select IRQ_DOMAIN
	13	select HANDLE_DOMAIN_IRQ
	14	select DW_APB_TIMER_OF
	15	select GENERIC_LIB_ASHLDI3
	16	select GENERIC_LIB_ASHRDI3
	17	select GENERIC_LIB_LSHRDI3
	18	select GENERIC_LIB_MULDI3
	19	select GENERIC_LIB_CMPDI2
	20	select GENERIC_LIB_UCMPDI2
	21	select GENERIC_ALLOCATOR
	22	select GENERIC_ATOMIC64
	23	select GENERIC_CLOCKEVENTS
	24	select GENERIC_CPU_DEVICES
	25	select GENERIC_IRQ_CHIP
	26	select GENERIC_IRQ_PROBE
	27	select GENERIC_IRQ_SHOW
	28	select GENERIC_IRQ_MULTI_HANDLER
	29	select GENERIC_SCHED_CLOCK
	30	select GENERIC_SMP_IDLE_THREAD
	31	select HAVE_ARCH_TRACEHOOK
	32	select HAVE_GENERIC_DMA_COHERENT
	33	select HAVE_KERNEL_GZIP
	34	select HAVE_KERNEL_LZO
	35	select HAVE_KERNEL_LZMA
	36	select HAVE_C_RECORDMCOUNT
	37	select HAVE_DMA_API_DEBUG
	38	select HAVE_DMA_CONTIGUOUS
	39	select HAVE_MEMBLOCK
	40	select MAY_HAVE_SPARSE_IRQ
	41	select MODULES_USE_ELF_RELA if MODULES
c32e64e8 GR	42	select OF
	43	select OF_EARLY_FLATTREE
	44	select OF_RESERVED_MEM
	45	select PERF_USE_VMALLOC
	46	select RTC_LIB
	47	select TIMER_OF
	48	select USB_ARCH_HAS_EHCI
	49	select USB_ARCH_HAS_OHCI
	50
	51	config CPU_HAS_CACHEV2
	52	bool
	53
	54	config CPU_HAS_FPUV2
	55	bool
	56
	57	config CPU_HAS_HILO
	58	bool
	59
	60	config CPU_HAS_TLBI
	61	bool
	62
	63	config CPU_HAS_LDSTEX
	64	bool
	65	help
	66	For SMP, CPU needs "ldex&stex" instrcutions to atomic operations.
	67
	68	config CPU_NEED_TLBSYNC
	69	bool
	70
	71	config CPU_NEED_SOFTALIGN
	72	bool
	73
	74	config CPU_NO_USER_BKPT
	75	bool
	76	help
	77	For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because
	78	abiv2 is 16/32bit instruction set and "trap 1" is 32bit.
	79	So we need a 16bit instruction as user space bkpt, and it will cause an illegal
	80	instruction exception.
	81	In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
	82
	83	config GENERIC_CALIBRATE_DELAY
	84	def_bool y
	85
	86	config GENERIC_CSUM
	87	def_bool y
	88
	89	config GENERIC_HWEIGHT
	90	def_bool y
	91
	92	config MMU
	93	def_bool y
	94
	95	config RWSEM_GENERIC_SPINLOCK
	96	def_bool y
	97
	98	config TIME_LOW_RES
	99	def_bool y
	100
	101	config TRACE_IRQFLAGS_SUPPORT
	102	def_bool y
	103
	104	config CPU_TLB_SIZE
	105	int
106	default "128" if (CPU_CK610 \|\| CPU_CK807 \|\| CPU_CK810)
107	default "1024" if (CPU_CK860)
108
109	config CPU_ASID_BITS
110	int
111	default "8" if (CPU_CK610 \|\| CPU_CK807 \|\| CPU_CK810)
112	default "12" if (CPU_CK860)
113
114	config L1_CACHE_SHIFT
115	int
116	default "4" if (CPU_CK610)
117	default "5" if (CPU_CK807 \|\| CPU_CK810)
118	default "6" if (CPU_CK860)
119
120	menu "Processor type and features"
121
122	choice
123	prompt "CPU MODEL"
124	default CPU_CK807
125
126	config CPU_CK610
127	bool "CSKY CPU ck610"
128	select CPU_NEED_TLBSYNC
129	select CPU_NEED_SOFTALIGN
130	select CPU_NO_USER_BKPT
131
132	config CPU_CK810
133	bool "CSKY CPU ck810"
134	select CPU_HAS_HILO
135	select CPU_NEED_TLBSYNC
136
137	config CPU_CK807
138	bool "CSKY CPU ck807"
139	select CPU_HAS_HILO
140
141	config CPU_CK860
142	bool "CSKY CPU ck860"
143	select CPU_HAS_TLBI
144	select CPU_HAS_CACHEV2
145	select CPU_HAS_LDSTEX
146	select CPU_HAS_FPUV2
147	endchoice
148
149	choice
150	prompt "Power Manager Instruction (wait/doze/stop)"
151	default CPU_PM_NONE
152
153	config CPU_PM_NONE
154	bool "None"
155
156	config CPU_PM_WAIT
157	bool "wait"
158
159	config CPU_PM_DOZE
160	bool "doze"
161
162	config CPU_PM_STOP
163	bool "stop"
164	endchoice
165
166	config CPU_HAS_VDSP
167	bool "CPU has VDSP coprocessor"
168	depends on CPU_HAS_FPU && CPU_HAS_FPUV2
169
170	config CPU_HAS_FPU
171	bool "CPU has FPU coprocessor"
172	depends on CPU_CK807 \|\| CPU_CK810 \|\| CPU_CK860
173
174	config CPU_HAS_TEE
175	bool "CPU has Trusted Execution Environment"
176	depends on CPU_CK810
177
178	config SMP
179	bool "Symmetric Multi-Processing (SMP) support for C-SKY"
180	depends on CPU_CK860
181	default n
182
183	config NR_CPUS
184	int "Maximum number of CPUs (2-32)"
185	range 2 32
186	depends on SMP
187	default "2"
188
189	config HIGHMEM
190	bool "High Memory Support"
191	depends on !CPU_CK610
192	default y
193
194	config FORCE_MAX_ZONEORDER
195	int "Maximum zone order"
196	default "11"
197
198	config RAM_BASE
199	hex "DRAM start addr (the same with memory-section in dts)"
200	default 0x0
201
202	endmenu
203
204	source "kernel/Kconfig.hz"