[linux-block.git] / arch / cris / include / asm / pgtable.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * CRIS pgtable.h - macros and functions to manipulate page tables.
 */

#ifndef _CRIS_PGTABLE_H
#define _CRIS_PGTABLE_H

#include <asm/page.h>
#define __ARCH_USE_5LEVEL_HACK
#include <asm-generic/pgtable-nopmd.h>

#ifndef __ASSEMBLY__
#include <linux/sched/mm.h>
#include <asm/mmu.h>
#endif
#include <arch/pgtable.h>

/*
 * The Linux memory management assumes a three-level page table setup. On
 * CRIS, we use that, but "fold" the mid level into the top-level page
 * table. Since the MMU TLB is software loaded through an interrupt, it
 * supports any page table structure, so we could have used a three-level
 * setup, but for the amounts of memory we normally use, a two-level is
 * probably more efficient.
 *
 * This file contains the functions and defines necessary to modify and use
 * the CRIS page table tree.
 */
#ifndef __ASSEMBLY__
extern void paging_init(void);
#endif

/* Certain architectures need to do special things when pte's
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)

/*
 * (pmds are folded into pgds so this doesn't get actually called,
 * but the define is needed for a generic inline function.)
 */
#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
#define set_pgu(pudptr, pudval) (*(pudptr) = pudval)

/* PGDIR_SHIFT determines the size of the area a second-level page table can
 * map. It is equal to the page size times the number of PTE's that fit in
 * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
 */

#define PGDIR_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT-2))
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * entries per page directory level: we use a two-level, so
 * we don't really have any PMD directory physically.
 * pointers are 4 bytes so we can use the page size and 
 * divide it by 4 (shift by 2).
 */
#define PTRS_PER_PTE	(1UL << (PAGE_SHIFT-2))
#define PTRS_PER_PGD	(1UL << (PAGE_SHIFT-2))

/* calculate how many PGD entries a user-level program can use
 * the first mappable virtual address is 0
 * (TASK_SIZE is the maximum virtual address space)
 */

#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
#define FIRST_USER_ADDRESS      0UL

/* zero page used for uninitialized stuff */
#ifndef __ASSEMBLY__
extern unsigned long empty_zero_page;
#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
#endif

/* number of bits that fit into a memory pointer */
#define BITS_PER_PTR			(8*sizeof(unsigned long))

/* to align the pointer to a pointer address */
#define PTR_MASK			(~(sizeof(void*)-1))

/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
/* 64-bit machines, beware!  SRB. */
#define SIZEOF_PTR_LOG2			2

/* to find an entry in a page-table */
#define PAGE_PTR(address) \
((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)

/* to set the page-dir */
#define SET_PAGE_DIR(tsk,pgdir)

#define pte_none(x)	(!pte_val(x))
#define pte_present(x)	(pte_val(x) & _PAGE_PRESENT)
#define pte_clear(mm,addr,xp)	do { pte_val(*(xp)) = 0; } while (0)

#define pmd_none(x)     (!pmd_val(x))
/* by removing the _PAGE_KERNEL bit from the comparison, the same pmd_bad
 * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
 */
#define	pmd_bad(x)	((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE)
#define pmd_present(x)	(pmd_val(x) & _PAGE_PRESENT)
#define pmd_clear(xp)	do { pmd_val(*(xp)) = 0; } while (0)

#ifndef __ASSEMBLY__

/*
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */

static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_WRITE; }
static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_MODIFIED; }
static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
static inline int pte_special(pte_t pte)	{ return 0; }

static inline pte_t pte_wrprotect(pte_t pte)
{
        pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
        return pte;
}

static inline pte_t pte_mkclean(pte_t pte)
{
	pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); 
	return pte; 
}

static inline pte_t pte_mkold(pte_t pte)
{
	pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
	return pte;
}

static inline pte_t pte_mkwrite(pte_t pte)
{
        pte_val(pte) |= _PAGE_WRITE;
        if (pte_val(pte) & _PAGE_MODIFIED)
                pte_val(pte) |= _PAGE_SILENT_WRITE;
        return pte;
}

static inline pte_t pte_mkdirty(pte_t pte)
{
        pte_val(pte) |= _PAGE_MODIFIED;
        if (pte_val(pte) & _PAGE_WRITE)
                pte_val(pte) |= _PAGE_SILENT_WRITE;
        return pte;
}

static inline pte_t pte_mkyoung(pte_t pte)
{
        pte_val(pte) |= _PAGE_ACCESSED;
        if (pte_val(pte) & _PAGE_READ)
        {
                pte_val(pte) |= _PAGE_SILENT_READ;
                if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) ==
		    (_PAGE_WRITE | _PAGE_MODIFIED))
                        pte_val(pte) |= _PAGE_SILENT_WRITE;
        }
        return pte;
}
static inline pte_t pte_mkspecial(pte_t pte)	{ return pte; }

/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */

/* What actually goes as arguments to the various functions is less than
 * obvious, but a rule of thumb is that struct page's goes as struct page *,
 * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
 * addresses (the 0xc0xxxxxx's) goes as void *'s.
 */

static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
{
	pte_t pte;
	/* the PTE needs a physical address */
	pte_val(pte) = __pa(page) | pgprot_val(pgprot);
	return pte;
}

#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))

#define mk_pte_phys(physpage, pgprot) \
({                                                                      \
        pte_t __pte;                                                    \
                                                                        \
        pte_val(__pte) = (physpage) + pgprot_val(pgprot);               \
        __pte;                                                          \
})

static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }

#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE))


/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
 * __pte_page(pte_val) refers to the "virtual" DRAM interval
 * pte_pagenr refers to the page-number counted starting from the virtual DRAM start
 */

static inline unsigned long __pte_page(pte_t pte)
{
	/* the PTE contains a physical address */
	return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
}

#define pte_pagenr(pte)         ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)

/* permanent address of a page */

#define __page_address(page)    (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
#define pte_page(pte)           (mem_map+pte_pagenr(pte))

/* only the pte's themselves need to point to physical DRAM (see above)
 * the pagetable links are purely handled within the kernel SW and thus
 * don't need the __pa and __va transformations.
 */

static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; }

#define pmd_page(pmd)		(pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
#define pmd_page_vaddr(pmd)	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))

/* to find an entry in a page-table-directory. */
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))

/* to find an entry in a page-table-directory */
static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address)
{
	return mm->pgd + pgd_index(address);
}

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

/* Find an entry in the third-level page table.. */
#define __pte_offset(address) \
	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_kernel(dir, address) \
	((pte_t *) pmd_page_vaddr(*(dir)) +  __pte_offset(address))
#define pte_offset_map(dir, address) \
	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))

#define pte_unmap(pte) do { } while (0)
#define pte_pfn(x)		((unsigned long)(__va((x).pte)) >> PAGE_SHIFT)
#define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))

#define pte_ERROR(e) \
        printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
#define pgd_ERROR(e) \
        printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))


extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */

/*
 * CRIS doesn't have any external MMU info: the kernel page
 * tables contain all the necessary information.
 * 
 * Actually I am not sure on what this could be used for.
 */
static inline void update_mmu_cache(struct vm_area_struct * vma,
	unsigned long address, pte_t *ptep)
{
}

/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */

#define __swp_type(x)			(((x).val >> 5) & 0x7f)
#define __swp_offset(x)			((x).val >> 12)
#define __swp_entry(type, offset)	((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)		((pte_t) { (x).val })

#define kern_addr_valid(addr)   (1)

#include <asm-generic/pgtable.h>

/*
 * No page table caches to initialise
 */
#define pgtable_cache_init()   do { } while (0)

typedef pte_t *pte_addr_t;

#endif /* __ASSEMBLY__ */
#endif /* _CRIS_PGTABLE_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 LT	2	/*
	3	* CRIS pgtable.h - macros and functions to manipulate page tables.
	4	*/
	5
	6	#ifndef _CRIS_PGTABLE_H
	7	#define _CRIS_PGTABLE_H
	8
5d01e6ce	9	#include <asm/page.h>
9849a569	10	#define __ARCH_USE_5LEVEL_HACK
5d01e6ce	11	#include <asm-generic/pgtable-nopmd.h>
1da177e4 LT	12
1da177e4 LT	13	#ifndef __ASSEMBLY__
589ee628	14	#include <linux/sched/mm.h>
1da177e4 LT	15	#include <asm/mmu.h>
1da177e4 LT	16	#endif
556dcee7	17	#include <arch/pgtable.h>
1da177e4 LT	18
	19	/*
	20	* The Linux memory management assumes a three-level page table setup. On
	21	* CRIS, we use that, but "fold" the mid level into the top-level page
	22	* table. Since the MMU TLB is software loaded through an interrupt, it
	23	* supports any page table structure, so we could have used a three-level
	24	* setup, but for the amounts of memory we normally use, a two-level is
	25	* probably more efficient.
	26	*
	27	* This file contains the functions and defines necessary to modify and use
	28	* the CRIS page table tree.
	29	*/
	30	#ifndef __ASSEMBLY__
	31	extern void paging_init(void);
	32	#endif
	33
	34	/* Certain architectures need to do special things when pte's
	35	* within a page table are directly modified. Thus, the following
	36	* hook is made available.
	37	*/
	38	#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
	39	#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
	40
	41	/*
	42	* (pmds are folded into pgds so this doesn't get actually called,
	43	* but the define is needed for a generic inline function.)
	44	*/
	45	#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
5d01e6ce	46	#define set_pgu(pudptr, pudval) (*(pudptr) = pudval)
1da177e4	47
5d01e6ce	48	/* PGDIR_SHIFT determines the size of the area a second-level page table can
1da177e4 LT	49	* map. It is equal to the page size times the number of PTE's that fit in
	50	* a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
	51	*/
	52
5d01e6ce	53	#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2))
1da177e4 LT	54	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	55	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	56
	57	/*
	58	* entries per page directory level: we use a two-level, so
	59	* we don't really have any PMD directory physically.
	60	* pointers are 4 bytes so we can use the page size and
	61	* divide it by 4 (shift by 2).
	62	*/
	63	#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2))
1da177e4 LT	64	#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2))
	65
	66	/* calculate how many PGD entries a user-level program can use
	67	* the first mappable virtual address is 0
	68	* (TASK_SIZE is the maximum virtual address space)
	69	*/
	70
	71	#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
d016bf7e	72	#define FIRST_USER_ADDRESS 0UL
1da177e4 LT	73
	74	/* zero page used for uninitialized stuff */
	75	#ifndef __ASSEMBLY__
	76	extern unsigned long empty_zero_page;
	77	#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
	78	#endif
	79
	80	/* number of bits that fit into a memory pointer */
	81	#define BITS_PER_PTR (8*sizeof(unsigned long))
	82
	83	/* to align the pointer to a pointer address */
	84	#define PTR_MASK (~(sizeof(void*)-1))
	85
	86	/* sizeof(void)==1<<SIZEOF_PTR_LOG2 /
	87	/* 64-bit machines, beware! SRB. */
	88	#define SIZEOF_PTR_LOG2 2
	89
	90	/* to find an entry in a page-table */
	91	#define PAGE_PTR(address) \
	92	((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
	93
	94	/* to set the page-dir */
	95	#define SET_PAGE_DIR(tsk,pgdir)
	96
	97	#define pte_none(x) (!pte_val(x))
	98	#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
	99	#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
	100
5d01e6ce	101	#define pmd_none(x) (!pmd_val(x))
25985edc	102	/* by removing the _PAGE_KERNEL bit from the comparison, the same pmd_bad
1da177e4 LT	103	* works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
	104	*/
	105	#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE)
	106	#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
	107	#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
	108
	109	#ifndef __ASSEMBLY__
	110
1da177e4 LT	111	/*
	112	* The following only work if pte_present() is true.
	113	* Undefined behaviour if not..
	114	*/
	115
d9b5444e	116	static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
d9b5444e AB	117	static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
d9b5444e AB	118	static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
7e675137	119	static inline int pte_special(pte_t pte) { return 0; }
d9b5444e AB	120
d9b5444e AB	121	static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 LT	122	{
	123	pte_val(pte) &= ~(_PAGE_WRITE \| _PAGE_SILENT_WRITE);
	124	return pte;
	125	}
	126
d9b5444e	127	static inline pte_t pte_mkclean(pte_t pte)
1da177e4 LT	128	{
	129	pte_val(pte) &= ~(_PAGE_MODIFIED \| _PAGE_SILENT_WRITE);
	130	return pte;
	131	}
	132
d9b5444e	133	static inline pte_t pte_mkold(pte_t pte)
1da177e4 LT	134	{
	135	pte_val(pte) &= ~(_PAGE_ACCESSED \| _PAGE_SILENT_READ);
	136	return pte;
	137	}
	138
d9b5444e	139	static inline pte_t pte_mkwrite(pte_t pte)
1da177e4 LT	140	{
	141	pte_val(pte) \|= _PAGE_WRITE;
	142	if (pte_val(pte) & _PAGE_MODIFIED)
	143	pte_val(pte) \|= _PAGE_SILENT_WRITE;
	144	return pte;
	145	}
	146
d9b5444e	147	static inline pte_t pte_mkdirty(pte_t pte)
1da177e4 LT	148	{
	149	pte_val(pte) \|= _PAGE_MODIFIED;
	150	if (pte_val(pte) & _PAGE_WRITE)
	151	pte_val(pte) \|= _PAGE_SILENT_WRITE;
	152	return pte;
	153	}
	154
d9b5444e	155	static inline pte_t pte_mkyoung(pte_t pte)
1da177e4 LT	156	{
	157	pte_val(pte) \|= _PAGE_ACCESSED;
	158	if (pte_val(pte) & _PAGE_READ)
	159	{
	160	pte_val(pte) \|= _PAGE_SILENT_READ;
	161	if ((pte_val(pte) & (_PAGE_WRITE \| _PAGE_MODIFIED)) ==
	162	(_PAGE_WRITE \| _PAGE_MODIFIED))
	163	pte_val(pte) \|= _PAGE_SILENT_WRITE;
	164	}
	165	return pte;
	166	}
7e675137	167	static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
1da177e4 LT	168
	169	/*
	170	* Conversion functions: convert a page and protection to a page entry,
	171	* and a page entry and page directory to the page they refer to.
	172	*/
	173
	174	/* What actually goes as arguments to the various functions is less than
	175	* obvious, but a rule of thumb is that struct page's goes as struct page *,
	176	* really physical DRAM addresses are unsigned long's, and DRAM "virtual"
	177	* addresses (the 0xc0xxxxxx's) goes as void *'s.
	178	*/
	179
d9b5444e	180	static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
1da177e4 LT	181	{
	182	pte_t pte;
	183	/* the PTE needs a physical address */
	184	pte_val(pte) = __pa(page) \| pgprot_val(pgprot);
	185	return pte;
	186	}
	187
	188	#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
	189
	190	#define mk_pte_phys(physpage, pgprot) \
	191	({ \
	192	pte_t __pte; \
	193	\
	194	pte_val(__pte) = (physpage) + pgprot_val(pgprot); \
	195	__pte; \
	196	})
	197
d9b5444e	198	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 LT	199	{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) \| pgprot_val(newprot); return pte; }
1da177e4 LT	200
d8fb91e8 AB	201	#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) \| _PAGE_NO_CACHE))
d8fb91e8 AB	202
1da177e4 LT	203
	204	/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
	205	* __pte_page(pte_val) refers to the "virtual" DRAM interval
	206	* pte_pagenr refers to the page-number counted starting from the virtual DRAM start
	207	*/
	208
d9b5444e	209	static inline unsigned long __pte_page(pte_t pte)
1da177e4 LT	210	{
	211	/* the PTE contains a physical address */
	212	return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
	213	}
	214
	215	#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
	216
	217	/* permanent address of a page */
	218
	219	#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
	220	#define pte_page(pte) (mem_map+pte_pagenr(pte))
	221
	222	/* only the pte's themselves need to point to physical DRAM (see above)
	223	* the pagetable links are purely handled within the kernel SW and thus
	224	* don't need the __pa and __va transformations.
	225	*/
	226
d9b5444e	227	static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
1da177e4 LT	228	{ pmd_val(*pmdp) = _PAGE_TABLE \| (unsigned long) ptep; }
	229
	230	#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
46a82b2d	231	#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
1da177e4 LT	232
1da177e4 LT	233	/* to find an entry in a page-table-directory. */
5d01e6ce	234	#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1da177e4 LT	235
1da177e4 LT	236	/* to find an entry in a page-table-directory */
16a26ef5	237	static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address)
1da177e4 LT	238	{
	239	return mm->pgd + pgd_index(address);
	240	}
	241
	242	/* to find an entry in a kernel page-table-directory */
	243	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	244
1da177e4 LT	245	/* Find an entry in the third-level page table.. */
	246	#define __pte_offset(address) \
	247	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	248	#define pte_offset_kernel(dir, address) \
46a82b2d	249	((pte_t ) pmd_page_vaddr((dir)) + __pte_offset(address))
1da177e4 LT	250	#define pte_offset_map(dir, address) \
1da177e4 LT	251	((pte_t )page_address(pmd_page((dir))) + __pte_offset(address))
1da177e4 LT	252
1da177e4 LT	253	#define pte_unmap(pte) do { } while (0)
1da177e4	254	#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT)
620cf2e4	255	#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) \| pgprot_val(prot))
1da177e4 LT	256
	257	#define pte_ERROR(e) \
	258	printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
1da177e4 LT	259	#define pgd_ERROR(e) \
	260	printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
	261
	262
	263	extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
	264
	265	/*
	266	* CRIS doesn't have any external MMU info: the kernel page
	267	* tables contain all the necessary information.
	268	*
	269	* Actually I am not sure on what this could be used for.
	270	*/
d9b5444e	271	static inline void update_mmu_cache(struct vm_area_struct * vma,
4b3073e1	272	unsigned long address, pte_t *ptep)
1da177e4 LT	273	{
	274	}
	275
	276	/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
	277	/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
	278
	279	#define __swp_type(x) (((x).val >> 5) & 0x7f)
	280	#define __swp_offset(x) ((x).val >> 12)
	281	#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) \| ((offset) << 12) })
	282	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	283	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	284
	285	#define kern_addr_valid(addr) (1)
	286
	287	#include <asm-generic/pgtable.h>
	288
	289	/*
	290	* No page table caches to initialise
	291	*/
	292	#define pgtable_cache_init() do { } while (0)
	293
5d01e6ce MS	294	typedef pte_t *pte_addr_t;
5d01e6ce MS	295
1da177e4 LT	296	#endif /* __ASSEMBLY__ */
1da177e4 LT	297	#endif /* _CRIS_PGTABLE_H */