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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
51533b61 MS |
2 | #ifndef __iop_crc_par_defs_h |
3 | #define __iop_crc_par_defs_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: ../../inst/io_proc/rtl/iop_crc_par.r | |
8 | * id: <not found> | |
9 | * last modfied: Mon Apr 11 16:08:45 2005 | |
10 | * | |
11 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r | |
12 | * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | |
13 | * Any changes here will be lost. | |
14 | * | |
15 | * -*- buffer-read-only: t -*- | |
16 | */ | |
17 | /* Main access macros */ | |
18 | #ifndef REG_RD | |
19 | #define REG_RD( scope, inst, reg ) \ | |
20 | REG_READ( reg_##scope##_##reg, \ | |
21 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
22 | #endif | |
23 | ||
24 | #ifndef REG_WR | |
25 | #define REG_WR( scope, inst, reg, val ) \ | |
26 | REG_WRITE( reg_##scope##_##reg, \ | |
27 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
28 | #endif | |
29 | ||
30 | #ifndef REG_RD_VECT | |
31 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
32 | REG_READ( reg_##scope##_##reg, \ | |
33 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
34 | (index) * STRIDE_##scope##_##reg ) | |
35 | #endif | |
36 | ||
37 | #ifndef REG_WR_VECT | |
38 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
39 | REG_WRITE( reg_##scope##_##reg, \ | |
40 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
41 | (index) * STRIDE_##scope##_##reg, (val) ) | |
42 | #endif | |
43 | ||
44 | #ifndef REG_RD_INT | |
45 | #define REG_RD_INT( scope, inst, reg ) \ | |
46 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
47 | #endif | |
48 | ||
49 | #ifndef REG_WR_INT | |
50 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
51 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
52 | #endif | |
53 | ||
54 | #ifndef REG_RD_INT_VECT | |
55 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
56 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
57 | (index) * STRIDE_##scope##_##reg ) | |
58 | #endif | |
59 | ||
60 | #ifndef REG_WR_INT_VECT | |
61 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
62 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
63 | (index) * STRIDE_##scope##_##reg, (val) ) | |
64 | #endif | |
65 | ||
66 | #ifndef REG_TYPE_CONV | |
67 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
68 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
69 | #endif | |
70 | ||
71 | #ifndef reg_page_size | |
72 | #define reg_page_size 8192 | |
73 | #endif | |
74 | ||
75 | #ifndef REG_ADDR | |
76 | #define REG_ADDR( scope, inst, reg ) \ | |
77 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
78 | #endif | |
79 | ||
80 | #ifndef REG_ADDR_VECT | |
81 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
82 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
83 | (index) * STRIDE_##scope##_##reg ) | |
84 | #endif | |
85 | ||
86 | /* C-code for register scope iop_crc_par */ | |
87 | ||
88 | /* Register rw_cfg, scope iop_crc_par, type rw */ | |
89 | typedef struct { | |
90 | unsigned int mode : 1; | |
91 | unsigned int crc_out : 1; | |
92 | unsigned int rev_out : 1; | |
93 | unsigned int inv_out : 1; | |
94 | unsigned int trig : 2; | |
95 | unsigned int poly : 3; | |
96 | unsigned int dummy1 : 23; | |
97 | } reg_iop_crc_par_rw_cfg; | |
98 | #define REG_RD_ADDR_iop_crc_par_rw_cfg 0 | |
99 | #define REG_WR_ADDR_iop_crc_par_rw_cfg 0 | |
100 | ||
101 | /* Register rw_init_crc, scope iop_crc_par, type rw */ | |
102 | typedef unsigned int reg_iop_crc_par_rw_init_crc; | |
103 | #define REG_RD_ADDR_iop_crc_par_rw_init_crc 4 | |
104 | #define REG_WR_ADDR_iop_crc_par_rw_init_crc 4 | |
105 | ||
106 | /* Register rw_correct_crc, scope iop_crc_par, type rw */ | |
107 | typedef unsigned int reg_iop_crc_par_rw_correct_crc; | |
108 | #define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8 | |
109 | #define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8 | |
110 | ||
111 | /* Register rw_ctrl, scope iop_crc_par, type rw */ | |
112 | typedef struct { | |
113 | unsigned int en : 1; | |
114 | unsigned int dummy1 : 31; | |
115 | } reg_iop_crc_par_rw_ctrl; | |
116 | #define REG_RD_ADDR_iop_crc_par_rw_ctrl 12 | |
117 | #define REG_WR_ADDR_iop_crc_par_rw_ctrl 12 | |
118 | ||
119 | /* Register rw_set_last, scope iop_crc_par, type rw */ | |
120 | typedef struct { | |
121 | unsigned int tr_dif : 1; | |
122 | unsigned int dummy1 : 31; | |
123 | } reg_iop_crc_par_rw_set_last; | |
124 | #define REG_RD_ADDR_iop_crc_par_rw_set_last 16 | |
125 | #define REG_WR_ADDR_iop_crc_par_rw_set_last 16 | |
126 | ||
127 | /* Register rw_wr1byte, scope iop_crc_par, type rw */ | |
128 | typedef struct { | |
129 | unsigned int data : 8; | |
130 | unsigned int dummy1 : 24; | |
131 | } reg_iop_crc_par_rw_wr1byte; | |
132 | #define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20 | |
133 | #define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20 | |
134 | ||
135 | /* Register rw_wr2byte, scope iop_crc_par, type rw */ | |
136 | typedef struct { | |
137 | unsigned int data : 16; | |
138 | unsigned int dummy1 : 16; | |
139 | } reg_iop_crc_par_rw_wr2byte; | |
140 | #define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24 | |
141 | #define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24 | |
142 | ||
143 | /* Register rw_wr3byte, scope iop_crc_par, type rw */ | |
144 | typedef struct { | |
145 | unsigned int data : 24; | |
146 | unsigned int dummy1 : 8; | |
147 | } reg_iop_crc_par_rw_wr3byte; | |
148 | #define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28 | |
149 | #define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28 | |
150 | ||
151 | /* Register rw_wr4byte, scope iop_crc_par, type rw */ | |
152 | typedef struct { | |
153 | unsigned int data : 32; | |
154 | } reg_iop_crc_par_rw_wr4byte; | |
155 | #define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32 | |
156 | #define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32 | |
157 | ||
158 | /* Register rw_wr1byte_last, scope iop_crc_par, type rw */ | |
159 | typedef struct { | |
160 | unsigned int data : 8; | |
161 | unsigned int dummy1 : 24; | |
162 | } reg_iop_crc_par_rw_wr1byte_last; | |
163 | #define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36 | |
164 | #define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36 | |
165 | ||
166 | /* Register rw_wr2byte_last, scope iop_crc_par, type rw */ | |
167 | typedef struct { | |
168 | unsigned int data : 16; | |
169 | unsigned int dummy1 : 16; | |
170 | } reg_iop_crc_par_rw_wr2byte_last; | |
171 | #define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40 | |
172 | #define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40 | |
173 | ||
174 | /* Register rw_wr3byte_last, scope iop_crc_par, type rw */ | |
175 | typedef struct { | |
176 | unsigned int data : 24; | |
177 | unsigned int dummy1 : 8; | |
178 | } reg_iop_crc_par_rw_wr3byte_last; | |
179 | #define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44 | |
180 | #define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44 | |
181 | ||
182 | /* Register rw_wr4byte_last, scope iop_crc_par, type rw */ | |
183 | typedef struct { | |
184 | unsigned int data : 32; | |
185 | } reg_iop_crc_par_rw_wr4byte_last; | |
186 | #define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48 | |
187 | #define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48 | |
188 | ||
189 | /* Register r_stat, scope iop_crc_par, type r */ | |
190 | typedef struct { | |
191 | unsigned int err : 1; | |
192 | unsigned int busy : 1; | |
193 | unsigned int dummy1 : 30; | |
194 | } reg_iop_crc_par_r_stat; | |
195 | #define REG_RD_ADDR_iop_crc_par_r_stat 52 | |
196 | ||
197 | /* Register r_sh_reg, scope iop_crc_par, type r */ | |
198 | typedef unsigned int reg_iop_crc_par_r_sh_reg; | |
199 | #define REG_RD_ADDR_iop_crc_par_r_sh_reg 56 | |
200 | ||
201 | /* Register r_crc, scope iop_crc_par, type r */ | |
202 | typedef unsigned int reg_iop_crc_par_r_crc; | |
203 | #define REG_RD_ADDR_iop_crc_par_r_crc 60 | |
204 | ||
205 | /* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ | |
206 | typedef struct { | |
207 | unsigned int last : 2; | |
208 | unsigned int dummy1 : 30; | |
209 | } reg_iop_crc_par_rw_strb_rec_dif_in; | |
210 | #define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 | |
211 | #define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 | |
212 | ||
213 | ||
214 | /* Constants */ | |
215 | enum { | |
216 | regk_iop_crc_par_calc = 0x00000001, | |
217 | regk_iop_crc_par_ccitt = 0x00000002, | |
218 | regk_iop_crc_par_check = 0x00000000, | |
219 | regk_iop_crc_par_crc16 = 0x00000001, | |
220 | regk_iop_crc_par_crc32 = 0x00000000, | |
221 | regk_iop_crc_par_crc5 = 0x00000003, | |
222 | regk_iop_crc_par_crc5_11 = 0x00000004, | |
223 | regk_iop_crc_par_dif_in = 0x00000002, | |
224 | regk_iop_crc_par_hi = 0x00000000, | |
225 | regk_iop_crc_par_neg = 0x00000002, | |
226 | regk_iop_crc_par_no = 0x00000000, | |
227 | regk_iop_crc_par_pos = 0x00000001, | |
228 | regk_iop_crc_par_pos_neg = 0x00000003, | |
229 | regk_iop_crc_par_rw_cfg_default = 0x00000000, | |
230 | regk_iop_crc_par_rw_ctrl_default = 0x00000000, | |
231 | regk_iop_crc_par_yes = 0x00000001 | |
232 | }; | |
233 | #endif /* __iop_crc_par_defs_h */ |