[linux-block.git] / arch / cris / include / arch-v32 / arch / hwregs / ata_defs.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ata_defs_h
#define __ata_defs_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/ata/rtl/ata_regs.r
 *     id:           ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
 *     last modfied: Mon Apr 11 16:06:25 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
 *      id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif

#ifndef reg_page_size
#define reg_page_size 8192
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )
#endif

/* C-code for register scope ata */

/* Register rw_ctrl0, scope ata, type rw */
typedef struct {
  unsigned int pio_hold  : 6;
  unsigned int pio_strb  : 6;
  unsigned int pio_setup : 6;
  unsigned int dma_hold  : 6;
  unsigned int dma_strb  : 6;
  unsigned int rst       : 1;
  unsigned int en        : 1;
} reg_ata_rw_ctrl0;
#define REG_RD_ADDR_ata_rw_ctrl0 12
#define REG_WR_ADDR_ata_rw_ctrl0 12

/* Register rw_ctrl1, scope ata, type rw */
typedef struct {
  unsigned int udma_tcyc : 4;
  unsigned int udma_tdvs : 4;
  unsigned int dummy1    : 24;
} reg_ata_rw_ctrl1;
#define REG_RD_ADDR_ata_rw_ctrl1 16
#define REG_WR_ADDR_ata_rw_ctrl1 16

/* Register rw_ctrl2, scope ata, type rw */
typedef struct {
  unsigned int data     : 16;
  unsigned int dummy1   : 3;
  unsigned int dma_size : 1;
  unsigned int multi    : 1;
  unsigned int hsh      : 2;
  unsigned int trf_mode : 1;
  unsigned int rw       : 1;
  unsigned int addr     : 3;
  unsigned int cs0      : 1;
  unsigned int cs1      : 1;
  unsigned int sel      : 2;
} reg_ata_rw_ctrl2;
#define REG_RD_ADDR_ata_rw_ctrl2 0
#define REG_WR_ADDR_ata_rw_ctrl2 0

/* Register rs_stat_data, scope ata, type rs */
typedef struct {
  unsigned int data : 16;
  unsigned int dav  : 1;
  unsigned int busy : 1;
  unsigned int dummy1 : 14;
} reg_ata_rs_stat_data;
#define REG_RD_ADDR_ata_rs_stat_data 4

/* Register r_stat_data, scope ata, type r */
typedef struct {
  unsigned int data : 16;
  unsigned int dav  : 1;
  unsigned int busy : 1;
  unsigned int dummy1 : 14;
} reg_ata_r_stat_data;
#define REG_RD_ADDR_ata_r_stat_data 8

/* Register rw_trf_cnt, scope ata, type rw */
typedef struct {
  unsigned int cnt : 17;
  unsigned int dummy1 : 15;
} reg_ata_rw_trf_cnt;
#define REG_RD_ADDR_ata_rw_trf_cnt 20
#define REG_WR_ADDR_ata_rw_trf_cnt 20

/* Register r_stat_misc, scope ata, type r */
typedef struct {
  unsigned int crc : 16;
  unsigned int dummy1 : 16;
} reg_ata_r_stat_misc;
#define REG_RD_ADDR_ata_r_stat_misc 24

/* Register rw_intr_mask, scope ata, type rw */
typedef struct {
  unsigned int bus0 : 1;
  unsigned int bus1 : 1;
  unsigned int bus2 : 1;
  unsigned int bus3 : 1;
  unsigned int dummy1 : 28;
} reg_ata_rw_intr_mask;
#define REG_RD_ADDR_ata_rw_intr_mask 28
#define REG_WR_ADDR_ata_rw_intr_mask 28

/* Register rw_ack_intr, scope ata, type rw */
typedef struct {
  unsigned int bus0 : 1;
  unsigned int bus1 : 1;
  unsigned int bus2 : 1;
  unsigned int bus3 : 1;
  unsigned int dummy1 : 28;
} reg_ata_rw_ack_intr;
#define REG_RD_ADDR_ata_rw_ack_intr 32
#define REG_WR_ADDR_ata_rw_ack_intr 32

/* Register r_intr, scope ata, type r */
typedef struct {
  unsigned int bus0 : 1;
  unsigned int bus1 : 1;
  unsigned int bus2 : 1;
  unsigned int bus3 : 1;
  unsigned int dummy1 : 28;
} reg_ata_r_intr;
#define REG_RD_ADDR_ata_r_intr 36

/* Register r_masked_intr, scope ata, type r */
typedef struct {
  unsigned int bus0 : 1;
  unsigned int bus1 : 1;
  unsigned int bus2 : 1;
  unsigned int bus3 : 1;
  unsigned int dummy1 : 28;
} reg_ata_r_masked_intr;
#define REG_RD_ADDR_ata_r_masked_intr 40


/* Constants */
enum {
  regk_ata_active                          = 0x00000001,
  regk_ata_byte                            = 0x00000001,
  regk_ata_data                            = 0x00000001,
  regk_ata_dma                             = 0x00000001,
  regk_ata_inactive                        = 0x00000000,
  regk_ata_no                              = 0x00000000,
  regk_ata_nodata                          = 0x00000000,
  regk_ata_pio                             = 0x00000000,
  regk_ata_rd                              = 0x00000001,
  regk_ata_reg                             = 0x00000000,
  regk_ata_rw_ctrl0_default                = 0x00000000,
  regk_ata_rw_ctrl2_default                = 0x00000000,
  regk_ata_rw_intr_mask_default            = 0x00000000,
  regk_ata_udma                            = 0x00000002,
  regk_ata_word                            = 0x00000000,
  regk_ata_wr                              = 0x00000000,
  regk_ata_yes                             = 0x00000001
};
#endif /* __ata_defs_h */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
51533b61 MS	2	#ifndef __ata_defs_h
	3	#define __ata_defs_h
	4
	5	/*
	6	* This file is autogenerated from
	7	* file: ../../inst/ata/rtl/ata_regs.r
	8	* id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
	9	* last modfied: Mon Apr 11 16:06:25 2005
	10	*
	11	* by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
	12	* id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
	13	* Any changes here will be lost.
	14	*
	15	* -- buffer-read-only: t --
	16	*/
	17	/* Main access macros */
	18	#ifndef REG_RD
	19	#define REG_RD( scope, inst, reg ) \
	20	REG_READ( reg_##scope##_##reg, \
	21	(inst) + REG_RD_ADDR_##scope##_##reg )
	22	#endif
	23
	24	#ifndef REG_WR
	25	#define REG_WR( scope, inst, reg, val ) \
	26	REG_WRITE( reg_##scope##_##reg, \
	27	(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
	28	#endif
	29
	30	#ifndef REG_RD_VECT
	31	#define REG_RD_VECT( scope, inst, reg, index ) \
	32	REG_READ( reg_##scope##_##reg, \
	33	(inst) + REG_RD_ADDR_##scope##_##reg + \
	34	(index) * STRIDE_##scope##_##reg )
	35	#endif
	36
	37	#ifndef REG_WR_VECT
	38	#define REG_WR_VECT( scope, inst, reg, index, val ) \
	39	REG_WRITE( reg_##scope##_##reg, \
	40	(inst) + REG_WR_ADDR_##scope##_##reg + \
	41	(index) * STRIDE_##scope##_##reg, (val) )
	42	#endif
	43
	44	#ifndef REG_RD_INT
	45	#define REG_RD_INT( scope, inst, reg ) \
	46	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
	47	#endif
	48
	49	#ifndef REG_WR_INT
	50	#define REG_WR_INT( scope, inst, reg, val ) \
	51	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
	52	#endif
	53
	54	#ifndef REG_RD_INT_VECT
	55	#define REG_RD_INT_VECT( scope, inst, reg, index ) \
	56	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	57	(index) * STRIDE_##scope##_##reg )
	58	#endif
	59
	60	#ifndef REG_WR_INT_VECT
	61	#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
	62	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	63	(index) * STRIDE_##scope##_##reg, (val) )
	64	#endif
	65
66	#ifndef REG_TYPE_CONV
67	#define REG_TYPE_CONV( type, orgtype, val ) \
68	( { union { orgtype o; type n; } r; r.o = val; r.n; } )
69	#endif
70
71	#ifndef reg_page_size
72	#define reg_page_size 8192
73	#endif
74
75	#ifndef REG_ADDR
76	#define REG_ADDR( scope, inst, reg ) \
77	( (inst) + REG_RD_ADDR_##scope##_##reg )
78	#endif
79
80	#ifndef REG_ADDR_VECT
81	#define REG_ADDR_VECT( scope, inst, reg, index ) \
82	( (inst) + REG_RD_ADDR_##scope##_##reg + \
83	(index) * STRIDE_##scope##_##reg )
84	#endif
85
86	/* C-code for register scope ata */
87
88	/* Register rw_ctrl0, scope ata, type rw */
89	typedef struct {
90	unsigned int pio_hold : 6;
91	unsigned int pio_strb : 6;
92	unsigned int pio_setup : 6;
93	unsigned int dma_hold : 6;
94	unsigned int dma_strb : 6;
95	unsigned int rst : 1;
96	unsigned int en : 1;
97	} reg_ata_rw_ctrl0;
98	#define REG_RD_ADDR_ata_rw_ctrl0 12
99	#define REG_WR_ADDR_ata_rw_ctrl0 12
100
101	/* Register rw_ctrl1, scope ata, type rw */
102	typedef struct {
103	unsigned int udma_tcyc : 4;
104	unsigned int udma_tdvs : 4;
105	unsigned int dummy1 : 24;
106	} reg_ata_rw_ctrl1;
107	#define REG_RD_ADDR_ata_rw_ctrl1 16
108	#define REG_WR_ADDR_ata_rw_ctrl1 16
109
110	/* Register rw_ctrl2, scope ata, type rw */
111	typedef struct {
112	unsigned int data : 16;
113	unsigned int dummy1 : 3;
114	unsigned int dma_size : 1;
115	unsigned int multi : 1;
116	unsigned int hsh : 2;
117	unsigned int trf_mode : 1;
118	unsigned int rw : 1;
119	unsigned int addr : 3;
120	unsigned int cs0 : 1;
121	unsigned int cs1 : 1;
122	unsigned int sel : 2;
123	} reg_ata_rw_ctrl2;
124	#define REG_RD_ADDR_ata_rw_ctrl2 0
125	#define REG_WR_ADDR_ata_rw_ctrl2 0
126
127	/* Register rs_stat_data, scope ata, type rs */
128	typedef struct {
129	unsigned int data : 16;
130	unsigned int dav : 1;
131	unsigned int busy : 1;
132	unsigned int dummy1 : 14;
133	} reg_ata_rs_stat_data;
134	#define REG_RD_ADDR_ata_rs_stat_data 4
135
136	/* Register r_stat_data, scope ata, type r */
137	typedef struct {
138	unsigned int data : 16;
139	unsigned int dav : 1;
140	unsigned int busy : 1;
141	unsigned int dummy1 : 14;
142	} reg_ata_r_stat_data;
143	#define REG_RD_ADDR_ata_r_stat_data 8
144
145	/* Register rw_trf_cnt, scope ata, type rw */
146	typedef struct {
147	unsigned int cnt : 17;
148	unsigned int dummy1 : 15;
149	} reg_ata_rw_trf_cnt;
150	#define REG_RD_ADDR_ata_rw_trf_cnt 20
151	#define REG_WR_ADDR_ata_rw_trf_cnt 20
152
153	/* Register r_stat_misc, scope ata, type r */
154	typedef struct {
155	unsigned int crc : 16;
156	unsigned int dummy1 : 16;
157	} reg_ata_r_stat_misc;
158	#define REG_RD_ADDR_ata_r_stat_misc 24
159
160	/* Register rw_intr_mask, scope ata, type rw */
161	typedef struct {
162	unsigned int bus0 : 1;
163	unsigned int bus1 : 1;
164	unsigned int bus2 : 1;
165	unsigned int bus3 : 1;
166	unsigned int dummy1 : 28;
167	} reg_ata_rw_intr_mask;
168	#define REG_RD_ADDR_ata_rw_intr_mask 28
169	#define REG_WR_ADDR_ata_rw_intr_mask 28
170
171	/* Register rw_ack_intr, scope ata, type rw */
172	typedef struct {
173	unsigned int bus0 : 1;
174	unsigned int bus1 : 1;
175	unsigned int bus2 : 1;
176	unsigned int bus3 : 1;
177	unsigned int dummy1 : 28;
178	} reg_ata_rw_ack_intr;
179	#define REG_RD_ADDR_ata_rw_ack_intr 32
180	#define REG_WR_ADDR_ata_rw_ack_intr 32
181
182	/* Register r_intr, scope ata, type r */
183	typedef struct {
184	unsigned int bus0 : 1;
185	unsigned int bus1 : 1;
186	unsigned int bus2 : 1;
187	unsigned int bus3 : 1;
188	unsigned int dummy1 : 28;
189	} reg_ata_r_intr;
190	#define REG_RD_ADDR_ata_r_intr 36
191
192	/* Register r_masked_intr, scope ata, type r */
193	typedef struct {
194	unsigned int bus0 : 1;
195	unsigned int bus1 : 1;
196	unsigned int bus2 : 1;
197	unsigned int bus3 : 1;
198	unsigned int dummy1 : 28;
199	} reg_ata_r_masked_intr;
200	#define REG_RD_ADDR_ata_r_masked_intr 40
201
202
203	/* Constants */
204	enum {
205	regk_ata_active = 0x00000001,
206	regk_ata_byte = 0x00000001,
207	regk_ata_data = 0x00000001,
208	regk_ata_dma = 0x00000001,
209	regk_ata_inactive = 0x00000000,
210	regk_ata_no = 0x00000000,
211	regk_ata_nodata = 0x00000000,
212	regk_ata_pio = 0x00000000,
213	regk_ata_rd = 0x00000001,
214	regk_ata_reg = 0x00000000,
215	regk_ata_rw_ctrl0_default = 0x00000000,
216	regk_ata_rw_ctrl2_default = 0x00000000,
217	regk_ata_rw_intr_mask_default = 0x00000000,
218	regk_ata_udma = 0x00000002,
219	regk_ata_word = 0x00000000,
220	regk_ata_wr = 0x00000000,
221	regk_ata_yes = 0x00000001
222	};
223	#endif /* __ata_defs_h */