License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[linux-block.git] / arch / cris / include / arch-v32 / arch / hwregs / asm / ata_defs_asm.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
51533b61
MS
2#ifndef __ata_defs_asm_h
3#define __ata_defs_asm_h
4
5/*
6 * This file is autogenerated from
7 * file: ../../inst/ata/rtl/ata_regs.r
8 * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
9 * last modfied: Mon Apr 11 16:06:25 2005
10 *
11 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r
12 * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
13 * Any changes here will be lost.
14 *
15 * -*- buffer-read-only: t -*-
16 */
17
18#ifndef REG_FIELD
19#define REG_FIELD( scope, reg, field, value ) \
20 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
21#define REG_FIELD_X_( value, shift ) ((value) << shift)
22#endif
23
24#ifndef REG_STATE
25#define REG_STATE( scope, reg, field, symbolic_value ) \
26 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
27#define REG_STATE_X_( k, shift ) (k << shift)
28#endif
29
30#ifndef REG_MASK
31#define REG_MASK( scope, reg, field ) \
32 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
33#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
34#endif
35
36#ifndef REG_LSB
37#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
38#endif
39
40#ifndef REG_BIT
41#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
42#endif
43
44#ifndef REG_ADDR
45#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
46#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
47#endif
48
49#ifndef REG_ADDR_VECT
50#define REG_ADDR_VECT( scope, inst, reg, index ) \
51 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 STRIDE_##scope##_##reg )
53#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
54 ((inst) + offs + (index) * stride)
55#endif
56
57/* Register rw_ctrl0, scope ata, type rw */
58#define reg_ata_rw_ctrl0___pio_hold___lsb 0
59#define reg_ata_rw_ctrl0___pio_hold___width 6
60#define reg_ata_rw_ctrl0___pio_strb___lsb 6
61#define reg_ata_rw_ctrl0___pio_strb___width 6
62#define reg_ata_rw_ctrl0___pio_setup___lsb 12
63#define reg_ata_rw_ctrl0___pio_setup___width 6
64#define reg_ata_rw_ctrl0___dma_hold___lsb 18
65#define reg_ata_rw_ctrl0___dma_hold___width 6
66#define reg_ata_rw_ctrl0___dma_strb___lsb 24
67#define reg_ata_rw_ctrl0___dma_strb___width 6
68#define reg_ata_rw_ctrl0___rst___lsb 30
69#define reg_ata_rw_ctrl0___rst___width 1
70#define reg_ata_rw_ctrl0___rst___bit 30
71#define reg_ata_rw_ctrl0___en___lsb 31
72#define reg_ata_rw_ctrl0___en___width 1
73#define reg_ata_rw_ctrl0___en___bit 31
74#define reg_ata_rw_ctrl0_offset 12
75
76/* Register rw_ctrl1, scope ata, type rw */
77#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0
78#define reg_ata_rw_ctrl1___udma_tcyc___width 4
79#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4
80#define reg_ata_rw_ctrl1___udma_tdvs___width 4
81#define reg_ata_rw_ctrl1_offset 16
82
83/* Register rw_ctrl2, scope ata, type rw */
84#define reg_ata_rw_ctrl2___data___lsb 0
85#define reg_ata_rw_ctrl2___data___width 16
86#define reg_ata_rw_ctrl2___dma_size___lsb 19
87#define reg_ata_rw_ctrl2___dma_size___width 1
88#define reg_ata_rw_ctrl2___dma_size___bit 19
89#define reg_ata_rw_ctrl2___multi___lsb 20
90#define reg_ata_rw_ctrl2___multi___width 1
91#define reg_ata_rw_ctrl2___multi___bit 20
92#define reg_ata_rw_ctrl2___hsh___lsb 21
93#define reg_ata_rw_ctrl2___hsh___width 2
94#define reg_ata_rw_ctrl2___trf_mode___lsb 23
95#define reg_ata_rw_ctrl2___trf_mode___width 1
96#define reg_ata_rw_ctrl2___trf_mode___bit 23
97#define reg_ata_rw_ctrl2___rw___lsb 24
98#define reg_ata_rw_ctrl2___rw___width 1
99#define reg_ata_rw_ctrl2___rw___bit 24
100#define reg_ata_rw_ctrl2___addr___lsb 25
101#define reg_ata_rw_ctrl2___addr___width 3
102#define reg_ata_rw_ctrl2___cs0___lsb 28
103#define reg_ata_rw_ctrl2___cs0___width 1
104#define reg_ata_rw_ctrl2___cs0___bit 28
105#define reg_ata_rw_ctrl2___cs1___lsb 29
106#define reg_ata_rw_ctrl2___cs1___width 1
107#define reg_ata_rw_ctrl2___cs1___bit 29
108#define reg_ata_rw_ctrl2___sel___lsb 30
109#define reg_ata_rw_ctrl2___sel___width 2
110#define reg_ata_rw_ctrl2_offset 0
111
112/* Register rs_stat_data, scope ata, type rs */
113#define reg_ata_rs_stat_data___data___lsb 0
114#define reg_ata_rs_stat_data___data___width 16
115#define reg_ata_rs_stat_data___dav___lsb 16
116#define reg_ata_rs_stat_data___dav___width 1
117#define reg_ata_rs_stat_data___dav___bit 16
118#define reg_ata_rs_stat_data___busy___lsb 17
119#define reg_ata_rs_stat_data___busy___width 1
120#define reg_ata_rs_stat_data___busy___bit 17
121#define reg_ata_rs_stat_data_offset 4
122
123/* Register r_stat_data, scope ata, type r */
124#define reg_ata_r_stat_data___data___lsb 0
125#define reg_ata_r_stat_data___data___width 16
126#define reg_ata_r_stat_data___dav___lsb 16
127#define reg_ata_r_stat_data___dav___width 1
128#define reg_ata_r_stat_data___dav___bit 16
129#define reg_ata_r_stat_data___busy___lsb 17
130#define reg_ata_r_stat_data___busy___width 1
131#define reg_ata_r_stat_data___busy___bit 17
132#define reg_ata_r_stat_data_offset 8
133
134/* Register rw_trf_cnt, scope ata, type rw */
135#define reg_ata_rw_trf_cnt___cnt___lsb 0
136#define reg_ata_rw_trf_cnt___cnt___width 17
137#define reg_ata_rw_trf_cnt_offset 20
138
139/* Register r_stat_misc, scope ata, type r */
140#define reg_ata_r_stat_misc___crc___lsb 0
141#define reg_ata_r_stat_misc___crc___width 16
142#define reg_ata_r_stat_misc_offset 24
143
144/* Register rw_intr_mask, scope ata, type rw */
145#define reg_ata_rw_intr_mask___bus0___lsb 0
146#define reg_ata_rw_intr_mask___bus0___width 1
147#define reg_ata_rw_intr_mask___bus0___bit 0
148#define reg_ata_rw_intr_mask___bus1___lsb 1
149#define reg_ata_rw_intr_mask___bus1___width 1
150#define reg_ata_rw_intr_mask___bus1___bit 1
151#define reg_ata_rw_intr_mask___bus2___lsb 2
152#define reg_ata_rw_intr_mask___bus2___width 1
153#define reg_ata_rw_intr_mask___bus2___bit 2
154#define reg_ata_rw_intr_mask___bus3___lsb 3
155#define reg_ata_rw_intr_mask___bus3___width 1
156#define reg_ata_rw_intr_mask___bus3___bit 3
157#define reg_ata_rw_intr_mask_offset 28
158
159/* Register rw_ack_intr, scope ata, type rw */
160#define reg_ata_rw_ack_intr___bus0___lsb 0
161#define reg_ata_rw_ack_intr___bus0___width 1
162#define reg_ata_rw_ack_intr___bus0___bit 0
163#define reg_ata_rw_ack_intr___bus1___lsb 1
164#define reg_ata_rw_ack_intr___bus1___width 1
165#define reg_ata_rw_ack_intr___bus1___bit 1
166#define reg_ata_rw_ack_intr___bus2___lsb 2
167#define reg_ata_rw_ack_intr___bus2___width 1
168#define reg_ata_rw_ack_intr___bus2___bit 2
169#define reg_ata_rw_ack_intr___bus3___lsb 3
170#define reg_ata_rw_ack_intr___bus3___width 1
171#define reg_ata_rw_ack_intr___bus3___bit 3
172#define reg_ata_rw_ack_intr_offset 32
173
174/* Register r_intr, scope ata, type r */
175#define reg_ata_r_intr___bus0___lsb 0
176#define reg_ata_r_intr___bus0___width 1
177#define reg_ata_r_intr___bus0___bit 0
178#define reg_ata_r_intr___bus1___lsb 1
179#define reg_ata_r_intr___bus1___width 1
180#define reg_ata_r_intr___bus1___bit 1
181#define reg_ata_r_intr___bus2___lsb 2
182#define reg_ata_r_intr___bus2___width 1
183#define reg_ata_r_intr___bus2___bit 2
184#define reg_ata_r_intr___bus3___lsb 3
185#define reg_ata_r_intr___bus3___width 1
186#define reg_ata_r_intr___bus3___bit 3
187#define reg_ata_r_intr_offset 36
188
189/* Register r_masked_intr, scope ata, type r */
190#define reg_ata_r_masked_intr___bus0___lsb 0
191#define reg_ata_r_masked_intr___bus0___width 1
192#define reg_ata_r_masked_intr___bus0___bit 0
193#define reg_ata_r_masked_intr___bus1___lsb 1
194#define reg_ata_r_masked_intr___bus1___width 1
195#define reg_ata_r_masked_intr___bus1___bit 1
196#define reg_ata_r_masked_intr___bus2___lsb 2
197#define reg_ata_r_masked_intr___bus2___width 1
198#define reg_ata_r_masked_intr___bus2___bit 2
199#define reg_ata_r_masked_intr___bus3___lsb 3
200#define reg_ata_r_masked_intr___bus3___width 1
201#define reg_ata_r_masked_intr___bus3___bit 3
202#define reg_ata_r_masked_intr_offset 40
203
204
205/* Constants */
206#define regk_ata_active 0x00000001
207#define regk_ata_byte 0x00000001
208#define regk_ata_data 0x00000001
209#define regk_ata_dma 0x00000001
210#define regk_ata_inactive 0x00000000
211#define regk_ata_no 0x00000000
212#define regk_ata_nodata 0x00000000
213#define regk_ata_pio 0x00000000
214#define regk_ata_rd 0x00000001
215#define regk_ata_reg 0x00000000
216#define regk_ata_rw_ctrl0_default 0x00000000
217#define regk_ata_rw_ctrl2_default 0x00000000
218#define regk_ata_rw_intr_mask_default 0x00000000
219#define regk_ata_udma 0x00000002
220#define regk_ata_word 0x00000000
221#define regk_ata_wr 0x00000000
222#define regk_ata_yes 0x00000001
223#endif /* __ata_defs_asm_h */