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License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[linux-2.6-block.git] / arch / cris / arch-v32 / kernel / kgdb.c
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
51533b61
MS		 2/*
3 * arch/cris/arch-v32/kernel/kgdb.c
4 *
5 * CRIS v32 version by Orjan Friberg, Axis Communications AB.
6 *
7 * S390 version
8 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
9 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
10 *
11 * Originally written by Glenn Engel, Lake Stevens Instrument Division
12 *
13 * Contributed by HP Systems
14 *
15 * Modified for SPARC by Stu Grossman, Cygnus Support.
16 *
17 * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
18 * Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
19 *
20 * Copyright (C) 1995 Andreas Busse
21 */
22
23/* FIXME: Check the documentation. */
24
25/*
26 * kgdb usage notes:
27 * -----------------
28 *
29 * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be
30 * built with different gcc flags: "-g" is added to get debug infos, and
31 * "-fomit-frame-pointer" is omitted to make debugging easier. Since the
32 * resulting kernel will be quite big (approx. > 7 MB), it will be stripped
33 * before compresion. Such a kernel will behave just as usually, except if
34 * given a "debug=<device>" command line option. (Only serial devices are
35 * allowed for <device>, i.e. no printers or the like; possible values are
36 * machine depedend and are the same as for the usual debug device, the one
37 * for logging kernel messages.) If that option is given and the device can be
38 * initialized, the kernel will connect to the remote gdb in trap_init(). The
39 * serial parameters are fixed to 8N1 and 115200 bps, for easyness of
40 * implementation.
41 *
42 * To start a debugging session, start that gdb with the debugging kernel
43 * image (the one with the symbols, vmlinux.debug) named on the command line.
44 * This file will be used by gdb to get symbol and debugging infos about the
45 * kernel. Next, select remote debug mode by
46 * target remote <device>
47 * where <device> is the name of the serial device over which the debugged
48 * machine is connected. Maybe you have to adjust the baud rate by
49 * set remotebaud <rate>
50 * or also other parameters with stty:
51 * shell stty ... </dev/...
52 * If the kernel to debug has already booted, it waited for gdb and now
53 * connects, and you'll see a breakpoint being reported. If the kernel isn't
54 * running yet, start it now. The order of gdb and the kernel doesn't matter.
55 * Another thing worth knowing about in the getting-started phase is how to
56 * debug the remote protocol itself. This is activated with
57 * set remotedebug 1
58 * gdb will then print out each packet sent or received. You'll also get some
59 * messages about the gdb stub on the console of the debugged machine.
60 *
61 * If all that works, you can use lots of the usual debugging techniques on
62 * the kernel, e.g. inspecting and changing variables/memory, setting
63 * breakpoints, single stepping and so on. It's also possible to interrupt the
64 * debugged kernel by pressing C-c in gdb. Have fun! :-)
65 *
66 * The gdb stub is entered (and thus the remote gdb gets control) in the
67 * following situations:
68 *
69 * - If breakpoint() is called. This is just after kgdb initialization, or if
70 * a breakpoint() call has been put somewhere into the kernel source.
71 * (Breakpoints can of course also be set the usual way in gdb.)
72 * In eLinux, we call breakpoint() in init/main.c after IRQ initialization.
73 *
74 * - If there is a kernel exception, i.e. bad_super_trap() or die_if_kernel()
75 * are entered. All the CPU exceptions are mapped to (more or less..., see
76 * the hard_trap_info array below) appropriate signal, which are reported
77 * to gdb. die_if_kernel() is usually called after some kind of access
78 * error and thus is reported as SIGSEGV.
79 *
80 * - When panic() is called. This is reported as SIGABRT.
81 *
82 * - If C-c is received over the serial line, which is treated as
83 * SIGINT.
84 *
85 * Of course, all these signals are just faked for gdb, since there is no
86 * signal concept as such for the kernel. It also isn't possible --obviously--
87 * to set signal handlers from inside gdb, or restart the kernel with a
88 * signal.
89 *
90 * Current limitations:
91 *
92 * - While the kernel is stopped, interrupts are disabled for safety reasons
93 * (i.e., variables not changing magically or the like). But this also
94 * means that the clock isn't running anymore, and that interrupts from the
95 * hardware may get lost/not be served in time. This can cause some device
96 * errors...
97 *
98 * - When single-stepping, only one instruction of the current thread is
99 * executed, but interrupts are allowed for that time and will be serviced
100 * if pending. Be prepared for that.
101 *
102 * - All debugging happens in kernel virtual address space. There's no way to
103 * access physical memory not mapped in kernel space, or to access user
104 * space. A way to work around this is using get_user_long & Co. in gdb
105 * expressions, but only for the current process.
106 *
107 * - Interrupting the kernel only works if interrupts are currently allowed,
108 * and the interrupt of the serial line isn't blocked by some other means
109 * (IPL too high, disabled, ...)
110 *
111 * - The gdb stub is currently not reentrant, i.e. errors that happen therein
112 * (e.g. accessing invalid memory) may not be caught correctly. This could
113 * be removed in future by introducing a stack of struct registers.
114 *
115 */
116
117/*
118 * To enable debugger support, two things need to happen. One, a
119 * call to kgdb_init() is necessary in order to allow any breakpoints
120 * or error conditions to be properly intercepted and reported to gdb.
121 * Two, a breakpoint needs to be generated to begin communication. This
122 * is most easily accomplished by a call to breakpoint().
123 *
124 * The following gdb commands are supported:
125 *
126 * command function Return value
127 *
128 * g return the value of the CPU registers hex data or ENN
129 * G set the value of the CPU registers OK or ENN
130 *
131 * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
132 * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
133 *
134 * c Resume at current address SNN ( signal NN)
135 * cAA..AA Continue at address AA..AA SNN
136 *
137 * s Step one instruction SNN
138 * sAA..AA Step one instruction from AA..AA SNN
139 *
140 * k kill
141 *
142 * ? What was the last sigval ? SNN (signal NN)
143 *
144 * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
145 * baud rate
146 *
147 * All commands and responses are sent with a packet which includes a
148 * checksum. A packet consists of
149 *
150 * $<packet info>#<checksum>.
151 *
152 * where
153 * <packet info> :: <characters representing the command or response>
154 * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
155 *
156 * When a packet is received, it is first acknowledged with either '+' or '-'.
157 * '+' indicates a successful transfer. '-' indicates a failed transfer.
158 *
159 * Example:
160 *
161 * Host: Reply:
162 * $m0,10#2a +$00010203040506070809101112131415#42
163 *
164 */
165
166
167#include <linux/string.h>
168#include <linux/signal.h>
169#include <linux/kernel.h>
170#include <linux/delay.h>
171#include <linux/linkage.h>
172#include <linux/reboot.h>
173
174#include <asm/setup.h>
175#include <asm/ptrace.h>
176
177#include <asm/irq.h>
ab43d14d
JN		 178#include <hwregs/reg_map.h>
179#include <hwregs/reg_rdwr.h>
180#include <hwregs/intr_vect_defs.h>
181#include <hwregs/ser_defs.h>
51533b61
MS		 182
183/* From entry.S. */
184extern void gdb_handle_exception(void);
185/* From kgdb_asm.S. */
186extern void kgdb_handle_exception(void);
187
188static int kgdb_started = 0;
189
190/********************************* Register image ****************************/
191
192typedef
193struct register_image
194{
195 /* Offset */
196 unsigned int r0; /* 0x00 */
197 unsigned int r1; /* 0x04 */
198 unsigned int r2; /* 0x08 */
199 unsigned int r3; /* 0x0C */
200 unsigned int r4; /* 0x10 */
201 unsigned int r5; /* 0x14 */
202 unsigned int r6; /* 0x18 */
203 unsigned int r7; /* 0x1C */
204 unsigned int r8; /* 0x20; Frame pointer (if any) */
205 unsigned int r9; /* 0x24 */
206 unsigned int r10; /* 0x28 */
207 unsigned int r11; /* 0x2C */
208 unsigned int r12; /* 0x30 */
209 unsigned int r13; /* 0x34 */
210 unsigned int sp; /* 0x38; R14, Stack pointer */
211 unsigned int acr; /* 0x3C; R15, Address calculation register. */
212
213 unsigned char bz; /* 0x40; P0, 8-bit zero register */
214 unsigned char vr; /* 0x41; P1, Version register (8-bit) */
215 unsigned int pid; /* 0x42; P2, Process ID */
216 unsigned char srs; /* 0x46; P3, Support register select (8-bit) */
217 unsigned short wz; /* 0x47; P4, 16-bit zero register */
218 unsigned int exs; /* 0x49; P5, Exception status */
219 unsigned int eda; /* 0x4D; P6, Exception data address */
220 unsigned int mof; /* 0x51; P7, Multiply overflow register */
221 unsigned int dz; /* 0x55; P8, 32-bit zero register */
222 unsigned int ebp; /* 0x59; P9, Exception base pointer */
223 unsigned int erp; /* 0x5D; P10, Exception return pointer. Contains the PC we are interested in. */
224 unsigned int srp; /* 0x61; P11, Subroutine return pointer */
225 unsigned int nrp; /* 0x65; P12, NMI return pointer */
226 unsigned int ccs; /* 0x69; P13, Condition code stack */
227 unsigned int usp; /* 0x6D; P14, User mode stack pointer */
228 unsigned int spc; /* 0x71; P15, Single step PC */
229 unsigned int pc; /* 0x75; Pseudo register (for the most part set to ERP). */
230
231} registers;
232
233typedef
234struct bp_register_image
235{
236 /* Support register bank 0. */
237 unsigned int s0_0;
238 unsigned int s1_0;
239 unsigned int s2_0;
240 unsigned int s3_0;
241 unsigned int s4_0;
242 unsigned int s5_0;
243 unsigned int s6_0;
244 unsigned int s7_0;
245 unsigned int s8_0;
246 unsigned int s9_0;
247 unsigned int s10_0;
248 unsigned int s11_0;
249 unsigned int s12_0;
250 unsigned int s13_0;
251 unsigned int s14_0;
252 unsigned int s15_0;
253
254 /* Support register bank 1. */
255 unsigned int s0_1;
256 unsigned int s1_1;
257 unsigned int s2_1;
258 unsigned int s3_1;
259 unsigned int s4_1;
260 unsigned int s5_1;
261 unsigned int s6_1;
262 unsigned int s7_1;
263 unsigned int s8_1;
264 unsigned int s9_1;
265 unsigned int s10_1;
266 unsigned int s11_1;
267 unsigned int s12_1;
268 unsigned int s13_1;
269 unsigned int s14_1;
270 unsigned int s15_1;
271
272 /* Support register bank 2. */
273 unsigned int s0_2;
274 unsigned int s1_2;
275 unsigned int s2_2;
276 unsigned int s3_2;
277 unsigned int s4_2;
278 unsigned int s5_2;
279 unsigned int s6_2;
280 unsigned int s7_2;
281 unsigned int s8_2;
282 unsigned int s9_2;
283 unsigned int s10_2;
284 unsigned int s11_2;
285 unsigned int s12_2;
286 unsigned int s13_2;
287 unsigned int s14_2;
288 unsigned int s15_2;
289
290 /* Support register bank 3. */
291 unsigned int s0_3; /* BP_CTRL */
292 unsigned int s1_3; /* BP_I0_START */
293 unsigned int s2_3; /* BP_I0_END */
294 unsigned int s3_3; /* BP_D0_START */
295 unsigned int s4_3; /* BP_D0_END */
296 unsigned int s5_3; /* BP_D1_START */
297 unsigned int s6_3; /* BP_D1_END */
298 unsigned int s7_3; /* BP_D2_START */
299 unsigned int s8_3; /* BP_D2_END */
300 unsigned int s9_3; /* BP_D3_START */
301 unsigned int s10_3; /* BP_D3_END */
302 unsigned int s11_3; /* BP_D4_START */
303 unsigned int s12_3; /* BP_D4_END */
304 unsigned int s13_3; /* BP_D5_START */
305 unsigned int s14_3; /* BP_D5_END */
306 unsigned int s15_3; /* BP_RESERVED */
307
308} support_registers;
309
310enum register_name
311{
312 R0, R1, R2, R3,
313 R4, R5, R6, R7,
314 R8, R9, R10, R11,
315 R12, R13, SP, ACR,
316
317 BZ, VR, PID, SRS,
318 WZ, EXS, EDA, MOF,
319 DZ, EBP, ERP, SRP,
320 NRP, CCS, USP, SPC,
321 PC,
322
323 S0, S1, S2, S3,
324 S4, S5, S6, S7,
325 S8, S9, S10, S11,
326 S12, S13, S14, S15
327
328};
329
330/* The register sizes of the registers in register_name. An unimplemented register
331 is designated by size 0 in this array. */
332static int register_size[] =
333{
334 4, 4, 4, 4,
335 4, 4, 4, 4,
336 4, 4, 4, 4,
337 4, 4, 4, 4,
338
339 1, 1, 4, 1,
340 2, 4, 4, 4,
341 4, 4, 4, 4,
342 4, 4, 4, 4,
343
344 4,
345
346 4, 4, 4, 4,
347 4, 4, 4, 4,
348 4, 4, 4, 4,
349 4, 4, 4
350
351};
352
353/* Contains the register image of the kernel.
354 (Global so that they can be reached from assembler code.) */
355registers reg;
356support_registers sreg;
357
358/************** Prototypes for local library functions ***********************/
359
360/* Copy of strcpy from libc. */
361static char *gdb_cris_strcpy(char *s1, const char *s2);
362
363/* Copy of strlen from libc. */
364static int gdb_cris_strlen(const char *s);
365
366/* Copy of memchr from libc. */
367static void *gdb_cris_memchr(const void *s, int c, int n);
368
369/* Copy of strtol from libc. Does only support base 16. */
370static int gdb_cris_strtol(const char *s, char **endptr, int base);
371
372/********************** Prototypes for local functions. **********************/
373
374/* Write a value to a specified register regno in the register image
375 of the current thread. */
376static int write_register(int regno, char *val);
377
378/* Read a value from a specified register in the register image. Returns the
379 status of the read operation. The register value is returned in valptr. */
380static int read_register(char regno, unsigned int *valptr);
381
382/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
383int getDebugChar(void);
384
51533b61
MS		 385/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
386void putDebugChar(int val);
387
51533b61
MS		 388/* Convert the memory, pointed to by mem into hexadecimal representation.
389 Put the result in buf, and return a pointer to the last character
390 in buf (null). */
391static char *mem2hex(char *buf, unsigned char *mem, int count);
392
51533b61
MS		 393/* Put the content of the array, in binary representation, pointed to by buf
394 into memory pointed to by mem, and return a pointer to
395 the character after the last byte written. */
396static unsigned char *bin2mem(unsigned char *mem, unsigned char *buf, int count);
397
398/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
399 returned. */
400static void getpacket(char *buffer);
401
402/* Send $<data>#<checksum> from the <data> in the array buffer. */
403static void putpacket(char *buffer);
404
405/* Build and send a response packet in order to inform the host the
406 stub is stopped. */
407static void stub_is_stopped(int sigval);
408
409/* All expected commands are sent from remote.c. Send a response according
410 to the description in remote.c. Not static since it needs to be reached
411 from assembler code. */
412void handle_exception(int sigval);
413
414/* Performs a complete re-start from scratch. ETRAX specific. */
415static void kill_restart(void);
416
417/******************** Prototypes for global functions. ***********************/
418
419/* The string str is prepended with the GDB printout token and sent. */
420void putDebugString(const unsigned char *str, int len);
421
422/* A static breakpoint to be used at startup. */
423void breakpoint(void);
424
425/* Avoid warning as the internal_stack is not used in the C-code. */
426#define USEDVAR(name) { if (name) { ; } }
427#define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) }
428
429/********************************** Packet I/O ******************************/
430/* BUFMAX defines the maximum number of characters in
431 inbound/outbound buffers */
432/* FIXME: How do we know it's enough? */
433#define BUFMAX 512
434
435/* Run-length encoding maximum length. Send 64 at most. */
436#define RUNLENMAX 64
437
51533b61
MS		 438/* The inbound/outbound buffers used in packet I/O */
439static char input_buffer[BUFMAX];
440static char output_buffer[BUFMAX];
441
442/* Error and warning messages. */
443enum error_type
444{
4d0d3975 445 SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08
51533b61
MS		 446};
447
448static char *error_message[] =
449{
450 "",
451 "E01 Set current or general thread - H[c,g] - internal error.",
452 "E02 Change register content - P - cannot change read-only register.",
453 "E03 Thread is not alive.", /* T, not used. */
454 "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
455 "E05 Change register content - P - the register is not implemented..",
456 "E06 Change memory content - M - internal error.",
4d0d3975
AS		 457 "E07 Change register content - P - the register is not stored on the stack",
458 "E08 Invalid parameter"
51533b61
MS		 459};
460
461/********************************** Breakpoint *******************************/
462/* Use an internal stack in the breakpoint and interrupt response routines.
463 FIXME: How do we know the size of this stack is enough?
464 Global so it can be reached from assembler code. */
465#define INTERNAL_STACK_SIZE 1024
466char internal_stack[INTERNAL_STACK_SIZE];
467
468/* Due to the breakpoint return pointer, a state variable is needed to keep
469 track of whether it is a static (compiled) or dynamic (gdb-invoked)
470 breakpoint to be handled. A static breakpoint uses the content of register
471 ERP as it is whereas a dynamic breakpoint requires subtraction with 2
472 in order to execute the instruction. The first breakpoint is static; all
473 following are assumed to be dynamic. */
474static int dynamic_bp = 0;
475
476/********************************* String library ****************************/
477/* Single-step over library functions creates trap loops. */
478
479/* Copy char s2[] to s1[]. */
480static char*
481gdb_cris_strcpy(char *s1, const char *s2)
482{
483 char *s = s1;
484
485 for (s = s1; (*s++ = *s2++) != '\0'; )
486 ;
487 return s1;
488}
489
490/* Find length of s[]. */
491static int
492gdb_cris_strlen(const char *s)
493{
494 const char *sc;
495
496 for (sc = s; *sc != '\0'; sc++)
497 ;
498 return (sc - s);
499}
500
501/* Find first occurrence of c in s[n]. */
502static void*
503gdb_cris_memchr(const void *s, int c, int n)
504{
505 const unsigned char uc = c;
506 const unsigned char *su;
507
508 for (su = s; 0 < n; ++su, --n)
509 if (*su == uc)
510 return (void *)su;
511 return NULL;
512}
513/******************************* Standard library ****************************/
514/* Single-step over library functions creates trap loops. */
515/* Convert string to long. */
516static int
517gdb_cris_strtol(const char *s, char **endptr, int base)
518{
519 char *s1;
520 char *sd;
521 int x = 0;
522
42a9a583
HH		 523 for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1)
524 x = x * base + (sd - hex_asc);
51533b61
MS		 525
526 if (endptr) {
527 /* Unconverted suffix is stored in endptr unless endptr is NULL. */
528 *endptr = s1;
529 }
530
531 return x;
532}
533
534/********************************* Register image ****************************/
535
536/* Write a value to a specified register in the register image of the current
4d0d3975 537 thread. Returns status code SUCCESS, E02, E05 or E08. */
51533b61
MS		 538static int
539write_register(int regno, char *val)
540{
541 int status = SUCCESS;
542
543 if (regno >= R0 && regno <= ACR) {
544 /* Consecutive 32-bit registers. */
4d0d3975
AS		 545 if (hex2bin((unsigned char *)&reg.r0 + (regno - R0) * sizeof(unsigned int),
546 val, sizeof(unsigned int)))
547 status = E08;
51533b61
MS		 548
549 } else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) {
550 /* Read-only registers. */
551 status = E02;
552
553 } else if (regno == PID) {
554 /* 32-bit register. (Even though we already checked SRS and WZ, we cannot
555 combine this with the EXS - SPC write since SRS and WZ have different size.) */
4d0d3975
AS		 556 if (hex2bin((unsigned char *)&reg.pid, val, sizeof(unsigned int)))
557 status = E08;
51533b61
MS		 558
559 } else if (regno == SRS) {
560 /* 8-bit register. */
4d0d3975
AS		 561 if (hex2bin((unsigned char *)&reg.srs, val, sizeof(unsigned char)))
562 status = E08;
51533b61
MS		 563
564 } else if (regno >= EXS && regno <= SPC) {
565 /* Consecutive 32-bit registers. */
4d0d3975
AS		 566 if (hex2bin((unsigned char *)&reg.exs + (regno - EXS) * sizeof(unsigned int),
567 val, sizeof(unsigned int)))
568 status = E08;
51533b61
MS		 569
570 } else if (regno == PC) {
571 /* Pseudo-register. Treat as read-only. */
572 status = E02;
573
574 } else if (regno >= S0 && regno <= S15) {
575 /* 32-bit registers. */
4d0d3975
AS		 576 if (hex2bin((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int),
577 val, sizeof(unsigned int)))
578 status = E08;
51533b61
MS		 579 } else {
580 /* Non-existing register. */
581 status = E05;
582 }
583 return status;
584}
585
586/* Read a value from a specified register in the register image. Returns the
587 value in the register or -1 for non-implemented registers. */
588static int
589read_register(char regno, unsigned int *valptr)
590{
591 int status = SUCCESS;
592
593 /* We read the zero registers from the register struct (instead of just returning 0)
594 to catch errors. */
595
596 if (regno >= R0 && regno <= ACR) {
597 /* Consecutive 32-bit registers. */
598 *valptr = *(unsigned int *)((char *)&reg.r0 + (regno - R0) * sizeof(unsigned int));
599
600 } else if (regno == BZ || regno == VR) {
601 /* Consecutive 8-bit registers. */
602 *valptr = (unsigned int)(*(unsigned char *)
603 ((char *)&reg.bz + (regno - BZ) * sizeof(char)));
604
605 } else if (regno == PID) {
606 /* 32-bit register. */
607 *valptr = *(unsigned int *)((char *)&reg.pid);
608
609 } else if (regno == SRS) {
610 /* 8-bit register. */
611 *valptr = (unsigned int)(*(unsigned char *)((char *)&reg.srs));
612
613 } else if (regno == WZ) {
614 /* 16-bit register. */
615 *valptr = (unsigned int)(*(unsigned short *)(char *)&reg.wz);
616
617 } else if (regno >= EXS && regno <= PC) {
618 /* Consecutive 32-bit registers. */
619 *valptr = *(unsigned int *)((char *)&reg.exs + (regno - EXS) * sizeof(unsigned int));
620
621 } else if (regno >= S0 && regno <= S15) {
622 /* Consecutive 32-bit registers, located elsewhere. */
623 *valptr = *(unsigned int *)((char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int));
624
625 } else {
626 /* Non-existing register. */
627 status = E05;
628 }
629 return status;
630
631}
632
633/********************************** Packet I/O ******************************/
51533b61
MS		 634/* Convert the memory, pointed to by mem into hexadecimal representation.
635 Put the result in buf, and return a pointer to the last character
636 in buf (null). */
637
638static char *
639mem2hex(char *buf, unsigned char *mem, int count)
640{
641 int i;
642 int ch;
643
644 if (mem == NULL) {
645 /* Invalid address, caught by 'm' packet handler. */
646 for (i = 0; i < count; i++) {
647 *buf++ = '0';
648 *buf++ = '0';
649 }
650 } else {
651 /* Valid mem address. */
652 for (i = 0; i < count; i++) {
653 ch = *mem++;
50e1499f 654 buf = hex_byte_pack(buf, ch);
51533b61
MS		 655 }
656 }
657 /* Terminate properly. */
658 *buf = '\0';
659 return buf;
660}
661
662/* Same as mem2hex, but puts it in network byte order. */
663static char *
664mem2hex_nbo(char *buf, unsigned char *mem, int count)
665{
666 int i;
667 int ch;
668
669 mem += count - 1;
670 for (i = 0; i < count; i++) {
671 ch = *mem--;
50e1499f 672 buf = hex_byte_pack(buf, ch);
51533b61
MS		 673 }
674
675 /* Terminate properly. */
676 *buf = '\0';
677 return buf;
678}
679
51533b61
MS		 680/* Put the content of the array, in binary representation, pointed to by buf
681 into memory pointed to by mem, and return a pointer to the character after
682 the last byte written.
683 Gdb will escape $, #, and the escape char (0x7d). */
684static unsigned char*
685bin2mem(unsigned char *mem, unsigned char *buf, int count)
686{
687 int i;
688 unsigned char *next;
689 for (i = 0; i < count; i++) {
690 /* Check for any escaped characters. Be paranoid and
691 only unescape chars that should be escaped. */
692 if (*buf == 0x7d) {
693 next = buf + 1;
694 if (*next == 0x3 || *next == 0x4 || *next == 0x5D) {
695 /* #, $, ESC */
696 buf++;
697 *buf += 0x20;
698 }
699 }
700 *mem++ = *buf++;
701 }
702 return mem;
703}
704
705/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
706 returned. */
707static void
708getpacket(char *buffer)
709{
710 unsigned char checksum;
711 unsigned char xmitcsum;
712 int i;
713 int count;
714 char ch;
715
716 do {
717 while((ch = getDebugChar ()) != '$')
718 /* Wait for the start character $ and ignore all other characters */;
719 checksum = 0;
720 xmitcsum = -1;
721 count = 0;
722 /* Read until a # or the end of the buffer is reached */
723 while (count < BUFMAX) {
724 ch = getDebugChar();
725 if (ch == '#')
726 break;
727 checksum = checksum + ch;
728 buffer[count] = ch;
729 count = count + 1;
730 }
731
732 if (count >= BUFMAX)
733 continue;
734
735 buffer[count] = 0;
736
737 if (ch == '#') {
4d0d3975
AS		 738 xmitcsum = hex_to_bin(getDebugChar()) << 4;
739 xmitcsum += hex_to_bin(getDebugChar());
51533b61
MS		 740 if (checksum != xmitcsum) {
741 /* Wrong checksum */
742 putDebugChar('-');
743 } else {
744 /* Correct checksum */
745 putDebugChar('+');
746 /* If sequence characters are received, reply with them */
747 if (buffer[2] == ':') {
748 putDebugChar(buffer[0]);
749 putDebugChar(buffer[1]);
750 /* Remove the sequence characters from the buffer */
751 count = gdb_cris_strlen(buffer);
752 for (i = 3; i <= count; i++)
753 buffer[i - 3] = buffer[i];
754 }
755 }
756 }
757 } while (checksum != xmitcsum);
758}
759
760/* Send $<data>#<checksum> from the <data> in the array buffer. */
761
762static void
763putpacket(char *buffer)
764{
765 int checksum;
766 int runlen;
767 int encode;
768
769 do {
770 char *src = buffer;
771 putDebugChar('$');
772 checksum = 0;
773 while (*src) {
774 /* Do run length encoding */
775 putDebugChar(*src);
776 checksum += *src;
777 runlen = 0;
778 while (runlen < RUNLENMAX && *src == src[runlen]) {
779 runlen++;
780 }
781 if (runlen > 3) {
782 /* Got a useful amount */
783 putDebugChar ('*');
784 checksum += '*';
785 encode = runlen + ' ' - 4;
786 putDebugChar(encode);
787 checksum += encode;
788 src += runlen;
789 } else {
790 src++;
791 }
792 }
793 putDebugChar('#');
42a9a583
HH		 794 putDebugChar(hex_asc_hi(checksum));
795 putDebugChar(hex_asc_lo(checksum));
51533b61
MS		 796 } while(kgdb_started && (getDebugChar() != '+'));
797}
798
799/* The string str is prepended with the GDB printout token and sent. Required
800 in traditional implementations. */
801void
802putDebugString(const unsigned char *str, int len)
803{
804 /* Move SPC forward if we are single-stepping. */
805 asm("spchere:");
806 asm("move $spc, $r10");
807 asm("cmp.d spchere, $r10");
808 asm("bne nosstep");
809 asm("nop");
810 asm("move.d spccont, $r10");
811 asm("move $r10, $spc");
812 asm("nosstep:");
813
814 output_buffer[0] = 'O';
815 mem2hex(&output_buffer[1], (unsigned char *)str, len);
816 putpacket(output_buffer);
817
818 asm("spccont:");
819}
820
821/********************************** Handle exceptions ************************/
822/* Build and send a response packet in order to inform the host the
823 stub is stopped. TAAn...:r...;n...:r...;n...:r...;
824 AA = signal number
825 n... = register number (hex)
826 r... = register contents
827 n... = `thread'
828 r... = thread process ID. This is a hex integer.
829 n... = other string not starting with valid hex digit.
830 gdb should ignore this n,r pair and go on to the next.
831 This way we can extend the protocol. */
832static void
833stub_is_stopped(int sigval)
834{
835 char *ptr = output_buffer;
836 unsigned int reg_cont;
837
838 /* Send trap type (converted to signal) */
839
840 *ptr++ = 'T';
50e1499f 841 ptr = hex_byte_pack(ptr, sigval);
51533b61
MS		 842
843 if (((reg.exs & 0xff00) >> 8) == 0xc) {
844
845 /* Some kind of hardware watchpoint triggered. Find which one
846 and determine its type (read/write/access). */
847 int S, bp, trig_bits = 0, rw_bits = 0;
848 int trig_mask = 0;
849 unsigned int *bp_d_regs = &sreg.s3_3;
850 /* In a lot of cases, the stopped data address will simply be EDA.
851 In some cases, we adjust it to match the watched data range.
852 (We don't want to change the actual EDA though). */
853 unsigned int stopped_data_address;
854 /* The S field of EXS. */
855 S = (reg.exs & 0xffff0000) >> 16;
856
857 if (S & 1) {
858 /* Instruction watchpoint. */
859 /* FIXME: Check against, and possibly adjust reported EDA. */
860 } else {
861 /* Data watchpoint. Find the one that triggered. */
862 for (bp = 0; bp < 6; bp++) {
863
864 /* Dx_RD, Dx_WR in the S field of EXS for this BP. */
865 int bitpos_trig = 1 + bp * 2;
866 /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
867 int bitpos_config = 2 + bp * 4;
868
869 /* Get read/write trig bits for this BP. */
870 trig_bits = (S & (3 << bitpos_trig)) >> bitpos_trig;
871
872 /* Read/write config bits for this BP. */
873 rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
874 if (trig_bits) {
875 /* Sanity check: the BP shouldn't trigger for accesses
876 that it isn't configured for. */
877 if ((rw_bits == 0x1 && trig_bits != 0x1) ||
878 (rw_bits == 0x2 && trig_bits != 0x2))
879 panic("Invalid r/w trigging for this BP");
880
881 /* Mark this BP as trigged for future reference. */
882 trig_mask |= (1 << bp);
883
884 if (reg.eda >= bp_d_regs[bp * 2] &&
885 reg.eda <= bp_d_regs[bp * 2 + 1]) {
25985edc 886 /* EDA within range for this BP; it must be the one
51533b61
MS		 887 we're looking for. */
888 stopped_data_address = reg.eda;
889 break;
890 }
891 }
892 }
893 if (bp < 6) {
894 /* Found a trigged BP with EDA within its configured data range. */
895 } else if (trig_mask) {
896 /* Something triggered, but EDA doesn't match any BP's range. */
897 for (bp = 0; bp < 6; bp++) {
898 /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
899 int bitpos_config = 2 + bp * 4;
900
901 /* Read/write config bits for this BP (needed later). */
902 rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
903
904 if (trig_mask & (1 << bp)) {
905 /* EDA within 31 bytes of the configured start address? */
906 if (reg.eda + 31 >= bp_d_regs[bp * 2]) {
907 /* Changing the reported address to match
908 the start address of the first applicable BP. */
909 stopped_data_address = bp_d_regs[bp * 2];
910 break;
911 } else {
912 /* We continue since we might find another useful BP. */
913 printk("EDA doesn't match trigged BP's range");
914 }
915 }
916 }
917 }
918
919 /* No match yet? */
920 BUG_ON(bp >= 6);
921 /* Note that we report the type according to what the BP is configured
922 for (otherwise we'd never report an 'awatch'), not according to how
923 it trigged. We did check that the trigged bits match what the BP is
924 configured for though. */
925 if (rw_bits == 0x1) {
926 /* read */
927 strncpy(ptr, "rwatch", 6);
928 ptr += 6;
929 } else if (rw_bits == 0x2) {
930 /* write */
931 strncpy(ptr, "watch", 5);
932 ptr += 5;
933 } else if (rw_bits == 0x3) {
934 /* access */
935 strncpy(ptr, "awatch", 6);
936 ptr += 6;
937 } else {
938 panic("Invalid r/w bits for this BP.");
939 }
940
941 *ptr++ = ':';
942 /* Note that we don't read_register(EDA, ...) */
943 ptr = mem2hex_nbo(ptr, (unsigned char *)&stopped_data_address, register_size[EDA]);
944 *ptr++ = ';';
945 }
946 }
947 /* Only send PC, frame and stack pointer. */
948 read_register(PC, &reg_cont);
50e1499f 949 ptr = hex_byte_pack(ptr, PC);
51533b61
MS		 950 *ptr++ = ':';
951 ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[PC]);
952 *ptr++ = ';';
953
954 read_register(R8, &reg_cont);
50e1499f 955 ptr = hex_byte_pack(ptr, R8);
51533b61
MS		 956 *ptr++ = ':';
957 ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[R8]);
958 *ptr++ = ';';
959
960 read_register(SP, &reg_cont);
50e1499f 961 ptr = hex_byte_pack(ptr, SP);
51533b61
MS		 962 *ptr++ = ':';
963 ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[SP]);
964 *ptr++ = ';';
965
966 /* Send ERP as well; this will save us an entire register fetch in some cases. */
967 read_register(ERP, &reg_cont);
50e1499f 968 ptr = hex_byte_pack(ptr, ERP);
51533b61
MS		 969 *ptr++ = ':';
970 ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[ERP]);
971 *ptr++ = ';';
972
973 /* null-terminate and send it off */
974 *ptr = 0;
975 putpacket(output_buffer);
976}
977
978/* Returns the size of an instruction that has a delay slot. */
979
980int insn_size(unsigned long pc)
981{
982 unsigned short opcode = *(unsigned short *)pc;
983 int size = 0;
984
985 switch ((opcode & 0x0f00) >> 8) {
986 case 0x0:
987 case 0x9:
988 case 0xb:
989 size = 2;
990 break;
991 case 0xe:
992 case 0xf:
993 size = 6;
994 break;
995 case 0xd:
996 /* Could be 4 or 6; check more bits. */
997 if ((opcode & 0xff) == 0xff)
998 size = 4;
999 else
1000 size = 6;
1001 break;
1002 default:
1003 panic("Couldn't find size of opcode 0x%x at 0x%lx\n", opcode, pc);
1004 }
1005
1006 return size;
1007}
1008
1009void register_fixup(int sigval)
1010{
1011 /* Compensate for ACR push at the beginning of exception handler. */
1012 reg.sp += 4;
1013
1014 /* Standard case. */
1015 reg.pc = reg.erp;
1016 if (reg.erp & 0x1) {
1017 /* Delay slot bit set. Report as stopped on proper instruction. */
1018 if (reg.spc) {
1019 /* Rely on SPC if set. */
1020 reg.pc = reg.spc;
1021 } else {
1022 /* Calculate the PC from the size of the instruction
1023 that the delay slot we're in belongs to. */
1024 reg.pc += insn_size(reg.erp & ~1) - 1 ;
1025 }
1026 }
1027
1028 if ((reg.exs & 0x3) == 0x0) {
1029 /* Bits 1 - 0 indicate the type of memory operation performed
1030 by the interrupted instruction. 0 means no memory operation,
1031 and EDA is undefined in that case. We zero it to avoid confusion. */
1032 reg.eda = 0;
1033 }
1034
1035 if (sigval == SIGTRAP) {
1036 /* Break 8, single step or hardware breakpoint exception. */
1037
1038 /* Check IDX field of EXS. */
1039 if (((reg.exs & 0xff00) >> 8) == 0x18) {
1040
1041 /* Break 8. */
1042
1043 /* Static (compiled) breakpoints must return to the next instruction
1044 in order to avoid infinite loops (default value of ERP). Dynamic
1045 (gdb-invoked) must subtract the size of the break instruction from
1046 the ERP so that the instruction that was originally in the break
1047 instruction's place will be run when we return from the exception. */
1048 if (!dynamic_bp) {
1049 /* Assuming that all breakpoints are dynamic from now on. */
1050 dynamic_bp = 1;
1051 } else {
1052
1053 /* Only if not in a delay slot. */
1054 if (!(reg.erp & 0x1)) {
1055 reg.erp -= 2;
1056 reg.pc -= 2;
1057 }
1058 }
1059
1060 } else if (((reg.exs & 0xff00) >> 8) == 0x3) {
1061 /* Single step. */
1062 /* Don't fiddle with S1. */
1063
1064 } else if (((reg.exs & 0xff00) >> 8) == 0xc) {
1065
1066 /* Hardware watchpoint exception. */
1067
1068 /* SPC has been updated so that we will get a single step exception
1069 when we return, but we don't want that. */
1070 reg.spc = 0;
1071
1072 /* Don't fiddle with S1. */
1073 }
1074
1075 } else if (sigval == SIGINT) {
1076 /* Nothing special. */
1077 }
1078}
1079
1080static void insert_watchpoint(char type, int addr, int len)
1081{
1082 /* Breakpoint/watchpoint types (GDB terminology):
1083 0 = memory breakpoint for instructions
1084 (not supported; done via memory write instead)
1085 1 = hardware breakpoint for instructions (supported)
1086 2 = write watchpoint (supported)
1087 3 = read watchpoint (supported)
1088 4 = access watchpoint (supported) */
1089
1090 if (type < '1' || type > '4') {
1091 output_buffer[0] = 0;
1092 return;
1093 }
1094
1095 /* Read watchpoints are set as access watchpoints, because of GDB's
1096 inability to deal with pure read watchpoints. */
1097 if (type == '3')
1098 type = '4';
1099
1100 if (type == '1') {
1101 /* Hardware (instruction) breakpoint. */
1102 /* Bit 0 in BP_CTRL holds the configuration for I0. */
1103 if (sreg.s0_3 & 0x1) {
1104 /* Already in use. */
1105 gdb_cris_strcpy(output_buffer, error_message[E04]);
1106 return;
1107 }
1108 /* Configure. */
1109 sreg.s1_3 = addr;
1110 sreg.s2_3 = (addr + len - 1);
1111 sreg.s0_3 |= 1;
1112 } else {
1113 int bp;
1114 unsigned int *bp_d_regs = &sreg.s3_3;
1115
1116 /* The watchpoint allocation scheme is the simplest possible.
1117 For example, if a region is watched for read and
1118 a write watch is requested, a new watchpoint will
1119 be used. Also, if a watch for a region that is already
1120 covered by one or more existing watchpoints, a new
1121 watchpoint will be used. */
1122
1123 /* First, find a free data watchpoint. */
1124 for (bp = 0; bp < 6; bp++) {
1125 /* Each data watchpoint's control registers occupy 2 bits
1126 (hence the 3), starting at bit 2 for D0 (hence the 2)
1127 with 4 bits between for each watchpoint (yes, the 4). */
1128 if (!(sreg.s0_3 & (0x3 << (2 + (bp * 4))))) {
1129 break;
1130 }
1131 }
1132
1133 if (bp > 5) {
1134 /* We're out of watchpoints. */
1135 gdb_cris_strcpy(output_buffer, error_message[E04]);
1136 return;
1137 }
1138
1139 /* Configure the control register first. */
1140 if (type == '3' || type == '4') {
1141 /* Trigger on read. */
1142 sreg.s0_3 |= (1 << (2 + bp * 4));
1143 }
1144 if (type == '2' || type == '4') {
1145 /* Trigger on write. */
1146 sreg.s0_3 |= (2 << (2 + bp * 4));
1147 }
1148
1149 /* Ugly pointer arithmetics to configure the watched range. */
1150 bp_d_regs[bp * 2] = addr;
1151 bp_d_regs[bp * 2 + 1] = (addr + len - 1);
1152 }
1153
1154 /* Set the S1 flag to enable watchpoints. */
1155 reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
1156 gdb_cris_strcpy(output_buffer, "OK");
1157}
1158
1159static void remove_watchpoint(char type, int addr, int len)
1160{
1161 /* Breakpoint/watchpoint types:
1162 0 = memory breakpoint for instructions
1163 (not supported; done via memory write instead)
1164 1 = hardware breakpoint for instructions (supported)
1165 2 = write watchpoint (supported)
1166 3 = read watchpoint (supported)
1167 4 = access watchpoint (supported) */
1168 if (type < '1' || type > '4') {
1169 output_buffer[0] = 0;
1170 return;
1171 }
1172
1173 /* Read watchpoints are set as access watchpoints, because of GDB's
1174 inability to deal with pure read watchpoints. */
1175 if (type == '3')
1176 type = '4';
1177
1178 if (type == '1') {
1179 /* Hardware breakpoint. */
1180 /* Bit 0 in BP_CTRL holds the configuration for I0. */
1181 if (!(sreg.s0_3 & 0x1)) {
1182 /* Not in use. */
1183 gdb_cris_strcpy(output_buffer, error_message[E04]);
1184 return;
1185 }
1186 /* Deconfigure. */
1187 sreg.s1_3 = 0;
1188 sreg.s2_3 = 0;
1189 sreg.s0_3 &= ~1;
1190 } else {
1191 int bp;
1192 unsigned int *bp_d_regs = &sreg.s3_3;
1193 /* Try to find a watchpoint that is configured for the
1194 specified range, then check that read/write also matches. */
1195
1196 /* Ugly pointer arithmetic, since I cannot rely on a
1197 single switch (addr) as there may be several watchpoints with
1198 the same start address for example. */
1199
1200 for (bp = 0; bp < 6; bp++) {
1201 if (bp_d_regs[bp * 2] == addr &&
1202 bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
1203 /* Matching range. */
1204 int bitpos = 2 + bp * 4;
1205 int rw_bits;
1206
1207 /* Read/write bits for this BP. */
1208 rw_bits = (sreg.s0_3 & (0x3 << bitpos)) >> bitpos;
1209
1210 if ((type == '3' && rw_bits == 0x1) ||
1211 (type == '2' && rw_bits == 0x2) ||
1212 (type == '4' && rw_bits == 0x3)) {
1213 /* Read/write matched. */
1214 break;
1215 }
1216 }
1217 }
1218
1219 if (bp > 5) {
1220 /* No watchpoint matched. */
1221 gdb_cris_strcpy(output_buffer, error_message[E04]);
1222 return;
1223 }
1224
1225 /* Found a matching watchpoint. Now, deconfigure it by
1226 both disabling read/write in bp_ctrl and zeroing its
1227 start/end addresses. */
1228 sreg.s0_3 &= ~(3 << (2 + (bp * 4)));
1229 bp_d_regs[bp * 2] = 0;
1230 bp_d_regs[bp * 2 + 1] = 0;
1231 }
1232
1233 /* Note that we don't clear the S1 flag here. It's done when continuing. */
1234 gdb_cris_strcpy(output_buffer, "OK");
1235}
1236
1237
1238
1239/* All expected commands are sent from remote.c. Send a response according
1240 to the description in remote.c. */
1241void
1242handle_exception(int sigval)
1243{
1244 /* Avoid warning of not used. */
1245
1246 USEDFUN(handle_exception);
1247 USEDVAR(internal_stack[0]);
1248
1249 register_fixup(sigval);
1250
1251 /* Send response. */
1252 stub_is_stopped(sigval);
1253
1254 for (;;) {
1255 output_buffer[0] = '\0';
1256 getpacket(input_buffer);
1257 switch (input_buffer[0]) {
1258 case 'g':
1259 /* Read registers: g
1260 Success: Each byte of register data is described by two hex digits.
1261 Registers are in the internal order for GDB, and the bytes
1262 in a register are in the same order the machine uses.
1263 Failure: void. */
1264 {
1265 char *buf;
1266 /* General and special registers. */
1267 buf = mem2hex(output_buffer, (char *)&reg, sizeof(registers));
1268 /* Support registers. */
1269 /* -1 because of the null termination that mem2hex adds. */
1270 mem2hex(buf,
1271 (char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
1272 16 * sizeof(unsigned int));
1273 break;
1274 }
1275 case 'G':
1276 /* Write registers. GXX..XX
1277 Each byte of register data is described by two hex digits.
1278 Success: OK
4d0d3975 1279 Failure: E08. */
51533b61 1280 /* General and special registers. */
4d0d3975
AS		 1281 if (hex2bin((char *)&reg, &input_buffer[1], sizeof(registers)))
1282 gdb_cris_strcpy(output_buffer, error_message[E08]);
51533b61 1283 /* Support registers. */
4d0d3975 1284 else if (hex2bin((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
51533b61 1285 &input_buffer[1] + sizeof(registers),
4d0d3975
AS		 1286 16 * sizeof(unsigned int)))
1287 gdb_cris_strcpy(output_buffer, error_message[E08]);
1288 else
1289 gdb_cris_strcpy(output_buffer, "OK");
51533b61
MS		 1290 break;
1291
1292 case 'P':
1293 /* Write register. Pn...=r...
1294 Write register n..., hex value without 0x, with value r...,
1295 which contains a hex value without 0x and two hex digits
1296 for each byte in the register (target byte order). P1f=11223344 means
1297 set register 31 to 44332211.
1298 Success: OK
1299 Failure: E02, E05 */
1300 {
1301 char *suffix;
1302 int regno = gdb_cris_strtol(&input_buffer[1], &suffix, 16);
1303 int status;
1304
1305 status = write_register(regno, suffix+1);
1306
1307 switch (status) {
1308 case E02:
1309 /* Do not support read-only registers. */
1310 gdb_cris_strcpy(output_buffer, error_message[E02]);
1311 break;
1312 case E05:
1313 /* Do not support non-existing registers. */
1314 gdb_cris_strcpy(output_buffer, error_message[E05]);
1315 break;
4d0d3975
AS		 1316 case E08:
1317 /* Invalid parameter. */
1318 gdb_cris_strcpy(output_buffer, error_message[E08]);
1319 break;
51533b61
MS		 1320 default:
1321 /* Valid register number. */
1322 gdb_cris_strcpy(output_buffer, "OK");
1323 break;
1324 }
1325 }
1326 break;
1327
1328 case 'm':
1329 /* Read from memory. mAA..AA,LLLL
1330 AA..AA is the address and LLLL is the length.
1331 Success: XX..XX is the memory content. Can be fewer bytes than
1332 requested if only part of the data may be read. m6000120a,6c means
1333 retrieve 108 byte from base address 6000120a.
1334 Failure: void. */
1335 {
1336 char *suffix;
1337 unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
1338 &suffix, 16);
1339 int len = gdb_cris_strtol(suffix+1, 0, 16);
1340
1341 /* Bogus read (i.e. outside the kernel's
1342 segment)? . */
1343 if (!((unsigned int)addr >= 0xc0000000 &&
1344 (unsigned int)addr < 0xd0000000))
1345 addr = NULL;
1346
1347 mem2hex(output_buffer, addr, len);
1348 }
1349 break;
1350
1351 case 'X':
1352 /* Write to memory. XAA..AA,LLLL:XX..XX
1353 AA..AA is the start address, LLLL is the number of bytes, and
1354 XX..XX is the binary data.
1355 Success: OK
1356 Failure: void. */
1357 case 'M':
1358 /* Write to memory. MAA..AA,LLLL:XX..XX
1359 AA..AA is the start address, LLLL is the number of bytes, and
1360 XX..XX is the hexadecimal data.
1361 Success: OK
4d0d3975 1362 Failure: E08. */
51533b61
MS		 1363 {
1364 char *lenptr;
1365 char *dataptr;
1366 unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
1367 &lenptr, 16);
1368 int len = gdb_cris_strtol(lenptr+1, &dataptr, 16);
1369 if (*lenptr == ',' && *dataptr == ':') {
1370 if (input_buffer[0] == 'M') {
4d0d3975
AS		 1371 if (hex2bin(addr, dataptr + 1, len))
1372 gdb_cris_strcpy(output_buffer, error_message[E08]);
1373 else
1374 gdb_cris_strcpy(output_buffer, "OK");
51533b61
MS		 1375 } else /* X */ {
1376 bin2mem(addr, dataptr + 1, len);
4d0d3975 1377 gdb_cris_strcpy(output_buffer, "OK");
51533b61 1378 }
4d0d3975 1379 } else {
51533b61
MS		 1380 gdb_cris_strcpy(output_buffer, error_message[E06]);
1381 }
1382 }
1383 break;
1384
1385 case 'c':
1386 /* Continue execution. cAA..AA
1387 AA..AA is the address where execution is resumed. If AA..AA is
1388 omitted, resume at the present address.
1389 Success: return to the executing thread.
1390 Failure: will never know. */
1391
1392 if (input_buffer[1] != '\0') {
1393 /* FIXME: Doesn't handle address argument. */
1394 gdb_cris_strcpy(output_buffer, error_message[E04]);
1395 break;
1396 }
1397
1398 /* Before continuing, make sure everything is set up correctly. */
1399
1400 /* Set the SPC to some unlikely value. */
1401 reg.spc = 0;
1402 /* Set the S1 flag to 0 unless some watchpoint is enabled (since setting
1403 S1 to 0 would also disable watchpoints). (Note that bits 26-31 in BP_CTRL
1404 are reserved, so don't check against those). */
1405 if ((sreg.s0_3 & 0x3fff) == 0) {
1406 reg.ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT));
1407 }
1408
1409 return;
1410
1411 case 's':
1412 /* Step. sAA..AA
1413 AA..AA is the address where execution is resumed. If AA..AA is
1414 omitted, resume at the present address. Success: return to the
1415 executing thread. Failure: will never know. */
1416
1417 if (input_buffer[1] != '\0') {
1418 /* FIXME: Doesn't handle address argument. */
1419 gdb_cris_strcpy(output_buffer, error_message[E04]);
1420 break;
1421 }
1422
1423 /* Set the SPC to PC, which is where we'll return
1424 (deduced previously). */
1425 reg.spc = reg.pc;
1426
1427 /* Set the S1 (first stacked, not current) flag, which will
1428 kick into action when we rfe. */
1429 reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
1430 return;
1431
1432 case 'Z':
1433
1434 /* Insert breakpoint or watchpoint, Ztype,addr,length.
1435 Remote protocol says: A remote target shall return an empty string
1436 for an unrecognized breakpoint or watchpoint packet type. */
1437 {
1438 char *lenptr;
1439 char *dataptr;
1440 int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
1441 int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
1442 char type = input_buffer[1];
1443
1444 insert_watchpoint(type, addr, len);
1445 break;
1446 }
1447
1448 case 'z':
1449 /* Remove breakpoint or watchpoint, Ztype,addr,length.
1450 Remote protocol says: A remote target shall return an empty string
1451 for an unrecognized breakpoint or watchpoint packet type. */
1452 {
1453 char *lenptr;
1454 char *dataptr;
1455 int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
1456 int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
1457 char type = input_buffer[1];
1458
1459 remove_watchpoint(type, addr, len);
1460 break;
1461 }
1462
1463
1464 case '?':
1465 /* The last signal which caused a stop. ?
1466 Success: SAA, where AA is the signal number.
1467 Failure: void. */
1468 output_buffer[0] = 'S';
42a9a583
HH		 1469 output_buffer[1] = hex_asc_hi(sigval);
1470 output_buffer[2] = hex_asc_lo(sigval);
51533b61
MS		 1471 output_buffer[3] = 0;
1472 break;
1473
1474 case 'D':
1475 /* Detach from host. D
1476 Success: OK, and return to the executing thread.
1477 Failure: will never know */
1478 putpacket("OK");
1479 return;
1480
1481 case 'k':
1482 case 'r':
1483 /* kill request or reset request.
1484 Success: restart of target.
1485 Failure: will never know. */
1486 kill_restart();
1487 break;
1488
1489 case 'C':
1490 case 'S':
1491 case '!':
1492 case 'R':
1493 case 'd':
1494 /* Continue with signal sig. Csig;AA..AA
1495 Step with signal sig. Ssig;AA..AA
1496 Use the extended remote protocol. !
1497 Restart the target system. R0
1498 Toggle debug flag. d
1499 Search backwards. tAA:PP,MM
1500 Not supported: E04 */
1501
1502 /* FIXME: What's the difference between not supported
1503 and ignored (below)? */
1504 gdb_cris_strcpy(output_buffer, error_message[E04]);
1505 break;
1506
1507 default:
1508 /* The stub should ignore other request and send an empty
1509 response ($#<checksum>). This way we can extend the protocol and GDB
1510 can tell whether the stub it is talking to uses the old or the new. */
1511 output_buffer[0] = 0;
1512 break;
1513 }
1514 putpacket(output_buffer);
1515 }
1516}
1517
1518void
1519kgdb_init(void)
1520{
1521 reg_intr_vect_rw_mask intr_mask;
1522 reg_ser_rw_intr_mask ser_intr_mask;
1523
1524 /* Configure the kgdb serial port. */
1525#if defined(CONFIG_ETRAX_KGDB_PORT0)
1526 /* Note: no shortcut registered (not handled by multiple_interrupt).
1527 See entry.S. */
1528 set_exception_vector(SER0_INTR_VECT, kgdb_handle_exception);
1529 /* Enable the ser irq in the global config. */
1530 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1531 intr_mask.ser0 = 1;
1532 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1533
1534 ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask);
f2bbc96a 1535 ser_intr_mask.dav = regk_ser_yes;
51533b61
MS		 1536 REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask);
1537#elif defined(CONFIG_ETRAX_KGDB_PORT1)
1538 /* Note: no shortcut registered (not handled by multiple_interrupt).
1539 See entry.S. */
1540 set_exception_vector(SER1_INTR_VECT, kgdb_handle_exception);
1541 /* Enable the ser irq in the global config. */
1542 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1543 intr_mask.ser1 = 1;
1544 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1545
1546 ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask);
f2bbc96a 1547 ser_intr_mask.dav = regk_ser_yes;
51533b61
MS		 1548 REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask);
1549#elif defined(CONFIG_ETRAX_KGDB_PORT2)
1550 /* Note: no shortcut registered (not handled by multiple_interrupt).
1551 See entry.S. */
1552 set_exception_vector(SER2_INTR_VECT, kgdb_handle_exception);
1553 /* Enable the ser irq in the global config. */
1554 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1555 intr_mask.ser2 = 1;
1556 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1557
1558 ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask);
f2bbc96a 1559 ser_intr_mask.dav = regk_ser_yes;
51533b61
MS		 1560 REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask);
1561#elif defined(CONFIG_ETRAX_KGDB_PORT3)
1562 /* Note: no shortcut registered (not handled by multiple_interrupt).
1563 See entry.S. */
1564 set_exception_vector(SER3_INTR_VECT, kgdb_handle_exception);
1565 /* Enable the ser irq in the global config. */
1566 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1567 intr_mask.ser3 = 1;
1568 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1569
1570 ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask);
f2bbc96a 1571 ser_intr_mask.dav = regk_ser_yes;
51533b61
MS		 1572 REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask);
1573#endif
1574
1575}
1576/* Performs a complete re-start from scratch. */
1577static void
1578kill_restart(void)
1579{
1580 machine_restart("");
1581}
1582
1583/* Use this static breakpoint in the start-up only. */
1584
1585void
1586breakpoint(void)
1587{
1588 kgdb_started = 1;
1589 dynamic_bp = 0; /* This is a static, not a dynamic breakpoint. */
1590 __asm__ volatile ("break 8"); /* Jump to kgdb_handle_breakpoint. */
1591}
1592
1593/****************************** End of file **********************************/
Linux 6.x block layer and io_uring tree(s)