[linux-2.6-block.git] / arch / cris / arch-v32 / kernel / head.S

/*
 * CRISv32 kernel startup code.
 *
 * Copyright (C) 2003, Axis Communications AB
 */

#define ASSEMBLER_MACROS_ONLY

/*
 * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so
 * -traditional must not be used when assembling this file.
 */
#include <arch/memmap.h>
#include <hwregs/reg_rdwr.h>
#include <hwregs/intr_vect.h>
#include <hwregs/asm/mmu_defs_asm.h>
#include <hwregs/asm/reg_map_asm.h>
#include <mach/startup.inc>

#define CRAMFS_MAGIC 0x28cd3d45
#define JHEAD_MAGIC 0x1FF528A6
#define JHEAD_SIZE 8
#define RAM_INIT_MAGIC 0x56902387
#define COMMAND_LINE_MAGIC 0x87109563
#define NAND_BOOT_MAGIC 0x9a9db001

	;; NOTE: R8 and R9 carry information from the decompressor (if the
	;; kernel was compressed). They must not be used in the code below
	;; until they are read!

	;; Exported symbols.
	.global etrax_irv
	.global romfs_start
	.global romfs_length
	.global romfs_in_flash
	.global nand_boot
	.global swapper_pg_dir

	;; Dummy section to make it bootable with current VCS simulator
#ifdef CONFIG_ETRAX_VCS_SIM
	.section ".boot", "ax"
	ba tstart
	nop
#endif

	.text
tstart:
	;; This is the entry point of the kernel. The CPU is currently in
	;; supervisor mode.
	;;
	;; 0x00000000 if flash.
	;; 0x40004000 if DRAM.
	;;
	di

	START_CLOCKS

	SETUP_WAIT_STATES

	GIO_INIT

#ifdef CONFIG_SMP
secondary_cpu_entry: /* Entry point for secondary CPUs */
	di
#endif

	;; Setup and enable the MMU. Use same configuration for both the data
	;; and the instruction MMU.
	;;
	;; Note; 3 cycles is needed for a bank-select to take effect. Further;
	;; bank 1 is the instruction MMU, bank 2 is the data MMU.
#ifndef CONFIG_ETRAX_VCS_SIM
	move.d	REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8)	\
		| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4)	\
		| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
#else
	;; Map the virtual DRAM to the RW eprom area at address 0.
	;; Also map 0xa for the hook calls,
	move.d	REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8)	\
		| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4)	\
		| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb)   \
		| REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa), $r0
#endif

	;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00.
	move.d	REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 4)  \
		| REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1

	;; Enable certain page protections and setup linear mapping
	;; for f,e,c,b,4,0.
#ifndef CONFIG_ETRAX_VCS_SIM
	move.d	REG_STATE(mmu, rw_mm_cfg, we, on)		\
		| REG_STATE(mmu, rw_mm_cfg, acc, on)		\
		| REG_STATE(mmu, rw_mm_cfg, ex, on)		\
		| REG_STATE(mmu, rw_mm_cfg, inv, on)		\
		| REG_STATE(mmu, rw_mm_cfg, seg_f, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_e, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_d, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_c, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_b, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_a, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_9, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_8, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_7, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_6, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_5, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_4, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_3, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_2, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_1, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
#else
	move.d	REG_STATE(mmu, rw_mm_cfg, we, on)		\
		| REG_STATE(mmu, rw_mm_cfg, acc, on)		\
		| REG_STATE(mmu, rw_mm_cfg, ex, on)		\
		| REG_STATE(mmu, rw_mm_cfg, inv, on)		\
		| REG_STATE(mmu, rw_mm_cfg, seg_f, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_e, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_d, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_c, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_b, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_a, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_9, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_8, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_7, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_6, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_5, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_4, linear)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_3, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_2, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_1, page)	\
		| REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
#endif

	;; Update instruction MMU.
	move	1, $srs
	nop
	nop
	nop
	move	$r0, $s2	; kbase_hi.
	move	$r1, $s1	; kbase_lo.
	move	$r2, $s0	; mm_cfg, virtual memory configuration.

	;; Update data MMU.
	move	2, $srs
	nop
	nop
	nop
	move	$r0, $s2	; kbase_hi.
	move	$r1, $s1	; kbase_lo
	move	$r2, $s0	; mm_cfg, virtual memory configuration.

	;; Enable data and instruction MMU.
	move	0, $srs
	moveq	0xf, $r0	;  IMMU, DMMU, DCache, Icache on
	nop
	nop
	nop
	move	$r0, $s0
	nop
	nop
	nop

#ifdef CONFIG_SMP
	;; Read CPU ID
	move    0, $srs
	nop
	nop
	nop
	move    $s12, $r0
	cmpq    0, $r0
	beq	master_cpu
	nop
slave_cpu:
	; Time to boot-up. Get stack location provided by master CPU.
	move.d  smp_init_current_idle_thread, $r1
	move.d  [$r1], $sp
	add.d	8192, $sp
	move.d	ebp_start, $r0	; Defined in linker-script.
	move	$r0, $ebp
	jsr	smp_callin
	nop
master_cpu:
	/* Set up entry point for secondary CPUs. The boot ROM has set up
	 * EBP at start of internal memory. The CPU will get there
	 * later when we issue an IPI to them... */
	move.d MEM_INTMEM_START + IPI_INTR_VECT * 4, $r0
	move.d secondary_cpu_entry, $r1
	move.d $r1, [$r0]
#endif
#ifndef CONFIG_ETRAX_VCS_SIM
	; Check if starting from DRAM (network->RAM boot or unpacked
	; compressed kernel), or directly from flash.
	lapcq	., $r0
	and.d	0x7fffffff, $r0 ; Mask off the non-cache bit.
	cmp.d	0x10000, $r0	; Arbitrary, something above this code.
	blo	_inflash0
	nop
#endif

	jump	_inram		; Jump to cached RAM.
	nop

	;; Jumpgate.
_inflash0:
	jump _inflash
	nop

	;; Put the following in a section so that storage for it can be
	;; reclaimed after init is finished.
	.section ".init.text", "ax"

_inflash:

	;; Initialize DRAM.
	cmp.d	RAM_INIT_MAGIC, $r8 ; Already initialized?
	beq	_dram_initialized
	nop

#if defined CONFIG_ETRAXFS
#include "../mach-fs/dram_init.S"
#elif defined CONFIG_CRIS_MACH_ARTPEC3
#include "../mach-a3/dram_init.S"
#else
#error Only ETRAXFS and ARTPEC-3 supported!
#endif


_dram_initialized:
	;; Copy the text and data section to DRAM. This depends on that the
	;; variables used below are correctly set up by the linker script.
	;; The calculated value stored in R4 is used below.
	;; Leave the cramfs file system (piggybacked after the kernel) in flash.
	moveq	0, $r0		; Source.
	move.d	text_start, $r1	; Destination.
	move.d	__vmlinux_end, $r2
	move.d	$r2, $r4
	sub.d	$r1, $r4
1:	move.w	[$r0+], $r3
	move.w	$r3, [$r1+]
	cmp.d	$r2, $r1
	blo	1b
	nop

	;; Check for cramfs.
	moveq	0, $r0
	move.d	romfs_length, $r1
	move.d	$r0, [$r1]
	move.d	[$r4], $r0	; cramfs_super.magic
	cmp.d	CRAMFS_MAGIC, $r0
	bne 1f
	nop

	;; Set length and start of cramfs, set romfs_in_flash flag
	addoq	+4, $r4, $acr
	move.d	[$acr], $r0
	move.d	romfs_length, $r1
	move.d	$r0, [$r1]
	add.d	0xf0000000, $r4	; Add cached flash start in virtual memory.
	move.d	romfs_start, $r1
	move.d	$r4, [$r1]
1:	moveq	1, $r0
	move.d	romfs_in_flash, $r1
	move.d	$r0, [$r1]

	jump	_start_it	; Jump to cached code.
	nop

_inram:
	;; Check if booting from NAND flash; if so, set appropriate flags
	;; and move on.
	cmp.d	NAND_BOOT_MAGIC, $r12
	bne	move_cramfs	; not nand, jump
	moveq	1, $r0
	move.d	nand_boot, $r1	; tell axisflashmap we're booting from NAND
	move.d	$r0, [$r1]
	moveq	0, $r0		; tell axisflashmap romfs is not in
	move.d	romfs_in_flash, $r1 ; (directly accessed) flash
	move.d	$r0, [$r1]
	jump	_start_it	; continue with boot
	nop

move_cramfs:
	;; kernel is in DRAM.
	;; Must figure out if there is a piggybacked rootfs image or not.
	;; Set romfs_length to 0 => no rootfs image available by default.
	moveq	0, $r0
	move.d	romfs_length, $r1
	move.d	$r0, [$r1]

#ifndef CONFIG_ETRAX_VCS_SIM
	;; The kernel could have been unpacked to DRAM by the loader, but
	;; the cramfs image could still be in the flash immediately
	;; following the compressed kernel image. The loader passes the address
	;; of the byte succeeding the last compressed byte in the flash in
	;; register R9 when starting the kernel.
	cmp.d	0x0ffffff8, $r9
	bhs	_no_romfs_in_flash ; R9 points outside the flash area.
	nop
#else
	ba _no_romfs_in_flash
	nop
#endif
	;; cramfs rootfs might to be in flash. Check for it.
	move.d	[$r9], $r0	; cramfs_super.magic
	cmp.d	CRAMFS_MAGIC, $r0
	bne	_no_romfs_in_flash
	nop

	;; found cramfs in flash. set address and size, and romfs_in_flash flag.
	addoq	+4, $r9, $acr
	move.d	[$acr], $r0
	move.d	romfs_length, $r1
	move.d	$r0, [$r1]
	add.d	0xf0000000, $r9	; Add cached flash start in virtual memory.
	move.d	romfs_start, $r1
	move.d	$r9, [$r1]
	moveq	1, $r0
	move.d	romfs_in_flash, $r1
	move.d	$r0, [$r1]

	jump	_start_it	; Jump to cached code.
	nop

_no_romfs_in_flash:
	;; No romfs in flash, so look for cramfs, or jffs2 with jhead,
	;; after kernel in RAM, as is the case with network->RAM boot.
	;; For cramfs, partition starts with magic and length.
	;; For jffs2, a jhead is prepended which contains with magic and length.
	;; The jhead is not part of the jffs2 partition however.
#ifndef CONFIG_ETRAXFS_SIM
	move.d	__vmlinux_end, $r0
#else
	move.d	__end, $r0
#endif
	move.d	[$r0], $r1
	cmp.d	CRAMFS_MAGIC, $r1 ; cramfs magic?
	beq	2f		  ; yes, jump
	nop
	cmp.d	JHEAD_MAGIC, $r1 ; jffs2 (jhead) magic?
	bne	4f		; no, skip copy
	nop
	addq	4, $r0		; location of jffs2 size
	move.d	[$r0+], $r2	; fetch jffs2 size -> r2
				; r0 now points to start of jffs2
	ba	3f
	nop
2:
	addoq	+4, $r0, $acr	; location of cramfs size
	move.d	[$acr], $r2	; fetch cramfs size -> r2
				; r0 still points to start of cramfs
3:
	;; Now, move the root fs to after kernel's BSS

	move.d	_end, $r1	; start of cramfs -> r1
	move.d	romfs_start, $r3
	move.d	$r1, [$r3]	; store at romfs_start (for axisflashmap)
	move.d	romfs_length, $r3
	move.d	$r2, [$r3]	; store size at romfs_length

#ifndef CONFIG_ETRAX_VCS_SIM
	add.d	$r2, $r0	; copy from end and downwards
	add.d	$r2, $r1

	lsrq	1, $r2		; Size is in bytes, we copy words.
	addq    1, $r2
1:
	move.w	[$r0], $r3
	move.w	$r3, [$r1]
	subq	2, $r0
	subq	2, $r1
	subq	1, $r2
	bne	1b
	nop
#endif

4:
	;; BSS move done.
	;; Clear romfs_in_flash flag, as we now know romfs is in DRAM
	;; Also clear nand_boot flag; if we got here, we know we've not
	;; booted from NAND flash.
	moveq	0, $r0
	move.d	romfs_in_flash, $r1
	move.d	$r0, [$r1]
	moveq	0, $r0
	move.d	nand_boot, $r1
	move.d	$r0, [$r1]

	jump	_start_it	; Jump to cached code.
	nop

_start_it:

	;; Check if kernel command line is supplied
	cmp.d	COMMAND_LINE_MAGIC, $r10
	bne	no_command_line
	nop

	move.d	256, $r13
	move.d  cris_command_line, $r10
	or.d	0x80000000, $r11 ; Make it virtual
1:
	move.b  [$r11+], $r1
	move.b  $r1, [$r10+]
	subq	1, $r13
	bne	1b
	nop

no_command_line:

	;; The kernel stack contains a task structure for each task. This
	;; the initial kernel stack is in the same page as the init_task,
	;; but starts at the top of the page, i.e. + 8192 bytes.
	move.d	init_thread_union + 8192, $sp
	move.d	ebp_start, $r0	; Defined in linker-script.
	move	$r0, $ebp
	move.d	etrax_irv, $r1	; Set the exception base register and pointer.
	move.d	$r0, [$r1]

#ifndef CONFIG_ETRAX_VCS_SIM
	;; Clear the BSS region from _bss_start to _end.
	move.d	__bss_start, $r0
	move.d	_end, $r1
1:	clear.d	[$r0+]
	cmp.d	$r1, $r0
	blo 1b
	nop
#endif

#ifdef CONFIG_ETRAX_VCS_SIM
	/* Set the watchdog timeout to something big. Will be removed when */
	/* watchdog can be disabled with command line option */
	move.d  0x7fffffff, $r10
	jsr     CPU_WATCHDOG_TIMEOUT
	nop
#endif

	; Initialize registers to increase determinism
	move.d __bss_start, $r0
	movem [$r0], $r13

#ifdef CONFIG_ETRAX_L2CACHE
	jsr	l2cache_init
	nop
#endif

	jump	start_kernel	; Jump to start_kernel() in init/main.c.
	nop

	.data
etrax_irv:
	.dword 0

; Variables for communication with the Axis flash map driver (axisflashmap),
; and for setting up memory in arch/cris/kernel/setup.c .

; romfs_start is set to the start of the root file system, if it exists
; in directly accessible memory (i.e. NOR Flash when booting from Flash,
; or RAM when booting directly from a network-downloaded RAM image)
romfs_start:
	.dword 0

; romfs_length is set to the size of the root file system image, if it exists
; in directly accessible memory (see romfs_start). Otherwise it is set to 0.
romfs_length:
	.dword 0

; romfs_in_flash is set to 1 if the root file system resides in directly
; accessible flash memory (i.e. NOR flash). It is set to 0 for RAM boot
; or NAND flash boot.
romfs_in_flash:
	.dword 0

; nand_boot is set to 1 when the kernel has been booted from NAND flash
nand_boot:
	.dword 0

swapper_pg_dir = 0xc0002000

	.section ".init.data", "aw"

#if defined CONFIG_ETRAXFS
#include "../mach-fs/hw_settings.S"
#elif defined CONFIG_CRIS_MACH_ARTPEC3
#include "../mach-a3/hw_settings.S"
#else
#error Only ETRAXFS and ARTPEC-3 supported!
#endif
Commit	Line	Data
51533b61 MS	1	/*
	2	* CRISv32 kernel startup code.
	3	*
	4	* Copyright (C) 2003, Axis Communications AB
	5	*/
	6
51533b61 MS	7	#define ASSEMBLER_MACROS_ONLY
	8
	9	/*
	10	* The macros found in mmu_defs_asm.h uses the ## concatenation operator, so
	11	* -traditional must not be used when assembling this file.
	12	*/
556dcee7	13	#include <arch/memmap.h>
c5ec6fb0	14	#include <hwregs/reg_rdwr.h>
96e47669 JN	15	#include <hwregs/intr_vect.h>
	16	#include <hwregs/asm/mmu_defs_asm.h>
	17	#include <hwregs/asm/reg_map_asm.h>
556dcee7	18	#include <mach/startup.inc>
51533b61 MS	19
51533b61 MS	20	#define CRAMFS_MAGIC 0x28cd3d45
96e47669 JN	21	#define JHEAD_MAGIC 0x1FF528A6
96e47669 JN	22	#define JHEAD_SIZE 8
51533b61 MS	23	#define RAM_INIT_MAGIC 0x56902387
51533b61 MS	24	#define COMMAND_LINE_MAGIC 0x87109563
96e47669	25	#define NAND_BOOT_MAGIC 0x9a9db001
51533b61 MS	26
	27	;; NOTE: R8 and R9 carry information from the decompressor (if the
	28	;; kernel was compressed). They must not be used in the code below
	29	;; until they are read!
	30
	31	;; Exported symbols.
	32	.global etrax_irv
	33	.global romfs_start
	34	.global romfs_length
	35	.global romfs_in_flash
96e47669	36	.global nand_boot
51533b61	37	.global swapper_pg_dir
51533b61 MS	38
51533b61 MS	39	;; Dummy section to make it bootable with current VCS simulator
96e47669	40	#ifdef CONFIG_ETRAX_VCS_SIM
51533b61 MS	41	.section ".boot", "ax"
	42	ba tstart
	43	nop
	44	#endif
	45
	46	.text
	47	tstart:
	48	;; This is the entry point of the kernel. The CPU is currently in
	49	;; supervisor mode.
	50	;;
	51	;; 0x00000000 if flash.
	52	;; 0x40004000 if DRAM.
	53	;;
	54	di
	55
96e47669 JN	56	START_CLOCKS
	57
	58	SETUP_WAIT_STATES
	59
f8e47cb0 JN	60	GIO_INIT
f8e47cb0 JN	61
96e47669 JN	62	#ifdef CONFIG_SMP
	63	secondary_cpu_entry: /* Entry point for secondary CPUs */
	64	di
51533b61 MS	65	#endif
	66
	67	;; Setup and enable the MMU. Use same configuration for both the data
	68	;; and the instruction MMU.
	69	;;
	70	;; Note; 3 cycles is needed for a bank-select to take effect. Further;
	71	;; bank 1 is the instruction MMU, bank 2 is the data MMU.
96e47669	72	#ifndef CONFIG_ETRAX_VCS_SIM
51533b61 MS	73	move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
	74	\| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
	75	\| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
	76	#else
	77	;; Map the virtual DRAM to the RW eprom area at address 0.
	78	;; Also map 0xa for the hook calls,
	79	move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
96e47669	80	\| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
51533b61 MS	81	\| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) \
	82	\| REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa), $r0
	83	#endif
	84
	85	;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00.
	86	move.d REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 4) \
	87	\| REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1
	88
	89	;; Enable certain page protections and setup linear mapping
	90	;; for f,e,c,b,4,0.
96e47669	91	#ifndef CONFIG_ETRAX_VCS_SIM
51533b61 MS	92	move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
	93	\| REG_STATE(mmu, rw_mm_cfg, acc, on) \
	94	\| REG_STATE(mmu, rw_mm_cfg, ex, on) \
	95	\| REG_STATE(mmu, rw_mm_cfg, inv, on) \
	96	\| REG_STATE(mmu, rw_mm_cfg, seg_f, linear) \
	97	\| REG_STATE(mmu, rw_mm_cfg, seg_e, linear) \
	98	\| REG_STATE(mmu, rw_mm_cfg, seg_d, page) \
	99	\| REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \
	100	\| REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \
	101	\| REG_STATE(mmu, rw_mm_cfg, seg_a, page) \
	102	\| REG_STATE(mmu, rw_mm_cfg, seg_9, page) \
	103	\| REG_STATE(mmu, rw_mm_cfg, seg_8, page) \
	104	\| REG_STATE(mmu, rw_mm_cfg, seg_7, page) \
	105	\| REG_STATE(mmu, rw_mm_cfg, seg_6, page) \
	106	\| REG_STATE(mmu, rw_mm_cfg, seg_5, page) \
	107	\| REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \
	108	\| REG_STATE(mmu, rw_mm_cfg, seg_3, page) \
	109	\| REG_STATE(mmu, rw_mm_cfg, seg_2, page) \
	110	\| REG_STATE(mmu, rw_mm_cfg, seg_1, page) \
	111	\| REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
	112	#else
	113	move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
	114	\| REG_STATE(mmu, rw_mm_cfg, acc, on) \
	115	\| REG_STATE(mmu, rw_mm_cfg, ex, on) \
	116	\| REG_STATE(mmu, rw_mm_cfg, inv, on) \
	117	\| REG_STATE(mmu, rw_mm_cfg, seg_f, linear) \
	118	\| REG_STATE(mmu, rw_mm_cfg, seg_e, linear) \
	119	\| REG_STATE(mmu, rw_mm_cfg, seg_d, page) \
	120	\| REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \
	121	\| REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \
	122	\| REG_STATE(mmu, rw_mm_cfg, seg_a, linear) \
	123	\| REG_STATE(mmu, rw_mm_cfg, seg_9, page) \
	124	\| REG_STATE(mmu, rw_mm_cfg, seg_8, page) \
	125	\| REG_STATE(mmu, rw_mm_cfg, seg_7, page) \
	126	\| REG_STATE(mmu, rw_mm_cfg, seg_6, page) \
	127	\| REG_STATE(mmu, rw_mm_cfg, seg_5, page) \
	128	\| REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \
	129	\| REG_STATE(mmu, rw_mm_cfg, seg_3, page) \
	130	\| REG_STATE(mmu, rw_mm_cfg, seg_2, page) \
	131	\| REG_STATE(mmu, rw_mm_cfg, seg_1, page) \
	132	\| REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
	133	#endif
	134
	135	;; Update instruction MMU.
	136	move 1, $srs
	137	nop
	138	nop
	139	nop
	140	move $r0, $s2 ; kbase_hi.
	141	move $r1, $s1 ; kbase_lo.
	142	move $r2, $s0 ; mm_cfg, virtual memory configuration.
	143
	144	;; Update data MMU.
	145	move 2, $srs
	146	nop
	147	nop
	148	nop
	149	move $r0, $s2 ; kbase_hi.
	150	move $r1, $s1 ; kbase_lo
	151	move $r2, $s0 ; mm_cfg, virtual memory configuration.
	152
	153	;; Enable data and instruction MMU.
	154	move 0, $srs
	155	moveq 0xf, $r0 ; IMMU, DMMU, DCache, Icache on
156	nop
157	nop
158	nop
159	move $r0, $s0
160	nop
161	nop
162	nop
163
164	#ifdef CONFIG_SMP
165	;; Read CPU ID
166	move 0, $srs
167	nop
168	nop
169	nop
96e47669	170	move $s12, $r0
51533b61 MS	171	cmpq 0, $r0
	172	beq master_cpu
	173	nop
	174	slave_cpu:
51533b61 MS	175	; Time to boot-up. Get stack location provided by master CPU.
	176	move.d smp_init_current_idle_thread, $r1
	177	move.d [$r1], $sp
	178	add.d 8192, $sp
	179	move.d ebp_start, $r0 ; Defined in linker-script.
	180	move $r0, $ebp
	181	jsr smp_callin
	182	nop
	183	master_cpu:
96e47669 JN	184	/* Set up entry point for secondary CPUs. The boot ROM has set up
	185	* EBP at start of internal memory. The CPU will get there
	186	* later when we issue an IPI to them... */
	187	move.d MEM_INTMEM_START + IPI_INTR_VECT * 4, $r0
	188	move.d secondary_cpu_entry, $r1
	189	move.d $r1, [$r0]
51533b61	190	#endif
96e47669 JN	191	#ifndef CONFIG_ETRAX_VCS_SIM
	192	; Check if starting from DRAM (network->RAM boot or unpacked
	193	; compressed kernel), or directly from flash.
51533b61 MS	194	lapcq ., $r0
	195	and.d 0x7fffffff, $r0 ; Mask off the non-cache bit.
	196	cmp.d 0x10000, $r0 ; Arbitrary, something above this code.
	197	blo _inflash0
	198	nop
	199	#endif
	200
	201	jump _inram ; Jump to cached RAM.
	202	nop
	203
	204	;; Jumpgate.
	205	_inflash0:
	206	jump _inflash
	207	nop
	208
	209	;; Put the following in a section so that storage for it can be
	210	;; reclaimed after init is finished.
	211	.section ".init.text", "ax"
	212
	213	_inflash:
	214
	215	;; Initialize DRAM.
	216	cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
	217	beq _dram_initialized
	218	nop
	219
c5ec6fb0 JN	220	#if defined CONFIG_ETRAXFS
	221	#include "../mach-fs/dram_init.S"
	222	#elif defined CONFIG_CRIS_MACH_ARTPEC3
	223	#include "../mach-a3/dram_init.S"
	224	#else
	225	#error Only ETRAXFS and ARTPEC-3 supported!
	226	#endif
	227
51533b61 MS	228
	229	_dram_initialized:
	230	;; Copy the text and data section to DRAM. This depends on that the
	231	;; variables used below are correctly set up by the linker script.
	232	;; The calculated value stored in R4 is used below.
96e47669	233	;; Leave the cramfs file system (piggybacked after the kernel) in flash.
51533b61 MS	234	moveq 0, $r0 ; Source.
	235	move.d text_start, $r1 ; Destination.
	236	move.d __vmlinux_end, $r2
	237	move.d $r2, $r4
	238	sub.d $r1, $r4
	239	1: move.w [$r0+], $r3
	240	move.w $r3, [$r1+]
	241	cmp.d $r2, $r1
	242	blo 1b
	243	nop
	244
96e47669	245	;; Check for cramfs.
51533b61 MS	246	moveq 0, $r0
	247	move.d romfs_length, $r1
	248	move.d $r0, [$r1]
	249	move.d [$r4], $r0 ; cramfs_super.magic
	250	cmp.d CRAMFS_MAGIC, $r0
	251	bne 1f
	252	nop
	253
96e47669	254	;; Set length and start of cramfs, set romfs_in_flash flag
51533b61 MS	255	addoq +4, $r4, $acr
	256	move.d [$acr], $r0
	257	move.d romfs_length, $r1
	258	move.d $r0, [$r1]
	259	add.d 0xf0000000, $r4 ; Add cached flash start in virtual memory.
	260	move.d romfs_start, $r1
	261	move.d $r4, [$r1]
	262	1: moveq 1, $r0
	263	move.d romfs_in_flash, $r1
	264	move.d $r0, [$r1]
	265
	266	jump _start_it ; Jump to cached code.
	267	nop
	268
	269	_inram:
96e47669 JN	270	;; Check if booting from NAND flash; if so, set appropriate flags
	271	;; and move on.
	272	cmp.d NAND_BOOT_MAGIC, $r12
	273	bne move_cramfs ; not nand, jump
51533b61	274	moveq 1, $r0
96e47669	275	move.d nand_boot, $r1 ; tell axisflashmap we're booting from NAND
51533b61	276	move.d $r0, [$r1]
96e47669 JN	277	moveq 0, $r0 ; tell axisflashmap romfs is not in
	278	move.d romfs_in_flash, $r1 ; (directly accessed) flash
	279	move.d $r0, [$r1]
	280	jump _start_it ; continue with boot
51533b61 MS	281	nop
	282
	283	move_cramfs:
96e47669 JN	284	;; kernel is in DRAM.
	285	;; Must figure out if there is a piggybacked rootfs image or not.
	286	;; Set romfs_length to 0 => no rootfs image available by default.
51533b61 MS	287	moveq 0, $r0
	288	move.d romfs_length, $r1
	289	move.d $r0, [$r1]
	290
96e47669	291	#ifndef CONFIG_ETRAX_VCS_SIM
51533b61	292	;; The kernel could have been unpacked to DRAM by the loader, but
96e47669 JN	293	;; the cramfs image could still be in the flash immediately
	294	;; following the compressed kernel image. The loader passes the address
	295	;; of the byte succeeding the last compressed byte in the flash in
51533b61 MS	296	;; register R9 when starting the kernel.
	297	cmp.d 0x0ffffff8, $r9
	298	bhs _no_romfs_in_flash ; R9 points outside the flash area.
	299	nop
	300	#else
	301	ba _no_romfs_in_flash
	302	nop
	303	#endif
96e47669	304	;; cramfs rootfs might to be in flash. Check for it.
51533b61 MS	305	move.d [$r9], $r0 ; cramfs_super.magic
	306	cmp.d CRAMFS_MAGIC, $r0
	307	bne _no_romfs_in_flash
	308	nop
	309
96e47669	310	;; found cramfs in flash. set address and size, and romfs_in_flash flag.
51533b61 MS	311	addoq +4, $r9, $acr
	312	move.d [$acr], $r0
	313	move.d romfs_length, $r1
	314	move.d $r0, [$r1]
	315	add.d 0xf0000000, $r9 ; Add cached flash start in virtual memory.
	316	move.d romfs_start, $r1
	317	move.d $r9, [$r1]
	318	moveq 1, $r0
	319	move.d romfs_in_flash, $r1
	320	move.d $r0, [$r1]
	321
	322	jump _start_it ; Jump to cached code.
	323	nop
	324
	325	_no_romfs_in_flash:
96e47669 JN	326	;; No romfs in flash, so look for cramfs, or jffs2 with jhead,
	327	;; after kernel in RAM, as is the case with network->RAM boot.
	328	;; For cramfs, partition starts with magic and length.
	329	;; For jffs2, a jhead is prepended which contains with magic and length.
	330	;; The jhead is not part of the jffs2 partition however.
51533b61 MS	331	#ifndef CONFIG_ETRAXFS_SIM
	332	move.d __vmlinux_end, $r0
	333	#else
	334	move.d __end, $r0
	335	#endif
	336	move.d [$r0], $r1
96e47669 JN	337	cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic?
	338	beq 2f ; yes, jump
	339	nop
	340	cmp.d JHEAD_MAGIC, $r1 ; jffs2 (jhead) magic?
	341	bne 4f ; no, skip copy
	342	nop
	343	addq 4, $r0 ; location of jffs2 size
	344	move.d [$r0+], $r2 ; fetch jffs2 size -> r2
	345	; r0 now points to start of jffs2
	346	ba 3f
51533b61	347	nop
96e47669 JN	348	2:
	349	addoq +4, $r0, $acr ; location of cramfs size
	350	move.d [$acr], $r2 ; fetch cramfs size -> r2
	351	; r0 still points to start of cramfs
	352	3:
	353	;; Now, move the root fs to after kernel's BSS
51533b61	354
96e47669	355	move.d _end, $r1 ; start of cramfs -> r1
51533b61	356	move.d romfs_start, $r3
96e47669	357	move.d $r1, [$r3] ; store at romfs_start (for axisflashmap)
51533b61	358	move.d romfs_length, $r3
96e47669	359	move.d $r2, [$r3] ; store size at romfs_length
51533b61	360
96e47669 JN	361	#ifndef CONFIG_ETRAX_VCS_SIM
96e47669 JN	362	add.d $r2, $r0 ; copy from end and downwards
51533b61 MS	363	add.d $r2, $r1
	364
	365	lsrq 1, $r2 ; Size is in bytes, we copy words.
	366	addq 1, $r2
	367	1:
	368	move.w [$r0], $r3
	369	move.w $r3, [$r1]
	370	subq 2, $r0
	371	subq 2, $r1
	372	subq 1, $r2
	373	bne 1b
	374	nop
	375	#endif
	376
96e47669 JN	377	4:
	378	;; BSS move done.
	379	;; Clear romfs_in_flash flag, as we now know romfs is in DRAM
	380	;; Also clear nand_boot flag; if we got here, we know we've not
	381	;; booted from NAND flash.
51533b61 MS	382	moveq 0, $r0
	383	move.d romfs_in_flash, $r1
	384	move.d $r0, [$r1]
96e47669 JN	385	moveq 0, $r0
	386	move.d nand_boot, $r1
	387	move.d $r0, [$r1]
51533b61 MS	388
	389	jump _start_it ; Jump to cached code.
	390	nop
	391
	392	_start_it:
	393
	394	;; Check if kernel command line is supplied
	395	cmp.d COMMAND_LINE_MAGIC, $r10
	396	bne no_command_line
	397	nop
	398
	399	move.d 256, $r13
	400	move.d cris_command_line, $r10
	401	or.d 0x80000000, $r11 ; Make it virtual
	402	1:
96e47669 JN	403	move.b [$r11+], $r1
96e47669 JN	404	move.b $r1, [$r10+]
51533b61 MS	405	subq 1, $r13
	406	bne 1b
	407	nop
	408
	409	no_command_line:
	410
	411	;; The kernel stack contains a task structure for each task. This
	412	;; the initial kernel stack is in the same page as the init_task,
	413	;; but starts at the top of the page, i.e. + 8192 bytes.
	414	move.d init_thread_union + 8192, $sp
	415	move.d ebp_start, $r0 ; Defined in linker-script.
	416	move $r0, $ebp
	417	move.d etrax_irv, $r1 ; Set the exception base register and pointer.
	418	move.d $r0, [$r1]
	419
96e47669	420	#ifndef CONFIG_ETRAX_VCS_SIM
51533b61 MS	421	;; Clear the BSS region from _bss_start to _end.
	422	move.d __bss_start, $r0
	423	move.d _end, $r1
	424	1: clear.d [$r0+]
	425	cmp.d $r1, $r0
	426	blo 1b
	427	nop
	428	#endif
	429
96e47669	430	#ifdef CONFIG_ETRAX_VCS_SIM
51533b61 MS	431	/* Set the watchdog timeout to something big. Will be removed when */
	432	/* watchdog can be disabled with command line option */
	433	move.d 0x7fffffff, $r10
	434	jsr CPU_WATCHDOG_TIMEOUT
	435	nop
	436	#endif
	437
	438	; Initialize registers to increase determinism
	439	move.d __bss_start, $r0
	440	movem [$r0], $r13
	441
96e47669 JN	442	#ifdef CONFIG_ETRAX_L2CACHE
	443	jsr l2cache_init
	444	nop
	445	#endif
	446
51533b61 MS	447	jump start_kernel ; Jump to start_kernel() in init/main.c.
	448	nop
	449
	450	.data
	451	etrax_irv:
	452	.dword 0
96e47669 JN	453
	454	; Variables for communication with the Axis flash map driver (axisflashmap),
	455	; and for setting up memory in arch/cris/kernel/setup.c .
	456
	457	; romfs_start is set to the start of the root file system, if it exists
	458	; in directly accessible memory (i.e. NOR Flash when booting from Flash,
	459	; or RAM when booting directly from a network-downloaded RAM image)
51533b61 MS	460	romfs_start:
51533b61 MS	461	.dword 0
96e47669 JN	462
	463	; romfs_length is set to the size of the root file system image, if it exists
	464	; in directly accessible memory (see romfs_start). Otherwise it is set to 0.
51533b61 MS	465	romfs_length:
51533b61 MS	466	.dword 0
96e47669 JN	467
	468	; romfs_in_flash is set to 1 if the root file system resides in directly
	469	; accessible flash memory (i.e. NOR flash). It is set to 0 for RAM boot
	470	; or NAND flash boot.
51533b61 MS	471	romfs_in_flash:
51533b61 MS	472	.dword 0
96e47669 JN	473
	474	; nand_boot is set to 1 when the kernel has been booted from NAND flash
	475	nand_boot:
51533b61 MS	476	.dword 0
	477
	478	swapper_pg_dir = 0xc0002000
	479
	480	.section ".init.data", "aw"
	481
c5ec6fb0 JN	482	#if defined CONFIG_ETRAXFS
	483	#include "../mach-fs/hw_settings.S"
	484	#elif defined CONFIG_CRIS_MACH_ARTPEC3
	485	#include "../mach-a3/hw_settings.S"
	486	#else
	487	#error Only ETRAXFS and ARTPEC-3 supported!
	488	#endif