[linux-2.6-block.git] / arch / cris / arch-v10 / kernel / time.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  linux/arch/cris/arch-v10/kernel/time.c
 *
 *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
 *  Copyright (C) 1999-2002 Axis Communications AB
 *
 */

#include <linux/timex.h>
#include <linux/time.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>
#include <linux/swap.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <asm/types.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/irq_regs.h>

/* define this if you need to use print_timestamp */
/* it will make jiffies at 96 hz instead of 100 hz though */
#undef USE_CASCADE_TIMERS

unsigned long get_ns_in_jiffie(void)
{
	unsigned char timer_count, t1;
	unsigned short presc_count;
	unsigned long ns;
	unsigned long flags;

	local_irq_save(flags);
	timer_count = *R_TIMER0_DATA;
	presc_count = *R_TIM_PRESC_STATUS;
	/* presc_count might be wrapped */
	t1 = *R_TIMER0_DATA;

	if (timer_count != t1){
		/* it wrapped, read prescaler again...  */
		presc_count = *R_TIM_PRESC_STATUS;
		timer_count = t1;
	}
	local_irq_restore(flags);
	if (presc_count >= PRESCALE_VALUE/2 ){
		presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
	} else {
		presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
	}

	ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
	     ( (presc_count) * (1000000000/PRESCALE_FREQ));
	return ns;
}

static u32 cris_v10_gettimeoffset(void)
{
	u32 count;

	/* The timer interrupt comes from Etrax timer 0. In order to get
	 * better precision, we check the current value. It might have
	 * underflowed already though.
	 */
	count = *R_TIMER0_DATA;

	/* Convert timer value to nsec */
	return (TIMER0_DIV - count) * (NSEC_PER_SEC/HZ)/TIMER0_DIV;
}

/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
 *
 * 3.10.4 Watchdog timer

 * When the watchdog timer is started, it generates an NMI if the watchdog
 * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
 * stopped after an additional 3.3 ms, the watchdog resets the chip.
 * The watchdog timer is stopped after reset. The watchdog timer is controlled
 * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
 * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
 * described in the table below:
 *
 *   Watchdog    Value written:
 *   state:      To enable:  To key:      Operation:
 *   --------    ----------  -------      ----------
 *   stopped         0         X          No effect.
 *   stopped         1       key_val      Start watchdog with key = key_val.
 *   started         0       ~key         Stop watchdog
 *   started         1       ~key         Restart watchdog with key = ~key.
 *   started         X       new_key_val  Change key to new_key_val.
 *
 * Note: '~' is the bitwise NOT operator.
 *
 */

/* right now, starting the watchdog is the same as resetting it */
#define start_watchdog reset_watchdog

#ifdef CONFIG_ETRAX_WATCHDOG
static int watchdog_key = 0;  /* arbitrary number */
#endif

/* number of pages to consider "out of memory". it is normal that the memory
 * is used though, so put this really low.
 */

#define WATCHDOG_MIN_FREE_PAGES 8

void reset_watchdog(void)
{
#if defined(CONFIG_ETRAX_WATCHDOG)
	/* only keep watchdog happy as long as we have memory left! */
	if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
		/* reset the watchdog with the inverse of the old key */
		watchdog_key ^= 0x7; /* invert key, which is 3 bits */
		*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
			IO_STATE(R_WATCHDOG, enable, start);
	}
#endif
}

/* stop the watchdog - we still need the correct key */

void stop_watchdog(void)
{
#ifdef CONFIG_ETRAX_WATCHDOG
	watchdog_key ^= 0x7; /* invert key, which is 3 bits */
	*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
		IO_STATE(R_WATCHDOG, enable, stop);
#endif
}


extern void cris_do_profile(struct pt_regs *regs);

/*
 * timer_interrupt() needs to keep up the real-time clock,
 * as well as call the "xtime_update()" routine every clocktick
 */
static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
{
	struct pt_regs *regs = get_irq_regs();
	/* acknowledge the timer irq */

#ifdef USE_CASCADE_TIMERS
	*R_TIMER_CTRL =
		IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
		IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
		IO_STATE( R_TIMER_CTRL, i1, clr) |
		IO_STATE( R_TIMER_CTRL, tm1, run) |
		IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
		IO_STATE( R_TIMER_CTRL, i0, clr) |
		IO_STATE( R_TIMER_CTRL, tm0, run) |
		IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
#else
	*R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr);
#endif

	/* reset watchdog otherwise it resets us! */
	reset_watchdog();

	/* Update statistics. */
	update_process_times(user_mode(regs));

	/* call the real timer interrupt handler */
	xtime_update(1);

        cris_do_profile(regs); /* Save profiling information */
        return IRQ_HANDLED;
}

/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain */

static struct irqaction irq2  = {
	.handler = timer_interrupt,
	.flags = IRQF_SHARED,
	.name = "timer",
};

void __init time_init(void)
{
	arch_gettimeoffset = cris_v10_gettimeoffset;

	/* probe for the RTC and read it if it exists
	 * Before the RTC can be probed the loops_per_usec variable needs
	 * to be initialized to make usleep work. A better value for
	 * loops_per_usec is calculated by the kernel later once the
	 * clock has started.
	 */
	loops_per_usec = 50;

	/* Setup the etrax timers
	 * Base frequency is 25000 hz, divider 250 -> 100 HZ
	 * In normal mode, we use timer0, so timer1 is free. In cascade
	 * mode (which we sometimes use for debugging) both timers are used.
	 * Remember that linux/timex.h contains #defines that rely on the
	 * timer settings below (hz and divide factor) !!!
	 */

#ifdef USE_CASCADE_TIMERS
	*R_TIMER_CTRL =
		IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
		IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
		IO_STATE( R_TIMER_CTRL, i1, nop) |
		IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
		IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
		IO_STATE( R_TIMER_CTRL, i0, nop) |
		IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
		IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);

	*R_TIMER_CTRL = r_timer_ctrl_shadow =
		IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
		IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
		IO_STATE( R_TIMER_CTRL, i1, nop) |
		IO_STATE( R_TIMER_CTRL, tm1, run) |
		IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
		IO_STATE( R_TIMER_CTRL, i0, nop) |
		IO_STATE( R_TIMER_CTRL, tm0, run) |
		IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
#else
	*R_TIMER_CTRL =
		IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
		IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
		IO_STATE(R_TIMER_CTRL, i1,        nop)      |
		IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
		IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
		IO_STATE(R_TIMER_CTRL, i0,        nop)      |
		IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
		IO_STATE(R_TIMER_CTRL, clksel0,   flexible);

	*R_TIMER_CTRL = r_timer_ctrl_shadow =
		IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
		IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
		IO_STATE(R_TIMER_CTRL, i1,        nop)      |
		IO_STATE(R_TIMER_CTRL, tm1,       run)      |
		IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
		IO_STATE(R_TIMER_CTRL, i0,        nop)      |
		IO_STATE(R_TIMER_CTRL, tm0,       run)      |
		IO_STATE(R_TIMER_CTRL, clksel0,   flexible);

	*R_TIMER_PRESCALE = PRESCALE_VALUE;
#endif

	/* unmask the timer irq */
	*R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set);

	/* now actually register the irq handler that calls timer_interrupt() */
	setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */

	/* enable watchdog if we should use one */
#if defined(CONFIG_ETRAX_WATCHDOG)
	printk("Enabling watchdog...\n");
	start_watchdog();

	/* If we use the hardware watchdog, we want to trap it as an NMI
	   and dump registers before it resets us.  For this to happen, we
	   must set the "m" NMI enable flag (which once set, is unset only
	   when an NMI is taken).

	   The same goes for the external NMI, but that doesn't have any
	   driver or infrastructure support yet.  */
	asm ("setf m");

	*R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
	*R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set);
#endif
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
3244c77b	2	/*
1da177e4 LT	3	* linux/arch/cris/arch-v10/kernel/time.c
	4	*
	5	* Copyright (C) 1991, 1992, 1995 Linus Torvalds
	6	* Copyright (C) 1999-2002 Axis Communications AB
	7	*
	8	*/
	9
1da177e4 LT	10	#include <linux/timex.h>
	11	#include <linux/time.h>
	12	#include <linux/jiffies.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/swap.h>
	15	#include <linux/sched.h>
	16	#include <linux/init.h>
a1056873	17	#include <linux/mm.h>
1da177e4 LT	18	#include <asm/types.h>
	19	#include <asm/signal.h>
	20	#include <asm/io.h>
	21	#include <asm/delay.h>
3244c77b	22	#include <asm/irq_regs.h>
1da177e4 LT	23
	24	/* define this if you need to use print_timestamp */
	25	/* it will make jiffies at 96 hz instead of 100 hz though */
	26	#undef USE_CASCADE_TIMERS
	27
1da177e4 LT	28	unsigned long get_ns_in_jiffie(void)
	29	{
	30	unsigned char timer_count, t1;
	31	unsigned short presc_count;
	32	unsigned long ns;
	33	unsigned long flags;
	34
	35	local_irq_save(flags);
1da177e4	36	timer_count = *R_TIMER0_DATA;
e269a869	37	presc_count = *R_TIM_PRESC_STATUS;
1da177e4 LT	38	/* presc_count might be wrapped */
	39	t1 = *R_TIMER0_DATA;
	40
	41	if (timer_count != t1){
	42	/* it wrapped, read prescaler again... */
	43	presc_count = *R_TIM_PRESC_STATUS;
	44	timer_count = t1;
	45	}
	46	local_irq_restore(flags);
	47	if (presc_count >= PRESCALE_VALUE/2 ){
	48	presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
	49	} else {
	50	presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
	51	}
	52
e269a869	53	ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
1da177e4 LT	54	( (presc_count) * (1000000000/PRESCALE_FREQ));
	55	return ns;
	56	}
	57
7b1f6207	58	static u32 cris_v10_gettimeoffset(void)
1da177e4	59	{
7b1f6207	60	u32 count;
1da177e4 LT	61
	62	/* The timer interrupt comes from Etrax timer 0. In order to get
	63	* better precision, we check the current value. It might have
	64	* underflowed already though.
	65	*/
1da177e4	66	count = *R_TIMER0_DATA;
1da177e4	67
547046f2 SW	68	/* Convert timer value to nsec */
547046f2 SW	69	return (TIMER0_DIV - count) * (NSEC_PER_SEC/HZ)/TIMER0_DIV;
1da177e4 LT	70	}
	71
	72	/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
	73	*
	74	* 3.10.4 Watchdog timer
	75
	76	* When the watchdog timer is started, it generates an NMI if the watchdog
	77	* isn't restarted or stopped within 0.1 s. If it still isn't restarted or
	78	* stopped after an additional 3.3 ms, the watchdog resets the chip.
	79	* The watchdog timer is stopped after reset. The watchdog timer is controlled
	80	* by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
	81	* and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
	82	* described in the table below:
e269a869	83	*
1da177e4 LT	84	* Watchdog Value written:
	85	* state: To enable: To key: Operation:
	86	* -------- ---------- ------- ----------
	87	* stopped 0 X No effect.
	88	* stopped 1 key_val Start watchdog with key = key_val.
	89	* started 0 ~key Stop watchdog
	90	* started 1 ~key Restart watchdog with key = ~key.
	91	* started X new_key_val Change key to new_key_val.
e269a869	92	*
1da177e4	93	* Note: '~' is the bitwise NOT operator.
e269a869	94	*
1da177e4 LT	95	*/
	96
	97	/* right now, starting the watchdog is the same as resetting it */
	98	#define start_watchdog reset_watchdog
	99
e269a869	100	#ifdef CONFIG_ETRAX_WATCHDOG
1da177e4 LT	101	static int watchdog_key = 0; /* arbitrary number */
	102	#endif
	103
	104	/* number of pages to consider "out of memory". it is normal that the memory
	105	* is used though, so put this really low.
	106	*/
	107
	108	#define WATCHDOG_MIN_FREE_PAGES 8
	109
e269a869	110	void reset_watchdog(void)
1da177e4	111	{
e269a869	112	#if defined(CONFIG_ETRAX_WATCHDOG)
1da177e4 LT	113	/* only keep watchdog happy as long as we have memory left! */
	114	if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
	115	/* reset the watchdog with the inverse of the old key */
	116	watchdog_key ^= 0x7; /* invert key, which is 3 bits */
	117	*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) \|
	118	IO_STATE(R_WATCHDOG, enable, start);
	119	}
	120	#endif
	121	}
	122
	123	/* stop the watchdog - we still need the correct key */
	124
e269a869	125	void stop_watchdog(void)
1da177e4	126	{
e269a869	127	#ifdef CONFIG_ETRAX_WATCHDOG
1da177e4 LT	128	watchdog_key ^= 0x7; /* invert key, which is 3 bits */
	129	*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) \|
	130	IO_STATE(R_WATCHDOG, enable, stop);
e269a869	131	#endif
1da177e4 LT	132	}
1da177e4 LT	133
1da177e4	134
e269a869 JN	135	extern void cris_do_profile(struct pt_regs *regs);
e269a869 JN	136
1da177e4 LT	137	/*
1da177e4 LT	138	* timer_interrupt() needs to keep up the real-time clock,
17588b99	139	* as well as call the "xtime_update()" routine every clocktick
1da177e4	140	*/
e269a869	141	static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
1da177e4	142	{
3244c77b	143	struct pt_regs *regs = get_irq_regs();
1da177e4 LT	144	/* acknowledge the timer irq */
	145
	146	#ifdef USE_CASCADE_TIMERS
	147	*R_TIMER_CTRL =
	148	IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) \|
	149	IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) \|
	150	IO_STATE( R_TIMER_CTRL, i1, clr) \|
	151	IO_STATE( R_TIMER_CTRL, tm1, run) \|
	152	IO_STATE( R_TIMER_CTRL, clksel1, cascade0) \|
	153	IO_STATE( R_TIMER_CTRL, i0, clr) \|
	154	IO_STATE( R_TIMER_CTRL, tm0, run) \|
	155	IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
	156	#else
e269a869	157	*R_TIMER_CTRL = r_timer_ctrl_shadow \| IO_STATE(R_TIMER_CTRL, i0, clr);
1da177e4 LT	158	#endif
	159
	160	/* reset watchdog otherwise it resets us! */
1da177e4	161	reset_watchdog();
e269a869	162
3244c77b JN	163	/* Update statistics. */
	164	update_process_times(user_mode(regs));
	165
1da177e4	166	/* call the real timer interrupt handler */
17588b99	167	xtime_update(1);
e269a869	168
1da177e4	169	cris_do_profile(regs); /* Save profiling information */
1da177e4 LT	170	return IRQ_HANDLED;
	171	}
	172
64d8ad93	173	/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain */
1da177e4	174
e5f71781 TG	175	static struct irqaction irq2 = {
e5f71781 TG	176	.handler = timer_interrupt,
64d8ad93	177	.flags = IRQF_SHARED,
e5f71781 TG	178	.name = "timer",
e5f71781 TG	179	};
1da177e4	180
e269a869 JN	181	void __init time_init(void)
e269a869 JN	182	{
7b1f6207 SW	183	arch_gettimeoffset = cris_v10_gettimeoffset;
7b1f6207 SW	184
e269a869 JN	185	/* probe for the RTC and read it if it exists
	186	* Before the RTC can be probed the loops_per_usec variable needs
	187	* to be initialized to make usleep work. A better value for
	188	* loops_per_usec is calculated by the kernel later once the
	189	* clock has started.
1da177e4 LT	190	*/
	191	loops_per_usec = 50;
	192
1da177e4 LT	193	/* Setup the etrax timers
	194	* Base frequency is 25000 hz, divider 250 -> 100 HZ
	195	* In normal mode, we use timer0, so timer1 is free. In cascade
	196	* mode (which we sometimes use for debugging) both timers are used.
	197	* Remember that linux/timex.h contains #defines that rely on the
	198	* timer settings below (hz and divide factor) !!!
	199	*/
e269a869	200
1da177e4 LT	201	#ifdef USE_CASCADE_TIMERS
	202	*R_TIMER_CTRL =
	203	IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) \|
	204	IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) \|
	205	IO_STATE( R_TIMER_CTRL, i1, nop) \|
	206	IO_STATE( R_TIMER_CTRL, tm1, stop_ld) \|
	207	IO_STATE( R_TIMER_CTRL, clksel1, cascade0) \|
	208	IO_STATE( R_TIMER_CTRL, i0, nop) \|
	209	IO_STATE( R_TIMER_CTRL, tm0, stop_ld) \|
	210	IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
e269a869 JN	211
e269a869 JN	212	*R_TIMER_CTRL = r_timer_ctrl_shadow =
1da177e4 LT	213	IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) \|
	214	IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) \|
	215	IO_STATE( R_TIMER_CTRL, i1, nop) \|
	216	IO_STATE( R_TIMER_CTRL, tm1, run) \|
	217	IO_STATE( R_TIMER_CTRL, clksel1, cascade0) \|
	218	IO_STATE( R_TIMER_CTRL, i0, nop) \|
	219	IO_STATE( R_TIMER_CTRL, tm0, run) \|
	220	IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
	221	#else
e269a869 JN	222	*R_TIMER_CTRL =
e269a869 JN	223	IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) \|
1da177e4	224	IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) \|
e269a869	225	IO_STATE(R_TIMER_CTRL, i1, nop) \|
1da177e4 LT	226	IO_STATE(R_TIMER_CTRL, tm1, stop_ld) \|
	227	IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) \|
	228	IO_STATE(R_TIMER_CTRL, i0, nop) \|
	229	IO_STATE(R_TIMER_CTRL, tm0, stop_ld) \|
	230	IO_STATE(R_TIMER_CTRL, clksel0, flexible);
e269a869	231
1da177e4	232	*R_TIMER_CTRL = r_timer_ctrl_shadow =
e269a869	233	IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) \|
1da177e4 LT	234	IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) \|
	235	IO_STATE(R_TIMER_CTRL, i1, nop) \|
	236	IO_STATE(R_TIMER_CTRL, tm1, run) \|
	237	IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) \|
	238	IO_STATE(R_TIMER_CTRL, i0, nop) \|
	239	IO_STATE(R_TIMER_CTRL, tm0, run) \|
	240	IO_STATE(R_TIMER_CTRL, clksel0, flexible);
	241
	242	*R_TIMER_PRESCALE = PRESCALE_VALUE;
	243	#endif
	244
e269a869 JN	245	/* unmask the timer irq */
	246	*R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set);
	247
	248	/* now actually register the irq handler that calls timer_interrupt() */
1da177e4 LT	249	setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
	250
	251	/* enable watchdog if we should use one */
e269a869	252	#if defined(CONFIG_ETRAX_WATCHDOG)
1da177e4 LT	253	printk("Enabling watchdog...\n");
	254	start_watchdog();
	255
	256	/* If we use the hardware watchdog, we want to trap it as an NMI
	257	and dump registers before it resets us. For this to happen, we
	258	must set the "m" NMI enable flag (which once set, is unset only
	259	when an NMI is taken).
	260
	261	The same goes for the external NMI, but that doesn't have any
	262	driver or infrastructure support yet. */
	263	asm ("setf m");
	264
e269a869 JN	265	*R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
e269a869 JN	266	*R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set);
1da177e4 LT	267	#endif
1da177e4 LT	268	}