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9df10281 | 1 | /* |
96f1050d | 2 | * Instruction SRAM accessor functions for the Blackfin |
9df10281 RG |
3 | * |
4 | * Copyright 2008 Analog Devices Inc. | |
5 | * | |
96f1050d | 6 | * Licensed under the GPL-2 or later |
9df10281 RG |
7 | */ |
8 | ||
c40cdb2c MF |
9 | #define pr_fmt(fmt) "isram: " fmt |
10 | ||
9df10281 RG |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/sched.h> | |
16 | ||
17 | #include <asm/blackfin.h> | |
c40cdb2c | 18 | #include <asm/dma.h> |
9df10281 RG |
19 | |
20 | /* | |
21 | * IMPORTANT WARNING ABOUT THESE FUNCTIONS | |
22 | * | |
23 | * The emulator will not function correctly if a write command is left in | |
24 | * ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by | |
25 | * the emulator. To avoid such problems, ensure that both ITEST_COMMAND | |
26 | * and DTEST_COMMAND are zero when exiting these functions. | |
27 | */ | |
28 | ||
29 | ||
30 | /* | |
31 | * On the Blackfin, L1 instruction sram (which operates at core speeds) can not | |
32 | * be accessed by a normal core load, so we need to go through a few hoops to | |
33 | * read/write it. | |
34 | * To try to make it easier - we export a memcpy interface, where either src or | |
35 | * dest can be in this special L1 memory area. | |
36 | * The low level read/write functions should not be exposed to the rest of the | |
37 | * kernel, since they operate on 64-bit data, and need specific address alignment | |
38 | */ | |
39 | ||
40 | static DEFINE_SPINLOCK(dtest_lock); | |
41 | ||
42 | /* Takes a void pointer */ | |
43 | #define IADDR2DTEST(x) \ | |
44 | ({ unsigned long __addr = (unsigned long)(x); \ | |
45 | (__addr & 0x47F8) | /* address bits 14 & 10:3 */ \ | |
774b8022 | 46 | (__addr & 0x8000) << 23 | /* Bank A/B */ \ |
9df10281 | 47 | (__addr & 0x0800) << 15 | /* address bit 11 */ \ |
774b8022 RG |
48 | (__addr & 0x3000) << 4 | /* address bits 13:12 */ \ |
49 | (__addr & 0x8000) << 8 | /* address bit 15 */ \ | |
50 | (0x1000000) | /* instruction access = 1 */ \ | |
51 | (0x4); /* data array = 1 */ \ | |
9df10281 RG |
52 | }) |
53 | ||
54 | /* Takes a pointer, and returns the offset (in bits) which things should be shifted */ | |
55 | #define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8) | |
56 | ||
57 | /* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */ | |
58 | #define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7) | |
59 | ||
60 | static void isram_write(const void *addr, uint64_t data) | |
61 | { | |
62 | uint32_t cmd; | |
63 | unsigned long flags; | |
64 | ||
65 | if (addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH)) | |
66 | return; | |
67 | ||
774b8022 | 68 | cmd = IADDR2DTEST(addr) | 2; /* write */ |
9df10281 RG |
69 | |
70 | /* | |
71 | * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND | |
72 | * While in exception context - atomicity is guaranteed or double fault | |
73 | */ | |
74 | spin_lock_irqsave(&dtest_lock, flags); | |
75 | ||
76 | bfin_write_DTEST_DATA0(data & 0xFFFFFFFF); | |
77 | bfin_write_DTEST_DATA1(data >> 32); | |
78 | ||
79 | /* use the builtin, since interrupts are already turned off */ | |
80 | __builtin_bfin_csync(); | |
81 | bfin_write_DTEST_COMMAND(cmd); | |
82 | __builtin_bfin_csync(); | |
83 | ||
84 | bfin_write_DTEST_COMMAND(0); | |
85 | __builtin_bfin_csync(); | |
86 | ||
87 | spin_unlock_irqrestore(&dtest_lock, flags); | |
88 | } | |
89 | ||
90 | static uint64_t isram_read(const void *addr) | |
91 | { | |
92 | uint32_t cmd; | |
93 | unsigned long flags; | |
94 | uint64_t ret; | |
95 | ||
96 | if (addr > (void *)(L1_CODE_START + L1_CODE_LENGTH)) | |
97 | return 0; | |
98 | ||
99 | cmd = IADDR2DTEST(addr) | 0; /* read */ | |
100 | ||
101 | /* | |
102 | * Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND | |
103 | * While in exception context - atomicity is guaranteed or double fault | |
104 | */ | |
105 | spin_lock_irqsave(&dtest_lock, flags); | |
106 | /* use the builtin, since interrupts are already turned off */ | |
107 | __builtin_bfin_csync(); | |
108 | bfin_write_DTEST_COMMAND(cmd); | |
109 | __builtin_bfin_csync(); | |
110 | ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32); | |
111 | ||
112 | bfin_write_DTEST_COMMAND(0); | |
113 | __builtin_bfin_csync(); | |
114 | spin_unlock_irqrestore(&dtest_lock, flags); | |
115 | ||
116 | return ret; | |
117 | } | |
118 | ||
119 | static bool isram_check_addr(const void *addr, size_t n) | |
120 | { | |
121 | if ((addr >= (void *)L1_CODE_START) && | |
122 | (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) { | |
4b402e3a | 123 | if ((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH)) { |
9df10281 | 124 | show_stack(NULL, NULL); |
c40cdb2c | 125 | pr_err("copy involving %p length (%zu) too long\n", addr, n); |
9df10281 RG |
126 | } |
127 | return true; | |
128 | } | |
129 | return false; | |
130 | } | |
131 | ||
132 | /* | |
133 | * The isram_memcpy() function copies n bytes from memory area src to memory area dest. | |
134 | * The isram_memcpy() function returns a pointer to dest. | |
135 | * Either dest or src can be in L1 instruction sram. | |
136 | */ | |
137 | void *isram_memcpy(void *dest, const void *src, size_t n) | |
138 | { | |
139 | uint64_t data_in = 0, data_out = 0; | |
140 | size_t count; | |
141 | bool dest_in_l1, src_in_l1, need_data, put_data; | |
142 | unsigned char byte, *src_byte, *dest_byte; | |
143 | ||
144 | src_byte = (unsigned char *)src; | |
145 | dest_byte = (unsigned char *)dest; | |
146 | ||
147 | dest_in_l1 = isram_check_addr(dest, n); | |
148 | src_in_l1 = isram_check_addr(src, n); | |
149 | ||
150 | need_data = true; | |
151 | put_data = true; | |
152 | for (count = 0; count < n; count++) { | |
153 | if (src_in_l1) { | |
154 | if (need_data) { | |
155 | data_in = isram_read(src + count); | |
156 | need_data = false; | |
157 | } | |
158 | ||
159 | if (ADDR2LAST(src + count)) | |
160 | need_data = true; | |
161 | ||
162 | byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff); | |
163 | ||
164 | } else { | |
165 | /* src is in L2 or L3 - so just dereference*/ | |
166 | byte = src_byte[count]; | |
167 | } | |
168 | ||
169 | if (dest_in_l1) { | |
170 | if (put_data) { | |
171 | data_out = isram_read(dest + count); | |
172 | put_data = false; | |
173 | } | |
174 | ||
175 | data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count)); | |
176 | data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count)); | |
177 | ||
178 | if (ADDR2LAST(dest + count)) { | |
179 | put_data = true; | |
180 | isram_write(dest + count, data_out); | |
181 | } | |
182 | } else { | |
183 | /* dest in L2 or L3 - so just dereference */ | |
184 | dest_byte[count] = byte; | |
185 | } | |
186 | } | |
187 | ||
188 | /* make sure we dump the last byte if necessary */ | |
189 | if (dest_in_l1 && !put_data) | |
190 | isram_write(dest + count, data_out); | |
191 | ||
192 | return dest; | |
193 | } | |
194 | EXPORT_SYMBOL(isram_memcpy); | |
195 | ||
c40cdb2c MF |
196 | #ifdef CONFIG_BFIN_ISRAM_SELF_TEST |
197 | ||
198 | #define TEST_LEN 0x100 | |
199 | ||
200 | static __init void hex_dump(unsigned char *buf, int len) | |
201 | { | |
202 | while (len--) | |
203 | pr_cont("%02x", *buf++); | |
204 | } | |
205 | ||
206 | static __init int isram_read_test(char *sdram, void *l1inst) | |
207 | { | |
208 | int i, ret = 0; | |
209 | uint64_t data1, data2; | |
210 | ||
211 | pr_info("INFO: running isram_read tests\n"); | |
212 | ||
213 | /* setup some different data to play with */ | |
214 | for (i = 0; i < TEST_LEN; ++i) | |
215 | sdram[i] = i; | |
216 | dma_memcpy(l1inst, sdram, TEST_LEN); | |
217 | ||
218 | /* make sure we can read the L1 inst */ | |
219 | for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) { | |
220 | data1 = isram_read(l1inst + i); | |
221 | memcpy(&data2, sdram + i, sizeof(data2)); | |
222 | if (memcmp(&data1, &data2, sizeof(uint64_t))) { | |
223 | pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n", | |
224 | l1inst + i, data1, data2); | |
225 | ++ret; | |
226 | } | |
227 | } | |
228 | ||
229 | return ret; | |
230 | } | |
231 | ||
232 | static __init int isram_write_test(char *sdram, void *l1inst) | |
233 | { | |
234 | int i, ret = 0; | |
235 | uint64_t data1, data2; | |
236 | ||
237 | pr_info("INFO: running isram_write tests\n"); | |
238 | ||
239 | /* setup some different data to play with */ | |
240 | memset(sdram, 0, TEST_LEN * 2); | |
241 | dma_memcpy(l1inst, sdram, TEST_LEN); | |
242 | for (i = 0; i < TEST_LEN; ++i) | |
243 | sdram[i] = i; | |
244 | ||
245 | /* make sure we can write the L1 inst */ | |
246 | for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) { | |
247 | memcpy(&data1, sdram + i, sizeof(data1)); | |
248 | isram_write(l1inst + i, data1); | |
249 | data2 = isram_read(l1inst + i); | |
250 | if (memcmp(&data1, &data2, sizeof(uint64_t))) { | |
251 | pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n", | |
252 | l1inst + i, data1, data2); | |
253 | ++ret; | |
254 | } | |
255 | } | |
256 | ||
257 | dma_memcpy(sdram + TEST_LEN, l1inst, TEST_LEN); | |
258 | if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) { | |
259 | pr_err("FAIL: isram_write() did not work properly\n"); | |
260 | ++ret; | |
261 | } | |
262 | ||
263 | return ret; | |
264 | } | |
265 | ||
266 | static __init int | |
267 | _isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy, | |
268 | void *(*fmemcpy)(void *, const void *, size_t)) | |
269 | { | |
270 | memset(sdram, pattern, TEST_LEN); | |
271 | fmemcpy(l1inst, sdram, TEST_LEN); | |
272 | fmemcpy(sdram + TEST_LEN, l1inst, TEST_LEN); | |
273 | if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) { | |
274 | pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n", | |
275 | smemcpy, l1inst, sdram, TEST_LEN, pattern); | |
276 | return 1; | |
277 | } | |
278 | return 0; | |
279 | } | |
280 | #define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d) | |
281 | ||
282 | static __init int isram_memcpy_test(char *sdram, void *l1inst) | |
283 | { | |
284 | int i, j, thisret, ret = 0; | |
285 | ||
286 | /* check broad isram_memcpy() */ | |
287 | pr_info("INFO: running broad isram_memcpy tests\n"); | |
288 | for (i = 0xf; i >= 0; --i) | |
289 | ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy); | |
290 | ||
291 | /* check read of small, unaligned, and hardware 64bit limits */ | |
292 | pr_info("INFO: running isram_memcpy (read) tests\n"); | |
293 | ||
294 | for (i = 0; i < TEST_LEN; ++i) | |
295 | sdram[i] = i; | |
296 | dma_memcpy(l1inst, sdram, TEST_LEN); | |
297 | ||
298 | thisret = 0; | |
299 | for (i = 0; i < TEST_LEN - 32; ++i) { | |
300 | unsigned char cmp[32]; | |
301 | for (j = 1; j <= 32; ++j) { | |
302 | memset(cmp, 0, sizeof(cmp)); | |
303 | isram_memcpy(cmp, l1inst + i, j); | |
304 | if (memcmp(cmp, sdram + i, j)) { | |
305 | pr_err("FAIL: %p:", l1inst + 1); | |
306 | hex_dump(cmp, j); | |
307 | pr_cont(" SDRAM:"); | |
308 | hex_dump(sdram + i, j); | |
309 | pr_cont("\n"); | |
310 | if (++thisret > 20) { | |
311 | pr_err("FAIL: skipping remaining series\n"); | |
312 | i = TEST_LEN; | |
313 | break; | |
314 | } | |
315 | } | |
316 | } | |
317 | } | |
318 | ret += thisret; | |
319 | ||
320 | /* check write of small, unaligned, and hardware 64bit limits */ | |
321 | pr_info("INFO: running isram_memcpy (write) tests\n"); | |
322 | ||
323 | memset(sdram + TEST_LEN, 0, TEST_LEN); | |
324 | dma_memcpy(l1inst, sdram + TEST_LEN, TEST_LEN); | |
325 | ||
326 | thisret = 0; | |
327 | for (i = 0; i < TEST_LEN - 32; ++i) { | |
328 | unsigned char cmp[32]; | |
329 | for (j = 1; j <= 32; ++j) { | |
330 | isram_memcpy(l1inst + i, sdram + i, j); | |
331 | dma_memcpy(cmp, l1inst + i, j); | |
332 | if (memcmp(cmp, sdram + i, j)) { | |
333 | pr_err("FAIL: %p:", l1inst + i); | |
334 | hex_dump(cmp, j); | |
335 | pr_cont(" SDRAM:"); | |
336 | hex_dump(sdram + i, j); | |
337 | pr_cont("\n"); | |
338 | if (++thisret > 20) { | |
339 | pr_err("FAIL: skipping remaining series\n"); | |
340 | i = TEST_LEN; | |
341 | break; | |
342 | } | |
343 | } | |
344 | } | |
345 | } | |
346 | ret += thisret; | |
347 | ||
348 | return ret; | |
349 | } | |
350 | ||
351 | static __init int isram_test_init(void) | |
352 | { | |
353 | int ret; | |
354 | char *sdram; | |
355 | void *l1inst; | |
356 | ||
357 | sdram = kmalloc(TEST_LEN * 2, GFP_KERNEL); | |
358 | if (!sdram) { | |
359 | pr_warning("SKIP: could not allocate sdram\n"); | |
360 | return 0; | |
361 | } | |
362 | ||
363 | l1inst = l1_inst_sram_alloc(TEST_LEN); | |
364 | if (!l1inst) { | |
365 | kfree(sdram); | |
366 | pr_warning("SKIP: could not allocate L1 inst\n"); | |
367 | return 0; | |
368 | } | |
369 | ||
370 | /* sanity check initial L1 inst state */ | |
371 | ret = 1; | |
372 | pr_info("INFO: running initial dma_memcpy checks\n"); | |
373 | if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy)) | |
374 | goto abort; | |
375 | if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy)) | |
376 | goto abort; | |
377 | ||
378 | ret = 0; | |
379 | ret += isram_read_test(sdram, l1inst); | |
380 | ret += isram_write_test(sdram, l1inst); | |
381 | ret += isram_memcpy_test(sdram, l1inst); | |
382 | ||
383 | abort: | |
384 | sram_free(l1inst); | |
385 | kfree(sdram); | |
386 | ||
387 | if (ret) | |
388 | return -EIO; | |
389 | ||
390 | pr_info("PASS: all tests worked !\n"); | |
391 | return 0; | |
392 | } | |
393 | late_initcall(isram_test_init); | |
394 | ||
395 | static __exit void isram_test_exit(void) | |
396 | { | |
397 | /* stub to allow unloading */ | |
398 | } | |
399 | module_exit(isram_test_exit); | |
400 | ||
401 | #endif |