[linux-block.git] / arch / blackfin / mach-common / smp.c

/*
 * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
 *
 * Copyright 2007-2009 Analog Devices Inc.
 *                         Philippe Gerum <rpm@xenomai.org>
 *
 * Licensed under the GPL-2.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/sched/task_stack.h>
#include <linux/interrupt.h>
#include <linux/cache.h>
#include <linux/clockchips.h>
#include <linux/profile.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/cpu.h>
#include <linux/smp.h>
#include <linux/cpumask.h>
#include <linux/seq_file.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/atomic.h>
#include <asm/cacheflush.h>
#include <asm/irq_handler.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/cpu.h>
#include <asm/time.h>
#include <linux/err.h>

/*
 * Anomaly notes:
 * 05000120 - we always define corelock as 32-bit integer in L2
 */
struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));

#ifdef CONFIG_ICACHE_FLUSH_L1
unsigned long blackfin_iflush_l1_entry[NR_CPUS];
#endif

struct blackfin_initial_pda initial_pda_coreb;

enum ipi_message_type {
	BFIN_IPI_NONE,
	BFIN_IPI_TIMER,
	BFIN_IPI_RESCHEDULE,
	BFIN_IPI_CALL_FUNC,
	BFIN_IPI_CPU_STOP,
};

struct blackfin_flush_data {
	unsigned long start;
	unsigned long end;
};

void *secondary_stack;

static struct blackfin_flush_data smp_flush_data;

static DEFINE_SPINLOCK(stop_lock);

/* A magic number - stress test shows this is safe for common cases */
#define BFIN_IPI_MSGQ_LEN 5

/* Simple FIFO buffer, overflow leads to panic */
struct ipi_data {
	atomic_t count;
	atomic_t bits;
};

static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);

static void ipi_cpu_stop(unsigned int cpu)
{
	spin_lock(&stop_lock);
	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	dump_stack();
	spin_unlock(&stop_lock);

	set_cpu_online(cpu, false);

	local_irq_disable();

	while (1)
		SSYNC();
}

static void ipi_flush_icache(void *info)
{
	struct blackfin_flush_data *fdata = info;

	/* Invalidate the memory holding the bounds of the flushed region. */
	blackfin_dcache_invalidate_range((unsigned long)fdata,
					 (unsigned long)fdata + sizeof(*fdata));

	/* Make sure all write buffers in the data side of the core
	 * are flushed before trying to invalidate the icache.  This
	 * needs to be after the data flush and before the icache
	 * flush so that the SSYNC does the right thing in preventing
	 * the instruction prefetcher from hitting things in cached
	 * memory at the wrong time -- it runs much further ahead than
	 * the pipeline.
	 */
	SSYNC();

	/* ipi_flaush_icache is invoked by generic flush_icache_range,
	 * so call blackfin arch icache flush directly here.
	 */
	blackfin_icache_flush_range(fdata->start, fdata->end);
}

/* Use IRQ_SUPPLE_0 to request reschedule.
 * When returning from interrupt to user space,
 * there is chance to reschedule */
static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
{
	unsigned int cpu = smp_processor_id();

	platform_clear_ipi(cpu, IRQ_SUPPLE_0);
	return IRQ_HANDLED;
}

DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
void ipi_timer(void)
{
	int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
	evt->event_handler(evt);
}

static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
{
	struct ipi_data *bfin_ipi_data;
	unsigned int cpu = smp_processor_id();
	unsigned long pending;
	unsigned long msg;

	platform_clear_ipi(cpu, IRQ_SUPPLE_1);

	smp_rmb();
	bfin_ipi_data = this_cpu_ptr(&bfin_ipi);
	while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
		msg = 0;
		do {
			msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
			switch (msg) {
			case BFIN_IPI_TIMER:
				ipi_timer();
				break;
			case BFIN_IPI_RESCHEDULE:
				scheduler_ipi();
				break;
			case BFIN_IPI_CALL_FUNC:
				generic_smp_call_function_interrupt();
				break;
			case BFIN_IPI_CPU_STOP:
				ipi_cpu_stop(cpu);
				break;
			default:
				goto out;
			}
			atomic_dec(&bfin_ipi_data->count);
		} while (msg < BITS_PER_LONG);

	}
out:
	return IRQ_HANDLED;
}

static void bfin_ipi_init(void)
{
	unsigned int cpu;
	struct ipi_data *bfin_ipi_data;
	for_each_possible_cpu(cpu) {
		bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
		atomic_set(&bfin_ipi_data->bits, 0);
		atomic_set(&bfin_ipi_data->count, 0);
	}
}

void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
{
	unsigned int cpu;
	struct ipi_data *bfin_ipi_data;
	unsigned long flags;

	local_irq_save(flags);
	for_each_cpu(cpu, cpumask) {
		bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
		atomic_or((1 << msg), &bfin_ipi_data->bits);
		atomic_inc(&bfin_ipi_data->count);
	}
	local_irq_restore(flags);
	smp_wmb();
	for_each_cpu(cpu, cpumask)
		platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
}

void arch_send_call_function_single_ipi(int cpu)
{
	send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
}

void arch_send_call_function_ipi_mask(const struct cpumask *mask)
{
	send_ipi(mask, BFIN_IPI_CALL_FUNC);
}

void smp_send_reschedule(int cpu)
{
	send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);

	return;
}

void smp_send_msg(const struct cpumask *mask, unsigned long type)
{
	send_ipi(mask, type);
}

void smp_timer_broadcast(const struct cpumask *mask)
{
	smp_send_msg(mask, BFIN_IPI_TIMER);
}

void smp_send_stop(void)
{
	cpumask_t callmap;

	preempt_disable();
	cpumask_copy(&callmap, cpu_online_mask);
	cpumask_clear_cpu(smp_processor_id(), &callmap);
	if (!cpumask_empty(&callmap))
		send_ipi(&callmap, BFIN_IPI_CPU_STOP);

	preempt_enable();

	return;
}

int __cpu_up(unsigned int cpu, struct task_struct *idle)
{
	int ret;

	secondary_stack = task_stack_page(idle) + THREAD_SIZE;

	ret = platform_boot_secondary(cpu, idle);

	secondary_stack = NULL;

	return ret;
}

static void setup_secondary(unsigned int cpu)
{
	unsigned long ilat;

	bfin_write_IMASK(0);
	CSYNC();
	ilat = bfin_read_ILAT();
	CSYNC();
	bfin_write_ILAT(ilat);
	CSYNC();

	/* Enable interrupt levels IVG7-15. IARs have been already
	 * programmed by the boot CPU.  */
	bfin_irq_flags |= IMASK_IVG15 |
	    IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
	    IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
}

void secondary_start_kernel(void)
{
	unsigned int cpu = smp_processor_id();
	struct mm_struct *mm = &init_mm;

	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
		printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
#ifdef CONFIG_DEBUG_DOUBLEFAULT
		printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
			initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
			initial_pda_coreb.retx_doublefault);
		printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n",
			initial_pda_coreb.dcplb_doublefault_addr);
		printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n",
			initial_pda_coreb.icplb_doublefault_addr);
#endif
		printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
			initial_pda_coreb.retx);
	}

	/*
	 * We want the D-cache to be enabled early, in case the atomic
	 * support code emulates cache coherence (see
	 * __ARCH_SYNC_CORE_DCACHE).
	 */
	init_exception_vectors();

	local_irq_disable();

	/* Attach the new idle task to the global mm. */
	mmget(mm);
	mmgrab(mm);
	current->active_mm = mm;

	preempt_disable();

	setup_secondary(cpu);

	platform_secondary_init(cpu);
	/* setup local core timer */
	bfin_local_timer_setup();

	local_irq_enable();

	bfin_setup_caches(cpu);

	notify_cpu_starting(cpu);
	/*
	 * Calibrate loops per jiffy value.
	 * IRQs need to be enabled here - D-cache can be invalidated
	 * in timer irq handler, so core B can read correct jiffies.
	 */
	calibrate_delay();

	/* We are done with local CPU inits, unblock the boot CPU. */
	set_cpu_online(cpu, true);
	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
}

void __init smp_prepare_boot_cpu(void)
{
}

void __init smp_prepare_cpus(unsigned int max_cpus)
{
	platform_prepare_cpus(max_cpus);
	bfin_ipi_init();
	platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
	platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
}

void __init smp_cpus_done(unsigned int max_cpus)
{
	unsigned long bogosum = 0;
	unsigned int cpu;

	for_each_online_cpu(cpu)
		bogosum += loops_per_jiffy;

	printk(KERN_INFO "SMP: Total of %d processors activated "
	       "(%lu.%02lu BogoMIPS).\n",
	       num_online_cpus(),
	       bogosum / (500000/HZ),
	       (bogosum / (5000/HZ)) % 100);
}

void smp_icache_flush_range_others(unsigned long start, unsigned long end)
{
	smp_flush_data.start = start;
	smp_flush_data.end = end;

	preempt_disable();
	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
		printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
	preempt_enable();
}
EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);

#ifdef __ARCH_SYNC_CORE_ICACHE
unsigned long icache_invld_count[NR_CPUS];
void resync_core_icache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_icache();
	icache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_icache);
#endif

#ifdef __ARCH_SYNC_CORE_DCACHE
unsigned long dcache_invld_count[NR_CPUS];
unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));

void resync_core_dcache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_dcache();
	dcache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_dcache);
#endif

#ifdef CONFIG_HOTPLUG_CPU
int __cpu_disable(void)
{
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EPERM;

	set_cpu_online(cpu, false);
	return 0;
}

int __cpu_die(unsigned int cpu)
{
	return cpu_wait_death(cpu, 5);
}

void cpu_die(void)
{
	(void)cpu_report_death();

	atomic_dec(&init_mm.mm_users);
	atomic_dec(&init_mm.mm_count);

	local_irq_disable();
	platform_cpu_die();
}
#endif
Commit	Line	Data
6b3087c6	1	/*
96f1050d	2	* IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
6b3087c6	3	*
96f1050d RG	4	* Copyright 2007-2009 Analog Devices Inc.
96f1050d RG	5	* Philippe Gerum <rpm@xenomai.org>
6b3087c6	6	*
96f1050d	7	* Licensed under the GPL-2.
6b3087c6 GY	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/sched.h>
68db0cf1	15	#include <linux/sched/task_stack.h>
6b3087c6 GY	16	#include <linux/interrupt.h>
6b3087c6 GY	17	#include <linux/cache.h>
d0014be4	18	#include <linux/clockchips.h>
6b3087c6 GY	19	#include <linux/profile.h>
	20	#include <linux/errno.h>
	21	#include <linux/mm.h>
	22	#include <linux/cpu.h>
	23	#include <linux/smp.h>
9c199b59	24	#include <linux/cpumask.h>
6b3087c6 GY	25	#include <linux/seq_file.h>
6b3087c6 GY	26	#include <linux/irq.h>
5a0e3ad6	27	#include <linux/slab.h>
60063497	28	#include <linux/atomic.h>
6b3087c6	29	#include <asm/cacheflush.h>
6327a574	30	#include <asm/irq_handler.h>
6b3087c6 GY	31	#include <asm/mmu_context.h>
	32	#include <asm/pgtable.h>
	33	#include <asm/pgalloc.h>
	34	#include <asm/processor.h>
	35	#include <asm/ptrace.h>
	36	#include <asm/cpu.h>
1fa9be72	37	#include <asm/time.h>
6b3087c6 GY	38	#include <linux/err.h>
6b3087c6 GY	39
555487bb GY	40	/*
	41	* Anomaly notes:
	42	* 05000120 - we always define corelock as 32-bit integer in L2
	43	*/
6b3087c6 GY	44	struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
6b3087c6 GY	45
c6345ab1 SZ	46	#ifdef CONFIG_ICACHE_FLUSH_L1
	47	unsigned long blackfin_iflush_l1_entry[NR_CPUS];
	48	#endif
	49
13dff62d	50	struct blackfin_initial_pda initial_pda_coreb;
6b3087c6	51
50888469	52	enum ipi_message_type {
150382a5	53	BFIN_IPI_NONE,
50888469 SM	54	BFIN_IPI_TIMER,
	55	BFIN_IPI_RESCHEDULE,
	56	BFIN_IPI_CALL_FUNC,
50888469 SM	57	BFIN_IPI_CPU_STOP,
50888469 SM	58	};
6b3087c6 GY	59
	60	struct blackfin_flush_data {
	61	unsigned long start;
	62	unsigned long end;
	63	};
	64
	65	void *secondary_stack;
	66
6b3087c6 GY	67	static struct blackfin_flush_data smp_flush_data;
	68
	69	static DEFINE_SPINLOCK(stop_lock);
	70
73a40064 YL	71	/* A magic number - stress test shows this is safe for common cases */
	72	#define BFIN_IPI_MSGQ_LEN 5
	73
	74	/* Simple FIFO buffer, overflow leads to panic */
50888469	75	struct ipi_data {
150382a5 SM	76	atomic_t count;
150382a5 SM	77	atomic_t bits;
6b3087c6 GY	78	};
6b3087c6 GY	79
50888469	80	static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);
6b3087c6 GY	81
	82	static void ipi_cpu_stop(unsigned int cpu)
	83	{
	84	spin_lock(&stop_lock);
	85	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	86	dump_stack();
	87	spin_unlock(&stop_lock);
	88
fecedc80	89	set_cpu_online(cpu, false);
6b3087c6 GY	90
	91	local_irq_disable();
	92
	93	while (1)
	94	SSYNC();
	95	}
	96
	97	static void ipi_flush_icache(void *info)
	98	{
	99	struct blackfin_flush_data *fdata = info;
	100
	101	/* Invalidate the memory holding the bounds of the flushed region. */
8d50de9e SZ	102	blackfin_dcache_invalidate_range((unsigned long)fdata,
	103	(unsigned long)fdata + sizeof(*fdata));
	104
	105	/* Make sure all write buffers in the data side of the core
	106	* are flushed before trying to invalidate the icache. This
	107	* needs to be after the data flush and before the icache
	108	* flush so that the SSYNC does the right thing in preventing
	109	* the instruction prefetcher from hitting things in cached
	110	* memory at the wrong time -- it runs much further ahead than
	111	* the pipeline.
	112	*/
	113	SSYNC();
	114
	115	/* ipi_flaush_icache is invoked by generic flush_icache_range,
	116	* so call blackfin arch icache flush directly here.
	117	*/
	118	blackfin_icache_flush_range(fdata->start, fdata->end);
6b3087c6 GY	119	}
6b3087c6 GY	120
73a40064 YL	121	/* Use IRQ_SUPPLE_0 to request reschedule.
	122	* When returning from interrupt to user space,
	123	* there is chance to reschedule */
	124	static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
	125	{
	126	unsigned int cpu = smp_processor_id();
	127
	128	platform_clear_ipi(cpu, IRQ_SUPPLE_0);
	129	return IRQ_HANDLED;
	130	}
	131
d0014be4 BL	132	DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
	133	void ipi_timer(void)
	134	{
	135	int cpu = smp_processor_id();
	136	struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
	137	evt->event_handler(evt);
	138	}
	139
73a40064	140	static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
6b3087c6	141	{
50888469	142	struct ipi_data *bfin_ipi_data;
6b3087c6	143	unsigned int cpu = smp_processor_id();
50888469 SM	144	unsigned long pending;
50888469 SM	145	unsigned long msg;
6b3087c6	146
73a40064	147	platform_clear_ipi(cpu, IRQ_SUPPLE_1);
6b3087c6	148
177a48fd	149	smp_rmb();
7e788ab1	150	bfin_ipi_data = this_cpu_ptr(&bfin_ipi);
16fc5bc4	151	while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
50888469 SM	152	msg = 0;
	153	do {
	154	msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
	155	switch (msg) {
	156	case BFIN_IPI_TIMER:
	157	ipi_timer();
	158	break;
	159	case BFIN_IPI_RESCHEDULE:
	160	scheduler_ipi();
	161	break;
	162	case BFIN_IPI_CALL_FUNC:
	163	generic_smp_call_function_interrupt();
	164	break;
50888469 SM	165	case BFIN_IPI_CPU_STOP:
	166	ipi_cpu_stop(cpu);
	167	break;
177a48fd SM	168	default:
177a48fd SM	169	goto out;
50888469	170	}
150382a5	171	atomic_dec(&bfin_ipi_data->count);
50888469	172	} while (msg < BITS_PER_LONG);
177a48fd	173
6b3087c6	174	}
177a48fd	175	out:
6b3087c6 GY	176	return IRQ_HANDLED;
	177	}
	178
50888469	179	static void bfin_ipi_init(void)
6b3087c6 GY	180	{
6b3087c6 GY	181	unsigned int cpu;
50888469	182	struct ipi_data *bfin_ipi_data;
6b3087c6	183	for_each_possible_cpu(cpu) {
50888469	184	bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
16fc5bc4 SM	185	atomic_set(&bfin_ipi_data->bits, 0);
16fc5bc4 SM	186	atomic_set(&bfin_ipi_data->count, 0);
6b3087c6 GY	187	}
	188	}
	189
50888469	190	void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
6b3087c6 GY	191	{
6b3087c6 GY	192	unsigned int cpu;
50888469 SM	193	struct ipi_data *bfin_ipi_data;
	194	unsigned long flags;
	195
	196	local_irq_save(flags);
50888469 SM	197	for_each_cpu(cpu, cpumask) {
50888469 SM	198	bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
805de8f4	199	atomic_or((1 << msg), &bfin_ipi_data->bits);
150382a5	200	atomic_inc(&bfin_ipi_data->count);
6b3087c6	201	}
50888469	202	local_irq_restore(flags);
177a48fd SM	203	smp_wmb();
	204	for_each_cpu(cpu, cpumask)
	205	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
73a40064 YL	206	}
73a40064 YL	207
50888469	208	void arch_send_call_function_single_ipi(int cpu)
73a40064	209	{
5e98c099	210	send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
6b3087c6	211	}
6b3087c6	212
50888469	213	void arch_send_call_function_ipi_mask(const struct cpumask *mask)
6b3087c6	214	{
50888469	215	send_ipi(mask, BFIN_IPI_CALL_FUNC);
6b3087c6	216	}
6b3087c6 GY	217
	218	void smp_send_reschedule(int cpu)
	219	{
50888469	220	send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);
6b3087c6 GY	221
	222	return;
	223	}
	224
d0014be4 BL	225	void smp_send_msg(const struct cpumask *mask, unsigned long type)
d0014be4 BL	226	{
50888469	227	send_ipi(mask, type);
d0014be4 BL	228	}
	229
	230	void smp_timer_broadcast(const struct cpumask *mask)
	231	{
	232	smp_send_msg(mask, BFIN_IPI_TIMER);
	233	}
	234
6b3087c6 GY	235	void smp_send_stop(void)
6b3087c6 GY	236	{
6b3087c6	237	cpumask_t callmap;
6b3087c6	238
567ebfc9	239	preempt_disable();
fecedc80 KM	240	cpumask_copy(&callmap, cpu_online_mask);
	241	cpumask_clear_cpu(smp_processor_id(), &callmap);
	242	if (!cpumask_empty(&callmap))
50888469	243	send_ipi(&callmap, BFIN_IPI_CPU_STOP);
6b3087c6	244
567ebfc9	245	preempt_enable();
6b3087c6	246
6b3087c6 GY	247	return;
	248	}
	249
13dff62d	250	int __cpu_up(unsigned int cpu, struct task_struct *idle)
6b3087c6	251	{
6b3087c6	252	int ret;
0b39db28	253
6b3087c6	254	secondary_stack = task_stack_page(idle) + THREAD_SIZE;
6b3087c6 GY	255
	256	ret = platform_boot_secondary(cpu, idle);
	257
6b3087c6 GY	258	secondary_stack = NULL;
	259
	260	return ret;
	261	}
	262
13dff62d	263	static void setup_secondary(unsigned int cpu)
6b3087c6	264	{
6b3087c6 GY	265	unsigned long ilat;
	266
	267	bfin_write_IMASK(0);
	268	CSYNC();
	269	ilat = bfin_read_ILAT();
	270	CSYNC();
	271	bfin_write_ILAT(ilat);
	272	CSYNC();
	273
6b3087c6 GY	274	/* Enable interrupt levels IVG7-15. IARs have been already
6b3087c6 GY	275	* programmed by the boot CPU. */
40059784	276	bfin_irq_flags \|= IMASK_IVG15 \|
6b3087c6 GY	277	IMASK_IVG14 \| IMASK_IVG13 \| IMASK_IVG12 \| IMASK_IVG11 \|
6b3087c6 GY	278	IMASK_IVG10 \| IMASK_IVG9 \| IMASK_IVG8 \| IMASK_IVG7 \| IMASK_IVGHW;
6b3087c6 GY	279	}
6b3087c6 GY	280
13dff62d	281	void secondary_start_kernel(void)
6b3087c6 GY	282	{
	283	unsigned int cpu = smp_processor_id();
	284	struct mm_struct *mm = &init_mm;
	285
	286	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
	287	printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
	288	#ifdef CONFIG_DEBUG_DOUBLEFAULT
fb1d9be5 MF	289	printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
	290	initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
	291	initial_pda_coreb.retx_doublefault);
	292	printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
	293	initial_pda_coreb.dcplb_doublefault_addr);
	294	printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
	295	initial_pda_coreb.icplb_doublefault_addr);
6b3087c6 GY	296	#endif
6b3087c6 GY	297	printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
fb1d9be5	298	initial_pda_coreb.retx);
6b3087c6 GY	299	}
	300
	301	/*
	302	* We want the D-cache to be enabled early, in case the atomic
	303	* support code emulates cache coherence (see
	304	* __ARCH_SYNC_CORE_DCACHE).
	305	*/
	306	init_exception_vectors();
	307
6b3087c6 GY	308	local_irq_disable();
	309
	310	/* Attach the new idle task to the global mm. */
3fce371b	311	mmget(mm);
f1f10076	312	mmgrab(mm);
6b3087c6	313	current->active_mm = mm;
6b3087c6 GY	314
	315	preempt_disable();
	316
	317	setup_secondary(cpu);
	318
578d36f5	319	platform_secondary_init(cpu);
0d152c27 YL	320	/* setup local core timer */
	321	bfin_local_timer_setup();
	322
6b3087c6 GY	323	local_irq_enable();
6b3087c6 GY	324
ab61d2ac	325	bfin_setup_caches(cpu);
ab61d2ac	326
d0014be4	327	notify_cpu_starting(cpu);
578d36f5 YL	328	/*
	329	* Calibrate loops per jiffy value.
	330	* IRQs need to be enabled here - D-cache can be invalidated
	331	* in timer irq handler, so core B can read correct jiffies.
	332	*/
	333	calibrate_delay();
6b3087c6	334
150382a5 SM	335	/* We are done with local CPU inits, unblock the boot CPU. */
150382a5 SM	336	set_cpu_online(cpu, true);
fc6d73d6	337	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
6b3087c6 GY	338	}
	339
	340	void __init smp_prepare_boot_cpu(void)
	341	{
	342	}
	343
	344	void __init smp_prepare_cpus(unsigned int max_cpus)
	345	{
	346	platform_prepare_cpus(max_cpus);
50888469	347	bfin_ipi_init();
73a40064 YL	348	platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
73a40064 YL	349	platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
6b3087c6 GY	350	}
	351
	352	void __init smp_cpus_done(unsigned int max_cpus)
	353	{
	354	unsigned long bogosum = 0;
	355	unsigned int cpu;
	356
	357	for_each_online_cpu(cpu)
c70c754f	358	bogosum += loops_per_jiffy;
6b3087c6 GY	359
	360	printk(KERN_INFO "SMP: Total of %d processors activated "
	361	"(%lu.%02lu BogoMIPS).\n",
	362	num_online_cpus(),
	363	bogosum / (500000/HZ),
	364	(bogosum / (5000/HZ)) % 100);
	365	}
	366
	367	void smp_icache_flush_range_others(unsigned long start, unsigned long end)
	368	{
	369	smp_flush_data.start = start;
	370	smp_flush_data.end = end;
	371
a2eff9dd SM	372	preempt_disable();
a2eff9dd SM	373	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
6b3087c6	374	printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
a2eff9dd	375	preempt_enable();
6b3087c6 GY	376	}
	377	EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
	378
47e9dedb	379	#ifdef __ARCH_SYNC_CORE_ICACHE
718340f6	380	unsigned long icache_invld_count[NR_CPUS];
47e9dedb SZ	381	void resync_core_icache(void)
	382	{
	383	unsigned int cpu = get_cpu();
	384	blackfin_invalidate_entire_icache();
718340f6	385	icache_invld_count[cpu]++;
47e9dedb SZ	386	put_cpu();
	387	}
	388	EXPORT_SYMBOL(resync_core_icache);
	389	#endif
	390
6b3087c6	391	#ifdef __ARCH_SYNC_CORE_DCACHE
718340f6	392	unsigned long dcache_invld_count[NR_CPUS];
6b3087c6 GY	393	unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
	394
	395	void resync_core_dcache(void)
	396	{
	397	unsigned int cpu = get_cpu();
	398	blackfin_invalidate_entire_dcache();
718340f6	399	dcache_invld_count[cpu]++;
6b3087c6 GY	400	put_cpu();
	401	}
	402	EXPORT_SYMBOL(resync_core_dcache);
	403	#endif
0b39db28 GY	404
0b39db28 GY	405	#ifdef CONFIG_HOTPLUG_CPU
13dff62d	406	int __cpu_disable(void)
0b39db28 GY	407	{
	408	unsigned int cpu = smp_processor_id();
	409
	410	if (cpu == 0)
	411	return -EPERM;
	412
	413	set_cpu_online(cpu, false);
	414	return 0;
	415	}
	416
13dff62d	417	int __cpu_die(unsigned int cpu)
0b39db28	418	{
a17b4b74	419	return cpu_wait_death(cpu, 5);
0b39db28 GY	420	}
	421
	422	void cpu_die(void)
	423	{
a17b4b74	424	(void)cpu_report_death();
0b39db28 GY	425
	426	atomic_dec(&init_mm.mm_users);
	427	atomic_dec(&init_mm.mm_count);
	428
	429	local_irq_disable();
	430	platform_cpu_die();
	431	}
	432	#endif