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Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
[linux-2.6-block.git] / arch / blackfin / mach-common / ints-priority.c
CommitLineData
1394f032 1/*
cfefe3c6 2 * File: arch/blackfin/mach-common/ints-priority.c
1394f032
BW		 3 * Based on:
4 * Author:
5 *
6 * Created: ?
d2d50aa9 7 * Description: Set up the interrupt priorities
1394f032
BW		 8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
cfefe3c6 16 * Copyright 2004-2008 Analog Devices Inc.
1394f032
BW		 17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36#include <linux/module.h>
37#include <linux/kernel_stat.h>
38#include <linux/seq_file.h>
39#include <linux/irq.h>
40#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
48#ifdef BF537_FAMILY
49# define BF537_GENERIC_ERROR_INT_DEMUX
50#else
51# undef BF537_GENERIC_ERROR_INT_DEMUX
52#endif
53
54/*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
a99bbccd
MF		 61/* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67unsigned long irq_flags = 0x1f;
1394f032
BW		 68
69/* The number of spurious interrupts */
70atomic_t num_spurious;
71
cfefe3c6
MH		 72#ifdef CONFIG_PM
73unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
4a88d0ce 74unsigned vr_wakeup;
cfefe3c6
MH		 75#endif
76
1394f032 77struct ivgx {
464abc5d 78 /* irq number for request_irq, available in mach-bf5xx/irq.h */
24a07a12 79 unsigned int irqno;
1394f032 80 /* corresponding bit in the SIC_ISR register */
24a07a12 81 unsigned int isrflag;
1394f032
BW		 82} ivg_table[NR_PERI_INTS];
83
84struct ivg_slice {
85 /* position of first irq in ivg_table for given ivg */
86 struct ivgx *ifirst;
87 struct ivgx *istop;
88} ivg7_13[IVG13 - IVG7 + 1];
89
1394f032
BW		 90
91/*
92 * Search SIC_IAR and fill tables with the irqvalues
93 * and their positions in the SIC_ISR register.
94 */
95static void __init search_IAR(void)
96{
97 unsigned ivg, irq_pos = 0;
98 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
99 int irqn;
100
34e0fc89 101 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
1394f032
BW		 102
103 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
104 int iar_shift = (irqn & 7) * 4;
2c4f829b 105 if (ivg == (0xf &
59003145 106#ifndef CONFIG_BF52x
34e0fc89 107 bfin_read32((unsigned long *)SIC_IAR0 +
1394f032 108 (irqn >> 3)) >> iar_shift)) {
59003145
MH		 109#else
110 bfin_read32((unsigned long *)SIC_IAR0 +
111 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
112#endif
1394f032 113 ivg_table[irq_pos].irqno = IVG7 + irqn;
24a07a12 114 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
1394f032
BW		 115 ivg7_13[ivg].istop++;
116 irq_pos++;
117 }
118 }
119 }
120}
121
122/*
464abc5d 123 * This is for core internal IRQs
1394f032
BW		 124 */
125
464abc5d 126static void bfin_ack_noop(unsigned int irq)
1394f032
BW		 127{
128 /* Dummy function. */
129}
130
131static void bfin_core_mask_irq(unsigned int irq)
132{
133 irq_flags &= ~(1 << irq);
134 if (!irqs_disabled())
135 local_irq_enable();
136}
137
138static void bfin_core_unmask_irq(unsigned int irq)
139{
140 irq_flags |= 1 << irq;
141 /*
142 * If interrupts are enabled, IMASK must contain the same value
143 * as irq_flags. Make sure that invariant holds. If interrupts
144 * are currently disabled we need not do anything; one of the
145 * callers will take care of setting IMASK to the proper value
146 * when reenabling interrupts.
147 * local_irq_enable just does "STI irq_flags", so it's exactly
148 * what we need.
149 */
150 if (!irqs_disabled())
151 local_irq_enable();
152 return;
153}
154
155static void bfin_internal_mask_irq(unsigned int irq)
156{
59003145 157#ifdef CONFIG_BF53x
1394f032 158 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
464abc5d 159 ~(1 << SIC_SYSIRQ(irq)));
24a07a12
RH		 160#else
161 unsigned mask_bank, mask_bit;
464abc5d
MH		 162 mask_bank = SIC_SYSIRQ(irq) / 32;
163 mask_bit = SIC_SYSIRQ(irq) % 32;
c04d66bb
BW		 164 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
165 ~(1 << mask_bit));
24a07a12 166#endif
1394f032
BW		 167 SSYNC();
168}
169
170static void bfin_internal_unmask_irq(unsigned int irq)
171{
59003145 172#ifdef CONFIG_BF53x
1394f032 173 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
464abc5d 174 (1 << SIC_SYSIRQ(irq)));
24a07a12
RH		 175#else
176 unsigned mask_bank, mask_bit;
464abc5d
MH		 177 mask_bank = SIC_SYSIRQ(irq) / 32;
178 mask_bit = SIC_SYSIRQ(irq) % 32;
c04d66bb
BW		 179 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
180 (1 << mask_bit));
24a07a12 181#endif
1394f032
BW		 182 SSYNC();
183}
184
cfefe3c6
MH		 185#ifdef CONFIG_PM
186int bfin_internal_set_wake(unsigned int irq, unsigned int state)
187{
4a88d0ce 188 unsigned bank, bit, wakeup = 0;
cfefe3c6 189 unsigned long flags;
464abc5d
MH		 190 bank = SIC_SYSIRQ(irq) / 32;
191 bit = SIC_SYSIRQ(irq) % 32;
cfefe3c6 192
4a88d0ce
MH		 193 switch (irq) {
194#ifdef IRQ_RTC
195 case IRQ_RTC:
196 wakeup |= WAKE;
197 break;
198#endif
199#ifdef IRQ_CAN0_RX
200 case IRQ_CAN0_RX:
201 wakeup |= CANWE;
202 break;
203#endif
204#ifdef IRQ_CAN1_RX
205 case IRQ_CAN1_RX:
206 wakeup |= CANWE;
207 break;
208#endif
209#ifdef IRQ_USB_INT0
210 case IRQ_USB_INT0:
211 wakeup |= USBWE;
212 break;
213#endif
214#ifdef IRQ_KEY
215 case IRQ_KEY:
216 wakeup |= KPADWE;
217 break;
218#endif
d310fb4b 219#ifdef CONFIG_BF54x
4a88d0ce
MH		 220 case IRQ_CNT:
221 wakeup |= ROTWE;
222 break;
223#endif
224 default:
225 break;
226 }
227
cfefe3c6
MH		 228 local_irq_save(flags);
229
4a88d0ce 230 if (state) {
cfefe3c6 231 bfin_sic_iwr[bank] |= (1 << bit);
4a88d0ce
MH		 232 vr_wakeup |= wakeup;
233
234 } else {
cfefe3c6 235 bfin_sic_iwr[bank] &= ~(1 << bit);
4a88d0ce
MH		 236 vr_wakeup &= ~wakeup;
237 }
cfefe3c6
MH		 238
239 local_irq_restore(flags);
240
241 return 0;
242}
243#endif
244
1394f032 245static struct irq_chip bfin_core_irqchip = {
763e63c6 246 .name = "CORE",
464abc5d 247 .ack = bfin_ack_noop,
1394f032
BW		 248 .mask = bfin_core_mask_irq,
249 .unmask = bfin_core_unmask_irq,
250};
251
252static struct irq_chip bfin_internal_irqchip = {
763e63c6 253 .name = "INTN",
464abc5d 254 .ack = bfin_ack_noop,
1394f032
BW		 255 .mask = bfin_internal_mask_irq,
256 .unmask = bfin_internal_unmask_irq,
ce3b7bb6
MH		 257 .mask_ack = bfin_internal_mask_irq,
258 .disable = bfin_internal_mask_irq,
259 .enable = bfin_internal_unmask_irq,
cfefe3c6
MH		 260#ifdef CONFIG_PM
261 .set_wake = bfin_internal_set_wake,
262#endif
1394f032
BW		 263};
264
265#ifdef BF537_GENERIC_ERROR_INT_DEMUX
266static int error_int_mask;
267
1394f032
BW		 268static void bfin_generic_error_mask_irq(unsigned int irq)
269{
270 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
271
464abc5d
MH		 272 if (!error_int_mask)
273 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
1394f032
BW		 274}
275
276static void bfin_generic_error_unmask_irq(unsigned int irq)
277{
464abc5d 278 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
1394f032
BW		 279 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
280}
281
282static struct irq_chip bfin_generic_error_irqchip = {
763e63c6 283 .name = "ERROR",
464abc5d
MH		 284 .ack = bfin_ack_noop,
285 .mask_ack = bfin_generic_error_mask_irq,
1394f032
BW		 286 .mask = bfin_generic_error_mask_irq,
287 .unmask = bfin_generic_error_unmask_irq,
288};
289
290static void bfin_demux_error_irq(unsigned int int_err_irq,
2c4f829b 291 struct irq_desc *inta_desc)
1394f032
BW		 292{
293 int irq = 0;
294
295 SSYNC();
296
297#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
298 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
299 irq = IRQ_MAC_ERROR;
300 else
301#endif
302 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
303 irq = IRQ_SPORT0_ERROR;
304 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
305 irq = IRQ_SPORT1_ERROR;
306 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
307 irq = IRQ_PPI_ERROR;
308 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
309 irq = IRQ_CAN_ERROR;
310 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
311 irq = IRQ_SPI_ERROR;
312 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
313 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
314 irq = IRQ_UART0_ERROR;
315 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
316 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
317 irq = IRQ_UART1_ERROR;
318
319 if (irq) {
320 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
321 struct irq_desc *desc = irq_desc + irq;
322 desc->handle_irq(irq, desc);
323 } else {
324
325 switch (irq) {
326 case IRQ_PPI_ERROR:
327 bfin_write_PPI_STATUS(PPI_ERR_MASK);
328 break;
329#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
330 case IRQ_MAC_ERROR:
331 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
332 break;
333#endif
334 case IRQ_SPORT0_ERROR:
335 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
336 break;
337
338 case IRQ_SPORT1_ERROR:
339 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
340 break;
341
342 case IRQ_CAN_ERROR:
343 bfin_write_CAN_GIS(CAN_ERR_MASK);
344 break;
345
346 case IRQ_SPI_ERROR:
347 bfin_write_SPI_STAT(SPI_ERR_MASK);
348 break;
349
350 default:
351 break;
352 }
353
354 pr_debug("IRQ %d:"
34e0fc89
MH		 355 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
356 irq);
1394f032
BW		 357 }
358 } else
359 printk(KERN_ERR
360 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
361 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
b85d858b 362 __func__, __FILE__, __LINE__);
1394f032 363
1394f032
BW		 364}
365#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
366
bfd15117
GY		 367static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
368{
369 struct irq_desc *desc = irq_desc + irq;
370 /* May not call generic set_irq_handler() due to spinlock
371 recursion. */
372 desc->handle_irq = handle;
373}
374
a055b2b4 375#if !defined(CONFIG_BF54x)
1394f032
BW		 376
377static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
378static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
379
affee2b2 380extern void bfin_gpio_irq_prepare(unsigned gpio);
6fce6a8d 381
1394f032
BW		 382static void bfin_gpio_ack_irq(unsigned int irq)
383{
384 u16 gpionr = irq - IRQ_PF0;
385
386 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
387 set_gpio_data(gpionr, 0);
388 SSYNC();
389 }
390}
391
392static void bfin_gpio_mask_ack_irq(unsigned int irq)
393{
394 u16 gpionr = irq - IRQ_PF0;
395
396 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
397 set_gpio_data(gpionr, 0);
398 SSYNC();
399 }
400
401 set_gpio_maska(gpionr, 0);
402 SSYNC();
403}
404
405static void bfin_gpio_mask_irq(unsigned int irq)
406{
407 set_gpio_maska(irq - IRQ_PF0, 0);
408 SSYNC();
409}
410
411static void bfin_gpio_unmask_irq(unsigned int irq)
412{
413 set_gpio_maska(irq - IRQ_PF0, 1);
414 SSYNC();
415}
416
417static unsigned int bfin_gpio_irq_startup(unsigned int irq)
418{
1394f032
BW		 419 u16 gpionr = irq - IRQ_PF0;
420
affee2b2
MH		 421 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
422 bfin_gpio_irq_prepare(gpionr);
1394f032
BW		 423
424 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
425 bfin_gpio_unmask_irq(irq);
426
affee2b2 427 return 0;
1394f032
BW		 428}
429
430static void bfin_gpio_irq_shutdown(unsigned int irq)
431{
432 bfin_gpio_mask_irq(irq);
1394f032
BW		 433 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
434}
435
436static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
437{
1394f032
BW		 438 u16 gpionr = irq - IRQ_PF0;
439
440 if (type == IRQ_TYPE_PROBE) {
441 /* only probe unenabled GPIO interrupt lines */
442 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
443 return 0;
444 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
445 }
446
447 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
34e0fc89 448 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
affee2b2
MH		 449 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
450 bfin_gpio_irq_prepare(gpionr);
1394f032
BW		 451
452 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
453 } else {
454 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
455 return 0;
456 }
457
f1bceb47 458 set_gpio_inen(gpionr, 0);
1394f032 459 set_gpio_dir(gpionr, 0);
1394f032
BW		 460
461 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
462 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
463 set_gpio_both(gpionr, 1);
464 else
465 set_gpio_both(gpionr, 0);
466
467 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
468 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
469 else
470 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
471
f1bceb47
MH		 472 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
473 set_gpio_edge(gpionr, 1);
474 set_gpio_inen(gpionr, 1);
475 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
476 set_gpio_data(gpionr, 0);
477
478 } else {
479 set_gpio_edge(gpionr, 0);
480 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
481 set_gpio_inen(gpionr, 1);
482 }
483
1394f032
BW		 484 SSYNC();
485
486 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
bfd15117 487 bfin_set_irq_handler(irq, handle_edge_irq);
1394f032 488 else
bfd15117 489 bfin_set_irq_handler(irq, handle_level_irq);
1394f032
BW		 490
491 return 0;
492}
493
cfefe3c6
MH		 494#ifdef CONFIG_PM
495int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
496{
497 unsigned gpio = irq_to_gpio(irq);
498
499 if (state)
500 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
501 else
502 gpio_pm_wakeup_free(gpio);
503
504 return 0;
505}
506#endif
507
1394f032 508static struct irq_chip bfin_gpio_irqchip = {
763e63c6 509 .name = "GPIO",
1394f032
BW		 510 .ack = bfin_gpio_ack_irq,
511 .mask = bfin_gpio_mask_irq,
512 .mask_ack = bfin_gpio_mask_ack_irq,
513 .unmask = bfin_gpio_unmask_irq,
1f2d1869
MH		 514 .disable = bfin_gpio_mask_irq,
515 .enable = bfin_gpio_unmask_irq,
1394f032
BW		 516 .set_type = bfin_gpio_irq_type,
517 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 518 .shutdown = bfin_gpio_irq_shutdown,
519#ifdef CONFIG_PM
520 .set_wake = bfin_gpio_set_wake,
521#endif
1394f032
BW		 522};
523
2c4f829b
MH		 524static void bfin_demux_gpio_irq(unsigned int inta_irq,
525 struct irq_desc *desc)
1394f032 526{
2c4f829b
MH		 527 unsigned int i, gpio, mask, irq, search = 0;
528
529 switch (inta_irq) {
530#if defined(CONFIG_BF53x)
531 case IRQ_PROG_INTA:
532 irq = IRQ_PF0;
533 search = 1;
534 break;
535# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
536 case IRQ_MAC_RX:
537 irq = IRQ_PH0;
538 break;
539# endif
540#elif defined(CONFIG_BF52x)
541 case IRQ_PORTF_INTA:
542 irq = IRQ_PF0;
543 break;
544 case IRQ_PORTG_INTA:
545 irq = IRQ_PG0;
546 break;
547 case IRQ_PORTH_INTA:
548 irq = IRQ_PH0;
549 break;
550#elif defined(CONFIG_BF561)
551 case IRQ_PROG0_INTA:
552 irq = IRQ_PF0;
553 break;
554 case IRQ_PROG1_INTA:
555 irq = IRQ_PF16;
556 break;
557 case IRQ_PROG2_INTA:
558 irq = IRQ_PF32;
559 break;
560#endif
561 default:
562 BUG();
563 return;
564 }
565
566 if (search) {
cfefe3c6 567 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
2c4f829b
MH		 568 irq += i;
569
570 mask = get_gpiop_data(i) &
571 (gpio_enabled[gpio_bank(i)] &
572 get_gpiop_maska(i));
573
574 while (mask) {
575 if (mask & 1) {
576 desc = irq_desc + irq;
577 desc->handle_irq(irq, desc);
578 }
579 irq++;
580 mask >>= 1;
1394f032 581 }
1394f032 582 }
2c4f829b
MH		 583 } else {
584 gpio = irq_to_gpio(irq);
585 mask = get_gpiop_data(gpio) &
586 (gpio_enabled[gpio_bank(gpio)] &
587 get_gpiop_maska(gpio));
588
589 do {
590 if (mask & 1) {
591 desc = irq_desc + irq;
592 desc->handle_irq(irq, desc);
593 }
594 irq++;
595 mask >>= 1;
596 } while (mask);
1394f032 597 }
2c4f829b 598
1394f032
BW		 599}
600
a055b2b4 601#else /* CONFIG_BF54x */
34e0fc89
MH		 602
603#define NR_PINT_SYS_IRQS 4
604#define NR_PINT_BITS 32
605#define NR_PINTS 160
606#define IRQ_NOT_AVAIL 0xFF
607
608#define PINT_2_BANK(x) ((x) >> 5)
609#define PINT_2_BIT(x) ((x) & 0x1F)
610#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
611
612static unsigned char irq2pint_lut[NR_PINTS];
e3f23000 613static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
34e0fc89 614
8baf560b
MH		 615static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
616static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
617
618
34e0fc89
MH		 619struct pin_int_t {
620 unsigned int mask_set;
621 unsigned int mask_clear;
622 unsigned int request;
623 unsigned int assign;
624 unsigned int edge_set;
625 unsigned int edge_clear;
626 unsigned int invert_set;
627 unsigned int invert_clear;
628 unsigned int pinstate;
629 unsigned int latch;
630};
631
632static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
633 (struct pin_int_t *)PINT0_MASK_SET,
634 (struct pin_int_t *)PINT1_MASK_SET,
635 (struct pin_int_t *)PINT2_MASK_SET,
636 (struct pin_int_t *)PINT3_MASK_SET,
637};
638
affee2b2
MH		 639extern void bfin_gpio_irq_prepare(unsigned gpio);
640
464abc5d 641inline unsigned short get_irq_base(u8 bank, u8 bmap)
34e0fc89
MH		 642{
643
644 u16 irq_base;
645
646 if (bank < 2) { /*PA-PB */
647 irq_base = IRQ_PA0 + bmap * 16;
648 } else { /*PC-PJ */
649 irq_base = IRQ_PC0 + bmap * 16;
650 }
651
652 return irq_base;
653
654}
655
656 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
657void init_pint_lut(void)
658{
659 u16 bank, bit, irq_base, bit_pos;
660 u32 pint_assign;
661 u8 bmap;
662
663 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
664
665 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
666
667 pint_assign = pint[bank]->assign;
668
669 for (bit = 0; bit < NR_PINT_BITS; bit++) {
670
671 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
672
673 irq_base = get_irq_base(bank, bmap);
674
675 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
676 bit_pos = bit + bank * NR_PINT_BITS;
677
e3f23000 678 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
34e0fc89
MH		 679 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
680
681 }
682
683 }
684
685}
686
34e0fc89
MH		 687static void bfin_gpio_ack_irq(unsigned int irq)
688{
689 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
8baf560b
MH		 690 u32 pintbit = PINT_BIT(pint_val);
691 u8 bank = PINT_2_BANK(pint_val);
692
693 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
694 if (pint[bank]->invert_set & pintbit)
695 pint[bank]->invert_clear = pintbit;
696 else
697 pint[bank]->invert_set = pintbit;
698 }
699 pint[bank]->request = pintbit;
34e0fc89 700
34e0fc89
MH		 701 SSYNC();
702}
703
704static void bfin_gpio_mask_ack_irq(unsigned int irq)
705{
706 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 707 u32 pintbit = PINT_BIT(pint_val);
708 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 709
8baf560b
MH		 710 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
711 if (pint[bank]->invert_set & pintbit)
712 pint[bank]->invert_clear = pintbit;
713 else
714 pint[bank]->invert_set = pintbit;
715 }
716
e3f23000
MH		 717 pint[bank]->request = pintbit;
718 pint[bank]->mask_clear = pintbit;
34e0fc89
MH		 719 SSYNC();
720}
721
722static void bfin_gpio_mask_irq(unsigned int irq)
723{
724 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
725
726 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
727 SSYNC();
728}
729
730static void bfin_gpio_unmask_irq(unsigned int irq)
731{
732 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 733 u32 pintbit = PINT_BIT(pint_val);
734 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 735
e3f23000
MH		 736 pint[bank]->request = pintbit;
737 pint[bank]->mask_set = pintbit;
34e0fc89
MH		 738 SSYNC();
739}
740
741static unsigned int bfin_gpio_irq_startup(unsigned int irq)
742{
8baf560b 743 u16 gpionr = irq_to_gpio(irq);
34e0fc89
MH		 744 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
745
50e163ce
MH		 746 if (pint_val == IRQ_NOT_AVAIL) {
747 printk(KERN_ERR
748 "GPIO IRQ %d :Not in PINT Assign table "
749 "Reconfigure Interrupt to Port Assignemt\n", irq);
34e0fc89 750 return -ENODEV;
50e163ce 751 }
34e0fc89 752
affee2b2
MH		 753 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
754 bfin_gpio_irq_prepare(gpionr);
34e0fc89
MH		 755
756 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
757 bfin_gpio_unmask_irq(irq);
758
affee2b2 759 return 0;
34e0fc89
MH		 760}
761
762static void bfin_gpio_irq_shutdown(unsigned int irq)
763{
8baf560b
MH		 764 u16 gpionr = irq_to_gpio(irq);
765
34e0fc89 766 bfin_gpio_mask_irq(irq);
8baf560b 767 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
34e0fc89
MH		 768}
769
770static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
771{
772
8baf560b 773 u16 gpionr = irq_to_gpio(irq);
34e0fc89 774 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 775 u32 pintbit = PINT_BIT(pint_val);
776 u8 bank = PINT_2_BANK(pint_val);
34e0fc89
MH		 777
778 if (pint_val == IRQ_NOT_AVAIL)
779 return -ENODEV;
780
781 if (type == IRQ_TYPE_PROBE) {
782 /* only probe unenabled GPIO interrupt lines */
783 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
784 return 0;
785 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
786 }
787
788 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
789 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
affee2b2
MH		 790 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
791 bfin_gpio_irq_prepare(gpionr);
34e0fc89
MH		 792
793 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
794 } else {
795 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
796 return 0;
797 }
798
34e0fc89 799 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
e3f23000 800 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
34e0fc89 801 else
8baf560b 802 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
34e0fc89 803
8baf560b
MH		 804 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
805 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
34e0fc89 806
8baf560b 807 gpio_both_edge_triggered[bank] |= pintbit;
34e0fc89 808
8baf560b
MH		 809 if (gpio_get_value(gpionr))
810 pint[bank]->invert_set = pintbit;
811 else
812 pint[bank]->invert_clear = pintbit;
813 } else {
814 gpio_both_edge_triggered[bank] &= ~pintbit;
815 }
816
817 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
818 pint[bank]->edge_set = pintbit;
bfd15117 819 bfin_set_irq_handler(irq, handle_edge_irq);
8baf560b
MH		 820 } else {
821 pint[bank]->edge_clear = pintbit;
bfd15117 822 bfin_set_irq_handler(irq, handle_level_irq);
8baf560b
MH		 823 }
824
825 SSYNC();
34e0fc89
MH		 826
827 return 0;
828}
829
cfefe3c6
MH		 830#ifdef CONFIG_PM
831u32 pint_saved_masks[NR_PINT_SYS_IRQS];
832u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
833
834int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
835{
836 u32 pint_irq;
837 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
838 u32 bank = PINT_2_BANK(pint_val);
839 u32 pintbit = PINT_BIT(pint_val);
840
841 switch (bank) {
842 case 0:
843 pint_irq = IRQ_PINT0;
844 break;
845 case 2:
846 pint_irq = IRQ_PINT2;
847 break;
848 case 3:
849 pint_irq = IRQ_PINT3;
850 break;
851 case 1:
852 pint_irq = IRQ_PINT1;
853 break;
854 default:
855 return -EINVAL;
856 }
857
858 bfin_internal_set_wake(pint_irq, state);
859
860 if (state)
861 pint_wakeup_masks[bank] |= pintbit;
862 else
863 pint_wakeup_masks[bank] &= ~pintbit;
864
865 return 0;
866}
867
868u32 bfin_pm_setup(void)
869{
870 u32 val, i;
871
872 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
873 val = pint[i]->mask_clear;
874 pint_saved_masks[i] = val;
875 if (val ^ pint_wakeup_masks[i]) {
876 pint[i]->mask_clear = val;
877 pint[i]->mask_set = pint_wakeup_masks[i];
878 }
879 }
880
881 return 0;
882}
883
884void bfin_pm_restore(void)
885{
886 u32 i, val;
887
888 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
889 val = pint_saved_masks[i];
890 if (val ^ pint_wakeup_masks[i]) {
891 pint[i]->mask_clear = pint[i]->mask_clear;
892 pint[i]->mask_set = val;
893 }
894 }
895}
896#endif
897
34e0fc89 898static struct irq_chip bfin_gpio_irqchip = {
763e63c6 899 .name = "GPIO",
34e0fc89
MH		 900 .ack = bfin_gpio_ack_irq,
901 .mask = bfin_gpio_mask_irq,
902 .mask_ack = bfin_gpio_mask_ack_irq,
903 .unmask = bfin_gpio_unmask_irq,
1f2d1869
MH		 904 .disable = bfin_gpio_mask_irq,
905 .enable = bfin_gpio_unmask_irq,
34e0fc89
MH		 906 .set_type = bfin_gpio_irq_type,
907 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 908 .shutdown = bfin_gpio_irq_shutdown,
909#ifdef CONFIG_PM
910 .set_wake = bfin_gpio_set_wake,
911#endif
34e0fc89
MH		 912};
913
2c4f829b
MH		 914static void bfin_demux_gpio_irq(unsigned int inta_irq,
915 struct irq_desc *desc)
34e0fc89
MH		 916{
917 u8 bank, pint_val;
918 u32 request, irq;
919
2c4f829b 920 switch (inta_irq) {
34e0fc89
MH		 921 case IRQ_PINT0:
922 bank = 0;
923 break;
924 case IRQ_PINT2:
925 bank = 2;
926 break;
927 case IRQ_PINT3:
928 bank = 3;
929 break;
930 case IRQ_PINT1:
931 bank = 1;
932 break;
e3f23000
MH		 933 default:
934 return;
34e0fc89
MH		 935 }
936
937 pint_val = bank * NR_PINT_BITS;
938
939 request = pint[bank]->request;
940
941 while (request) {
942 if (request & 1) {
e3f23000
MH		 943 irq = pint2irq_lut[pint_val] + SYS_IRQS;
944 desc = irq_desc + irq;
34e0fc89
MH		 945 desc->handle_irq(irq, desc);
946 }
947 pint_val++;
948 request >>= 1;
949 }
950
951}
a055b2b4 952#endif
1394f032 953
8be80ed3
BS		 954void __init init_exception_vectors(void)
955{
956 SSYNC();
957
f0b5d12f
MF		 958 /* cannot program in software:
959 * evt0 - emulation (jtag)
960 * evt1 - reset
961 */
962 bfin_write_EVT2(evt_nmi);
8be80ed3
BS		 963 bfin_write_EVT3(trap);
964 bfin_write_EVT5(evt_ivhw);
965 bfin_write_EVT6(evt_timer);
966 bfin_write_EVT7(evt_evt7);
967 bfin_write_EVT8(evt_evt8);
968 bfin_write_EVT9(evt_evt9);
969 bfin_write_EVT10(evt_evt10);
970 bfin_write_EVT11(evt_evt11);
971 bfin_write_EVT12(evt_evt12);
972 bfin_write_EVT13(evt_evt13);
973 bfin_write_EVT14(evt14_softirq);
974 bfin_write_EVT15(evt_system_call);
975 CSYNC();
976}
977
1394f032
BW		 978/*
979 * This function should be called during kernel startup to initialize
980 * the BFin IRQ handling routines.
981 */
982int __init init_arch_irq(void)
983{
984 int irq;
985 unsigned long ilat = 0;
986 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
2c4f829b 987#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
24a07a12
RH		 988 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
989 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
a055b2b4 990# ifdef CONFIG_BF54x
59003145 991 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
a055b2b4 992# endif
24a07a12 993#else
1394f032 994 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
24a07a12 995#endif
1394f032
BW		 996
997 local_irq_disable();
998
d70536ec 999#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
95a86b5e
MF		 1000 /* Clear EMAC Interrupt Status bits so we can demux it later */
1001 bfin_write_EMAC_SYSTAT(-1);
1002#endif
1003
a055b2b4
MF		 1004#ifdef CONFIG_BF54x
1005# ifdef CONFIG_PINTx_REASSIGN
34e0fc89
MH		 1006 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1007 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1008 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1009 pint[3]->assign = CONFIG_PINT3_ASSIGN;
a055b2b4 1010# endif
34e0fc89
MH		 1011 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1012 init_pint_lut();
1013#endif
1014
1015 for (irq = 0; irq <= SYS_IRQS; irq++) {
1394f032
BW		 1016 if (irq <= IRQ_CORETMR)
1017 set_irq_chip(irq, &bfin_core_irqchip);
1018 else
1019 set_irq_chip(irq, &bfin_internal_irqchip);
1394f032 1020
464abc5d 1021 switch (irq) {
59003145 1022#if defined(CONFIG_BF53x)
464abc5d 1023 case IRQ_PROG_INTA:
a055b2b4 1024# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
464abc5d 1025 case IRQ_MAC_RX:
a055b2b4 1026# endif
59003145 1027#elif defined(CONFIG_BF54x)
464abc5d
MH		 1028 case IRQ_PINT0:
1029 case IRQ_PINT1:
1030 case IRQ_PINT2:
1031 case IRQ_PINT3:
59003145 1032#elif defined(CONFIG_BF52x)
464abc5d
MH		 1033 case IRQ_PORTF_INTA:
1034 case IRQ_PORTG_INTA:
1035 case IRQ_PORTH_INTA:
2c4f829b 1036#elif defined(CONFIG_BF561)
464abc5d
MH		 1037 case IRQ_PROG0_INTA:
1038 case IRQ_PROG1_INTA:
1039 case IRQ_PROG2_INTA:
1394f032 1040#endif
464abc5d
MH		 1041 set_irq_chained_handler(irq,
1042 bfin_demux_gpio_irq);
1043 break;
1394f032 1044#ifdef BF537_GENERIC_ERROR_INT_DEMUX
464abc5d 1045 case IRQ_GENERIC_ERROR:
1394f032 1046 set_irq_handler(irq, bfin_demux_error_irq);
464abc5d
MH		 1047
1048 break;
1394f032 1049#endif
464abc5d
MH		 1050 default:
1051 set_irq_handler(irq, handle_simple_irq);
1052 break;
1053 }
1394f032 1054 }
464abc5d 1055
1394f032 1056#ifdef BF537_GENERIC_ERROR_INT_DEMUX
464abc5d
MH		 1057 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1058 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1059 handle_level_irq);
1394f032
BW		 1060#endif
1061
464abc5d
MH		 1062 /* if configured as edge, then will be changed to do_edge_IRQ */
1063 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1064 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1065 handle_level_irq);
2c4f829b 1066
a055b2b4 1067
1394f032
BW		 1068 bfin_write_IMASK(0);
1069 CSYNC();
1070 ilat = bfin_read_ILAT();
1071 CSYNC();
1072 bfin_write_ILAT(ilat);
1073 CSYNC();
1074
34e0fc89 1075 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1394f032
BW		 1076 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1077 * local_irq_enable()
1078 */
1079 program_IAR();
1080 /* Therefore it's better to setup IARs before interrupts enabled */
1081 search_IAR();
1082
1083 /* Enable interrupts IVG7-15 */
1084 irq_flags = irq_flags | IMASK_IVG15 |
1085 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
34e0fc89 1086 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1394f032 1087
fe9ec9b9 1088#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
56f5f590 1089 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
55546ac4
MH		 1090#if defined(CONFIG_BF52x)
1091 /* BF52x system reset does not properly reset SIC_IWR1 which
1092 * will screw up the bootrom as it relies on MDMA0/1 waking it
1093 * up from IDLE instructions. See this report for more info:
1094 * http://blackfin.uclinux.org/gf/tracker/4323
1095 */
1096 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1097#else
56f5f590 1098 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
55546ac4 1099#endif
fe9ec9b9 1100# ifdef CONFIG_BF54x
56f5f590 1101 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
fe9ec9b9
MH		 1102# endif
1103#else
56f5f590 1104 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
fe9ec9b9
MH		 1105#endif
1106
1394f032
BW		 1107 return 0;
1108}
1109
1110#ifdef CONFIG_DO_IRQ_L1
a055b2b4 1111__attribute__((l1_text))
1394f032 1112#endif
1394f032
BW		 1113void do_irq(int vec, struct pt_regs *fp)
1114{
1115 if (vec == EVT_IVTMR_P) {
1116 vec = IRQ_CORETMR;
1117 } else {
1118 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1119 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
2c4f829b 1120#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
24a07a12 1121 unsigned long sic_status[3];
1394f032 1122
4fb45241
MH		 1123 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1124 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
59003145 1125#ifdef CONFIG_BF54x
4fb45241 1126 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
59003145 1127#endif
1f83b8f1 1128 for (;; ivg++) {
24a07a12
RH		 1129 if (ivg >= ivg_stop) {
1130 atomic_inc(&num_spurious);
1131 return;
1132 }
34e0fc89 1133 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
24a07a12
RH		 1134 break;
1135 }
1136#else
1137 unsigned long sic_status;
464abc5d 1138
1394f032
BW		 1139 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1140
1141 for (;; ivg++) {
1142 if (ivg >= ivg_stop) {
1143 atomic_inc(&num_spurious);
1144 return;
1145 } else if (sic_status & ivg->isrflag)
1146 break;
1147 }
24a07a12 1148#endif
1394f032
BW		 1149 vec = ivg->irqno;
1150 }
1151 asm_do_IRQ(vec, fp);
1394f032 1152}
Linux 6.x block layer and io_uring tree(s)