Fix common misspellings
[linux-2.6-block.git] / arch / blackfin / mach-common / head.S
CommitLineData
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1/*
2 * Common Blackfin startup code
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
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6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/linkage.h>
10#include <linux/init.h>
11#include <asm/blackfin.h>
67618fd8 12#include <asm/thread_info.h>
09e1f70e 13#include <asm/trace.h>
6b3087c6 14#include <asm/asm-offsets.h>
09e1f70e 15
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16__INIT
17
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18ENTRY(__init_clear_bss)
19 r2 = r2 - r1;
20 cc = r2 == 0;
21 if cc jump .L_bss_done;
22 r2 >>= 2;
23 p1 = r1;
24 p2 = r2;
25 lsetup (1f, 1f) lc0 = p2;
261: [p1++] = r0;
27.L_bss_done:
28 rts;
29ENDPROC(__init_clear_bss)
30
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31ENTRY(__start)
32 /* R0: argument of command line string, passed from uboot, save it */
33 R7 = R0;
511cdcc5 34
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35 /* Enable Cycle Counter and Nesting Of Interrupts */
36#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
37 R0 = SYSCFG_SNEN;
38#else
39 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
40#endif
41 SYSCFG = R0;
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42
43 /* Optimization register tricks: keep a base value in the
44 * reserved P registers so we use the load/store with an
45 * offset syntax. R0 = [P5 + <constant>];
46 * P5 - core MMR base
47 * R6 - 0
48 */
49 r6 = 0;
50 p5.l = 0;
51 p5.h = hi(COREMMR_BASE);
52
53 /* Zero out registers required by Blackfin ABI */
54
55 /* Disable circular buffers */
56 L0 = r6;
57 L1 = r6;
58 L2 = r6;
59 L3 = r6;
60
61 /* Disable hardware loops in case we were started by 'go' */
62 LC0 = r6;
63 LC1 = r6;
17e89bcf 64
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65 /*
66 * Clear ITEST_COMMAND and DTEST_COMMAND registers,
67 * Leaving these as non-zero can confuse the emulator
68 */
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69 [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
70 [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
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71 CSYNC;
72
17e89bcf 73 trace_buffer_init(p0,r0);
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74
75 /* Turn off the icache */
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76 r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
77 BITCLR (r1, ENICPLB_P);
78 [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
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79 SSYNC;
80
81 /* Turn off the dcache */
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82 r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
83 BITCLR (r1, ENDCPLB_P);
84 [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
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85 SSYNC;
86
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87 /* in case of double faults, save a few things */
88 p0.l = _init_retx;
89 p0.h = _init_retx;
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90 R0 = RETX;
91 [P0] = R0;
92
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93#ifdef CONFIG_DEBUG_DOUBLEFAULT
94 /* Only save these if we are storing them,
95 * This happens here, since L1 gets clobbered
96 * below
97 */
6b3087c6 98 GET_PDA(p0, r0);
511cdcc5 99 r5 = [p0 + PDA_DF_RETX];
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100 p1.l = _init_saved_retx;
101 p1.h = _init_saved_retx;
511cdcc5 102 [p1] = r5;
0c7a6b21 103
511cdcc5 104 r5 = [p0 + PDA_DF_DCPLB];
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105 p1.l = _init_saved_dcplb_fault_addr;
106 p1.h = _init_saved_dcplb_fault_addr;
511cdcc5 107 [p1] = r5;
0c7a6b21 108
511cdcc5 109 r5 = [p0 + PDA_DF_ICPLB];
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110 p1.l = _init_saved_icplb_fault_addr;
111 p1.h = _init_saved_icplb_fault_addr;
511cdcc5 112 [p1] = r5;
0c7a6b21 113
511cdcc5 114 r5 = [p0 + PDA_DF_SEQSTAT];
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115 p1.l = _init_saved_seqstat;
116 p1.h = _init_saved_seqstat;
511cdcc5 117 [p1] = r5;
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118#endif
119
17e89bcf 120 /* Initialize stack pointer */
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121 sp.l = _init_thread_union + THREAD_SIZE;
122 sp.h = _init_thread_union + THREAD_SIZE;
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123 fp = sp;
124 usp = sp;
125
126#ifdef CONFIG_EARLY_PRINTK
127 call _init_early_exception_vectors;
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128 r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
129 sti r0;
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130#endif
131
511cdcc5 132 r0 = r6;
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133 /* Zero out all of the fun bss regions */
134#if L1_DATA_A_LENGTH > 0
135 r1.l = __sbss_l1;
136 r1.h = __sbss_l1;
137 r2.l = __ebss_l1;
138 r2.h = __ebss_l1;
139 call __init_clear_bss
140#endif
141#if L1_DATA_B_LENGTH > 0
142 r1.l = __sbss_b_l1;
143 r1.h = __sbss_b_l1;
144 r2.l = __ebss_b_l1;
145 r2.h = __ebss_b_l1;
146 call __init_clear_bss
147#endif
148#if L2_LENGTH > 0
149 r1.l = __sbss_l2;
150 r1.h = __sbss_l2;
151 r2.l = __ebss_l2;
152 r2.h = __ebss_l2;
153 call __init_clear_bss
154#endif
155 r1.l = ___bss_start;
156 r1.h = ___bss_start;
157 r2.l = ___bss_stop;
158 r2.h = ___bss_stop;
159 call __init_clear_bss
160
17e89bcf 161 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
5b04f271 162 call _bfin_relocate_l1_mem;
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163
164#ifdef CONFIG_ROMKERNEL
165 call _bfin_relocate_xip_data;
166#endif
167
17e89bcf 168#ifdef CONFIG_BFIN_KERNEL_CLOCK
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169 /* Only use on-chip scratch space for stack when absolutely required
170 * to avoid Anomaly 05000227 ... we know the init_clocks() func only
171 * uses L1 text and stack space and no other memory region.
172 */
173# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
174 sp.l = lo(KERNEL_CLOCK_STACK);
175 sp.h = hi(KERNEL_CLOCK_STACK);
73feb5c0 176 call _init_clocks;
25985edc 177 sp = usp; /* usp hasn't been touched, so restore from there */
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178#endif
179
180 /* This section keeps the processor in supervisor mode
181 * during kernel boot. Switches to user mode at end of boot.
182 * See page 3-9 of Hardware Reference manual for documentation.
183 */
184
185 /* EVT15 = _real_start */
186
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187 p1.l = _real_start;
188 p1.h = _real_start;
511cdcc5 189 [p5 + (EVT15 - COREMMR_BASE)] = p1;
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190 csync;
191
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192#ifdef CONFIG_EARLY_PRINTK
193 r0 = (EVT_IVG15 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU) (z);
194#else
c2414bd0 195 r0 = EVT_IVG15 (z);
837ec2d5 196#endif
c2414bd0 197 sti r0;
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198
199 raise 15;
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200#ifdef CONFIG_EARLY_PRINTK
201 p0.l = _early_trap;
202 p0.h = _early_trap;
203#else
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204 p0.l = .LWAIT_HERE;
205 p0.h = .LWAIT_HERE;
837ec2d5 206#endif
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207 reti = p0;
208#if ANOMALY_05000281
209 nop; nop; nop;
210#endif
211 rti;
212
213.LWAIT_HERE:
214 jump .LWAIT_HERE;
215ENDPROC(__start)
216
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217/* A little BF561 glue ... */
218#ifndef WDOG_CTL
219# define WDOG_CTL WDOGA_CTL
220#endif
221
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222ENTRY(_real_start)
223 /* Enable nested interrupts */
224 [--sp] = reti;
225
226 /* watchdog off for now */
227 p0.l = lo(WDOG_CTL);
228 p0.h = hi(WDOG_CTL);
229 r0 = 0xAD6(z);
230 w[p0] = r0;
231 ssync;
232
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233 /* Pass the u-boot arguments to the global value command line */
234 R0 = R7;
235 call _cmdline_init;
236
aad16f32 237 sp += -12 + 4; /* +4 is for reti loading above */
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238 call _init_pda
239 sp += 12;
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240 jump.l _start_kernel;
241ENDPROC(_real_start)
242
243__FINIT