[linux-2.6-block.git] / arch / blackfin / mach-common / head.S

/*
 * Common Blackfin startup code
 *
 * Copyright 2004-2008 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/thread_info.h>
#include <asm/trace.h>
#include <asm/asm-offsets.h>

__INIT

ENTRY(__init_clear_bss)
	r2 = r2 - r1;
	cc = r2 == 0;
	if cc jump .L_bss_done;
	r2 >>= 2;
	p1 = r1;
	p2 = r2;
	lsetup (1f, 1f) lc0 = p2;
1:	[p1++] = r0;
.L_bss_done:
	rts;
ENDPROC(__init_clear_bss)

ENTRY(__start)
	/* R0: argument of command line string, passed from uboot, save it */
	R7 = R0;

	/* Enable Cycle Counter and Nesting Of Interrupts */
#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
	R0 = SYSCFG_SNEN;
#else
	R0 = SYSCFG_SNEN | SYSCFG_CCEN;
#endif
	SYSCFG = R0;

	/* Optimization register tricks: keep a base value in the
	 * reserved P registers so we use the load/store with an
	 * offset syntax.  R0 = [P5 + <constant>];
	 *   P5 - core MMR base
	 *   R6 - 0
	 */
	r6 = 0;
	p5.l = 0;
	p5.h = hi(COREMMR_BASE);

	/* Zero out registers required by Blackfin ABI */

	/* Disable circular buffers */
	L0 = r6;
	L1 = r6;
	L2 = r6;
	L3 = r6;

	/* Disable hardware loops in case we were started by 'go' */
	LC0 = r6;
	LC1 = r6;

	/*
	 * Clear ITEST_COMMAND and DTEST_COMMAND registers,
	 * Leaving these as non-zero can confuse the emulator
	 */
	[p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
	[p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
	CSYNC;

	trace_buffer_init(p0,r0);

	/* Turn off the icache */
	r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
	BITCLR (r1, ENICPLB_P);
	[p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
	SSYNC;

	/* Turn off the dcache */
	r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
	BITCLR (r1, ENDCPLB_P);
	[p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
	SSYNC;

	/* in case of double faults, save a few things */
	p1.l = _initial_pda;
	p1.h = _initial_pda;
	r4 = RETX;
#ifdef CONFIG_DEBUG_DOUBLEFAULT
	/* Only save these if we are storing them,
	 * This happens here, since L1 gets clobbered
	 * below
	 */
	GET_PDA(p0, r0);
	r0 = [p0 + PDA_DF_RETX];
	r1 = [p0 + PDA_DF_DCPLB];
	r2 = [p0 + PDA_DF_ICPLB];
	r3 = [p0 + PDA_DF_SEQSTAT];
	[p1 + PDA_INIT_DF_RETX] = r0;
	[p1 + PDA_INIT_DF_DCPLB] = r1;
	[p1 + PDA_INIT_DF_ICPLB] = r2;
	[p1 + PDA_INIT_DF_SEQSTAT] = r3;
#endif
	[p1 + PDA_INIT_RETX] = r4;

	/* Initialize stack pointer */
	sp.l = _init_thread_union + THREAD_SIZE;
	sp.h = _init_thread_union + THREAD_SIZE;
	fp = sp;
	usp = sp;

#ifdef CONFIG_EARLY_PRINTK
	call _init_early_exception_vectors;
	r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
	sti r0;
#endif

	r0 = r6;
	/* Zero out all of the fun bss regions */
#if L1_DATA_A_LENGTH > 0
	r1.l = __sbss_l1;
	r1.h = __sbss_l1;
	r2.l = __ebss_l1;
	r2.h = __ebss_l1;
	call __init_clear_bss
#endif
#if L1_DATA_B_LENGTH > 0
	r1.l = __sbss_b_l1;
	r1.h = __sbss_b_l1;
	r2.l = __ebss_b_l1;
	r2.h = __ebss_b_l1;
	call __init_clear_bss
#endif
#if L2_LENGTH > 0
	r1.l = __sbss_l2;
	r1.h = __sbss_l2;
	r2.l = __ebss_l2;
	r2.h = __ebss_l2;
	call __init_clear_bss
#endif
	r1.l = ___bss_start;
	r1.h = ___bss_start;
	r2.l = ___bss_stop;
	r2.h = ___bss_stop;
	call __init_clear_bss

	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
	call _bfin_relocate_l1_mem;

#ifdef CONFIG_ROMKERNEL
	call _bfin_relocate_xip_data;
#endif

#ifdef CONFIG_BFIN_KERNEL_CLOCK
	/* Only use on-chip scratch space for stack when absolutely required
	 * to avoid Anomaly 05000227 ... we know the init_clocks() func only
	 * uses L1 text and stack space and no other memory region.
	 */
# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
	sp.l = lo(KERNEL_CLOCK_STACK);
	sp.h = hi(KERNEL_CLOCK_STACK);
	call _init_clocks;
	sp = usp;	/* usp hasn't been touched, so restore from there */
#endif

	/* This section keeps the processor in supervisor mode
	 * during kernel boot.  Switches to user mode at end of boot.
	 * See page 3-9 of Hardware Reference manual for documentation.
	 */

	/* EVT15 = _real_start */

	p1.l = _real_start;
	p1.h = _real_start;
	[p5 + (EVT15 - COREMMR_BASE)] = p1;
	csync;

#ifdef CONFIG_EARLY_PRINTK
	r0 = (EVT_IVG15 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU) (z);
#else
	r0 = EVT_IVG15 (z);
#endif
	sti r0;

	raise 15;
#ifdef CONFIG_EARLY_PRINTK
	p0.l = _early_trap;
	p0.h = _early_trap;
#else
	p0.l = .LWAIT_HERE;
	p0.h = .LWAIT_HERE;
#endif
	reti = p0;
#if ANOMALY_05000281
	nop; nop; nop;
#endif
	rti;

.LWAIT_HERE:
	jump .LWAIT_HERE;
ENDPROC(__start)

/* A little BF561 glue ... */
#ifndef WDOG_CTL
# define WDOG_CTL WDOGA_CTL
#endif

ENTRY(_real_start)
	/* Enable nested interrupts */
	[--sp] = reti;
	/* watchdog off for now */
	p0.l = lo(WDOG_CTL);
	p0.h = hi(WDOG_CTL);
	r0 = 0xAD6(z);
	w[p0] = r0;
	ssync;
	/* Pass the u-boot arguments to the global value command line */
	R0 = R7;
	call _cmdline_init;

	sp += -12 + 4; /* +4 is for reti loading above */
	call _init_pda
	sp += 12;
	jump.l _start_kernel;
ENDPROC(_real_start)

__FINIT
Commit	Line	Data
09e1f70e MF	1	/*
	2	* Common Blackfin startup code
	3	*
	4	* Copyright 2004-2008 Analog Devices Inc.
	5	*
09e1f70e MF	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#include <linux/linkage.h>
	10	#include <linux/init.h>
	11	#include <asm/blackfin.h>
67618fd8	12	#include <asm/thread_info.h>
09e1f70e	13	#include <asm/trace.h>
6b3087c6	14	#include <asm/asm-offsets.h>
09e1f70e	15
17e89bcf MF	16	__INIT
17e89bcf MF	17
9960aa6a GY	18	ENTRY(__init_clear_bss)
	19	r2 = r2 - r1;
	20	cc = r2 == 0;
	21	if cc jump .L_bss_done;
	22	r2 >>= 2;
	23	p1 = r1;
	24	p2 = r2;
	25	lsetup (1f, 1f) lc0 = p2;
	26	1: [p1++] = r0;
	27	.L_bss_done:
	28	rts;
	29	ENDPROC(__init_clear_bss)
	30
17e89bcf MF	31	ENTRY(__start)
	32	/* R0: argument of command line string, passed from uboot, save it */
	33	R7 = R0;
511cdcc5	34
17e89bcf MF	35	/* Enable Cycle Counter and Nesting Of Interrupts */
	36	#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
	37	R0 = SYSCFG_SNEN;
	38	#else
	39	R0 = SYSCFG_SNEN \| SYSCFG_CCEN;
	40	#endif
	41	SYSCFG = R0;
511cdcc5 MF	42
	43	/* Optimization register tricks: keep a base value in the
	44	* reserved P registers so we use the load/store with an
	45	* offset syntax. R0 = [P5 + <constant>];
	46	* P5 - core MMR base
	47	* R6 - 0
	48	*/
	49	r6 = 0;
	50	p5.l = 0;
	51	p5.h = hi(COREMMR_BASE);
	52
	53	/* Zero out registers required by Blackfin ABI */
	54
	55	/* Disable circular buffers */
	56	L0 = r6;
	57	L1 = r6;
	58	L2 = r6;
	59	L3 = r6;
	60
	61	/* Disable hardware loops in case we were started by 'go' */
	62	LC0 = r6;
	63	LC1 = r6;
17e89bcf	64
9df10281 RG	65	/*
	66	* Clear ITEST_COMMAND and DTEST_COMMAND registers,
	67	* Leaving these as non-zero can confuse the emulator
	68	*/
511cdcc5 MF	69	[p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
511cdcc5 MF	70	[p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
9df10281 RG	71	CSYNC;
9df10281 RG	72
17e89bcf	73	trace_buffer_init(p0,r0);
17e89bcf MF	74
17e89bcf MF	75	/* Turn off the icache */
511cdcc5 MF	76	r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
	77	BITCLR (r1, ENICPLB_P);
	78	[p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
17e89bcf MF	79	SSYNC;
	80
	81	/* Turn off the dcache */
511cdcc5 MF	82	r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
	83	BITCLR (r1, ENDCPLB_P);
	84	[p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
17e89bcf MF	85	SSYNC;
17e89bcf MF	86
0c7a6b21	87	/* in case of double faults, save a few things */
fb1d9be5 MF	88	p1.l = _initial_pda;
	89	p1.h = _initial_pda;
	90	r4 = RETX;
0c7a6b21 RG	91	#ifdef CONFIG_DEBUG_DOUBLEFAULT
	92	/* Only save these if we are storing them,
	93	* This happens here, since L1 gets clobbered
	94	* below
	95	*/
6b3087c6	96	GET_PDA(p0, r0);
fb1d9be5 MF	97	r0 = [p0 + PDA_DF_RETX];
	98	r1 = [p0 + PDA_DF_DCPLB];
	99	r2 = [p0 + PDA_DF_ICPLB];
	100	r3 = [p0 + PDA_DF_SEQSTAT];
	101	[p1 + PDA_INIT_DF_RETX] = r0;
	102	[p1 + PDA_INIT_DF_DCPLB] = r1;
	103	[p1 + PDA_INIT_DF_ICPLB] = r2;
	104	[p1 + PDA_INIT_DF_SEQSTAT] = r3;
0c7a6b21	105	#endif
fb1d9be5	106	[p1 + PDA_INIT_RETX] = r4;
0c7a6b21	107
17e89bcf	108	/* Initialize stack pointer */
aad16f32 BS	109	sp.l = _init_thread_union + THREAD_SIZE;
aad16f32 BS	110	sp.h = _init_thread_union + THREAD_SIZE;
17e89bcf MF	111	fp = sp;
	112	usp = sp;
	113
	114	#ifdef CONFIG_EARLY_PRINTK
	115	call _init_early_exception_vectors;
837ec2d5 RG	116	r0 = (EVT_IVHW \| EVT_IRPTEN \| EVT_EVX \| EVT_NMI \| EVT_RST \| EVT_EMU);
837ec2d5 RG	117	sti r0;
17e89bcf MF	118	#endif
17e89bcf MF	119
511cdcc5	120	r0 = r6;
9960aa6a GY	121	/* Zero out all of the fun bss regions */
	122	#if L1_DATA_A_LENGTH > 0
	123	r1.l = __sbss_l1;
	124	r1.h = __sbss_l1;
	125	r2.l = __ebss_l1;
	126	r2.h = __ebss_l1;
	127	call __init_clear_bss
	128	#endif
	129	#if L1_DATA_B_LENGTH > 0
	130	r1.l = __sbss_b_l1;
	131	r1.h = __sbss_b_l1;
	132	r2.l = __ebss_b_l1;
	133	r2.h = __ebss_b_l1;
	134	call __init_clear_bss
	135	#endif
	136	#if L2_LENGTH > 0
	137	r1.l = __sbss_l2;
	138	r1.h = __sbss_l2;
	139	r2.l = __ebss_l2;
	140	r2.h = __ebss_l2;
	141	call __init_clear_bss
	142	#endif
	143	r1.l = ___bss_start;
	144	r1.h = ___bss_start;
	145	r2.l = ___bss_stop;
	146	r2.h = ___bss_stop;
	147	call __init_clear_bss
	148
17e89bcf	149	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
5b04f271	150	call _bfin_relocate_l1_mem;
d86bfb16 BS	151
	152	#ifdef CONFIG_ROMKERNEL
	153	call _bfin_relocate_xip_data;
	154	#endif
	155
17e89bcf	156	#ifdef CONFIG_BFIN_KERNEL_CLOCK
729a3fa7 MF	157	/* Only use on-chip scratch space for stack when absolutely required
	158	* to avoid Anomaly 05000227 ... we know the init_clocks() func only
	159	* uses L1 text and stack space and no other memory region.
	160	*/
	161	# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
	162	sp.l = lo(KERNEL_CLOCK_STACK);
	163	sp.h = hi(KERNEL_CLOCK_STACK);
73feb5c0	164	call _init_clocks;
25985edc	165	sp = usp; /* usp hasn't been touched, so restore from there */
17e89bcf MF	166	#endif
	167
	168	/* This section keeps the processor in supervisor mode
	169	* during kernel boot. Switches to user mode at end of boot.
	170	* See page 3-9 of Hardware Reference manual for documentation.
	171	*/
	172
	173	/* EVT15 = _real_start */
	174
17e89bcf MF	175	p1.l = _real_start;
17e89bcf MF	176	p1.h = _real_start;
511cdcc5	177	[p5 + (EVT15 - COREMMR_BASE)] = p1;
17e89bcf MF	178	csync;
17e89bcf MF	179
837ec2d5 RG	180	#ifdef CONFIG_EARLY_PRINTK
	181	r0 = (EVT_IVG15 \| EVT_IVHW \| EVT_IRPTEN \| EVT_EVX \| EVT_NMI \| EVT_RST \| EVT_EMU) (z);
	182	#else
c2414bd0	183	r0 = EVT_IVG15 (z);
837ec2d5	184	#endif
c2414bd0	185	sti r0;
17e89bcf MF	186
17e89bcf MF	187	raise 15;
837ec2d5 RG	188	#ifdef CONFIG_EARLY_PRINTK
	189	p0.l = _early_trap;
	190	p0.h = _early_trap;
	191	#else
17e89bcf MF	192	p0.l = .LWAIT_HERE;
17e89bcf MF	193	p0.h = .LWAIT_HERE;
837ec2d5	194	#endif
17e89bcf MF	195	reti = p0;
	196	#if ANOMALY_05000281
	197	nop; nop; nop;
	198	#endif
	199	rti;
	200
	201	.LWAIT_HERE:
	202	jump .LWAIT_HERE;
	203	ENDPROC(__start)
	204
09e1f70e MF	205	/* A little BF561 glue ... */
	206	#ifndef WDOG_CTL
	207	# define WDOG_CTL WDOGA_CTL
	208	#endif
	209
09e1f70e MF	210	ENTRY(_real_start)
	211	/* Enable nested interrupts */
	212	[--sp] = reti;
09e1f70e MF	213	/* watchdog off for now */
	214	p0.l = lo(WDOG_CTL);
	215	p0.h = hi(WDOG_CTL);
	216	r0 = 0xAD6(z);
	217	w[p0] = r0;
	218	ssync;
09e1f70e MF	219	/* Pass the u-boot arguments to the global value command line */
	220	R0 = R7;
	221	call _cmdline_init;
	222
aad16f32	223	sp += -12 + 4; /* +4 is for reti loading above */
6b3087c6 GY	224	call _init_pda
6b3087c6 GY	225	sp += 12;
09e1f70e MF	226	jump.l _start_kernel;
	227	ENDPROC(_real_start)
	228
	229	__FINIT