projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 22a82628 SZ |
1 | /* |
| 2 | * the simple DMA Implementation for Blackfin | |
| 3 | * | |
| 4 | * Copyright 2007-2009 Analog Devices Inc. | |
| 5 | * | |
| 6 | * Licensed under the GPL-2 or later. | |
| 7 | */ | |
| 8 | ||
| 9 | #include <linux/module.h> | |
| 10 | ||
| 11 | #include <asm/blackfin.h> | |
| 12 | #include <asm/dma.h> | |
| 13 | ||
| 14 | struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { | |
| 15 | (struct dma_register *) DMA0_NEXT_DESC_PTR, | |
| 16 | (struct dma_register *) DMA1_NEXT_DESC_PTR, | |
| 17 | (struct dma_register *) DMA2_NEXT_DESC_PTR, | |
| 18 | (struct dma_register *) DMA3_NEXT_DESC_PTR, | |
| 19 | (struct dma_register *) DMA4_NEXT_DESC_PTR, | |
| 20 | (struct dma_register *) DMA5_NEXT_DESC_PTR, | |
| 21 | (struct dma_register *) DMA6_NEXT_DESC_PTR, | |
| 22 | (struct dma_register *) DMA7_NEXT_DESC_PTR, | |
| 23 | (struct dma_register *) DMA8_NEXT_DESC_PTR, | |
| 24 | (struct dma_register *) DMA9_NEXT_DESC_PTR, | |
| 25 | (struct dma_register *) DMA10_NEXT_DESC_PTR, | |
| 26 | (struct dma_register *) DMA11_NEXT_DESC_PTR, | |
| 27 | (struct dma_register *) DMA12_NEXT_DESC_PTR, | |
| 28 | (struct dma_register *) DMA13_NEXT_DESC_PTR, | |
| 29 | (struct dma_register *) DMA14_NEXT_DESC_PTR, | |
| 30 | (struct dma_register *) DMA15_NEXT_DESC_PTR, | |
| 31 | (struct dma_register *) DMA16_NEXT_DESC_PTR, | |
| 32 | (struct dma_register *) DMA17_NEXT_DESC_PTR, | |
| 33 | (struct dma_register *) DMA18_NEXT_DESC_PTR, | |
| 34 | (struct dma_register *) DMA19_NEXT_DESC_PTR, | |
| 35 | (struct dma_register *) DMA20_NEXT_DESC_PTR, | |
| 36 | (struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR, | |
| 37 | (struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR, | |
| 38 | (struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR, | |
| 39 | (struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR, | |
| 40 | (struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR, | |
| 41 | (struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR, | |
| 42 | (struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR, | |
| 43 | (struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR, | |
| 44 | (struct dma_register *) DMA29_NEXT_DESC_PTR, | |
| 45 | (struct dma_register *) DMA30_NEXT_DESC_PTR, | |
| 46 | (struct dma_register *) DMA31_NEXT_DESC_PTR, | |
| 47 | (struct dma_register *) DMA32_NEXT_DESC_PTR, | |
| 48 | (struct dma_register *) DMA33_NEXT_DESC_PTR, | |
| 49 | (struct dma_register *) DMA34_NEXT_DESC_PTR, | |
| 50 | (struct dma_register *) DMA35_NEXT_DESC_PTR, | |
| 51 | (struct dma_register *) DMA36_NEXT_DESC_PTR, | |
| 52 | (struct dma_register *) DMA37_NEXT_DESC_PTR, | |
| 53 | (struct dma_register *) DMA38_NEXT_DESC_PTR, | |
| 54 | (struct dma_register *) DMA39_NEXT_DESC_PTR, | |
| 55 | (struct dma_register *) DMA40_NEXT_DESC_PTR, | |
| 56 | (struct dma_register *) DMA41_NEXT_DESC_PTR, | |
| 57 | (struct dma_register *) DMA42_NEXT_DESC_PTR, | |
| 58 | (struct dma_register *) DMA43_NEXT_DESC_PTR, | |
| 59 | (struct dma_register *) DMA44_NEXT_DESC_PTR, | |
| 60 | (struct dma_register *) DMA45_NEXT_DESC_PTR, | |
| 61 | (struct dma_register *) DMA46_NEXT_DESC_PTR, | |
| 62 | }; | |
| 63 | EXPORT_SYMBOL(dma_io_base_addr); | |
| 64 | ||
| 65 | int channel2irq(unsigned int channel) | |
| 66 | { | |
| 67 | int ret_irq = -1; | |
| 68 | ||
| 69 | switch (channel) { | |
| 70 | case CH_SPORT0_RX: | |
| 71 | ret_irq = IRQ_SPORT0_RX; | |
| 72 | break; | |
| 73 | case CH_SPORT0_TX: | |
| 74 | ret_irq = IRQ_SPORT0_TX; | |
| 75 | break; | |
| 76 | case CH_SPORT1_RX: | |
| 77 | ret_irq = IRQ_SPORT1_RX; | |
| 78 | break; | |
| 79 | case CH_SPORT1_TX: | |
| 80 | ret_irq = IRQ_SPORT1_TX; | |
| 81 | break; | |
| 82 | case CH_SPORT2_RX: | |
| 83 | ret_irq = IRQ_SPORT2_RX; | |
| 84 | break; | |
| 85 | case CH_SPORT2_TX: | |
| 86 | ret_irq = IRQ_SPORT2_TX; | |
| 87 | break; | |
| 88 | case CH_SPI0_TX: | |
| 89 | ret_irq = IRQ_SPI0_TX; | |
| 90 | break; | |
| 91 | case CH_SPI0_RX: | |
| 92 | ret_irq = IRQ_SPI0_RX; | |
| 93 | break; | |
| 94 | case CH_SPI1_TX: | |
| 95 | ret_irq = IRQ_SPI1_TX; | |
| 96 | break; | |
| 97 | case CH_SPI1_RX: | |
| 98 | ret_irq = IRQ_SPI1_RX; | |
| 99 | break; | |
| 100 | case CH_RSI: | |
| 101 | ret_irq = IRQ_RSI; | |
| 102 | break; | |
| 103 | case CH_SDU: | |
| 104 | ret_irq = IRQ_SDU; | |
| 105 | break; | |
| 106 | case CH_LP0: | |
| 107 | ret_irq = IRQ_LP0; | |
| 108 | break; | |
| 109 | case CH_LP1: | |
| 110 | ret_irq = IRQ_LP1; | |
| 111 | break; | |
| 112 | case CH_LP2: | |
| 113 | ret_irq = IRQ_LP2; | |
| 114 | break; | |
| 115 | case CH_LP3: | |
| 116 | ret_irq = IRQ_LP3; | |
| 117 | break; | |
| 118 | case CH_UART0_RX: | |
| 119 | ret_irq = IRQ_UART0_RX; | |
| 120 | break; | |
| 121 | case CH_UART0_TX: | |
| 122 | ret_irq = IRQ_UART0_TX; | |
| 123 | break; | |
| 124 | case CH_UART1_RX: | |
| 125 | ret_irq = IRQ_UART1_RX; | |
| 126 | break; | |
| 127 | case CH_UART1_TX: | |
| 128 | ret_irq = IRQ_UART1_TX; | |
| 129 | break; | |
| 130 | case CH_EPPI0_CH0: | |
| 131 | ret_irq = IRQ_EPPI0_CH0; | |
| 132 | break; | |
| 133 | case CH_EPPI0_CH1: | |
| 134 | ret_irq = IRQ_EPPI0_CH1; | |
| 135 | break; | |
| 136 | case CH_EPPI1_CH0: | |
| 137 | ret_irq = IRQ_EPPI1_CH0; | |
| 138 | break; | |
| 139 | case CH_EPPI1_CH1: | |
| 140 | ret_irq = IRQ_EPPI1_CH1; | |
| 141 | break; | |
| 142 | case CH_EPPI2_CH0: | |
| 143 | ret_irq = IRQ_EPPI2_CH0; | |
| 144 | break; | |
| 145 | case CH_EPPI2_CH1: | |
| 146 | ret_irq = IRQ_EPPI2_CH1; | |
| 147 | break; | |
| 148 | case CH_PIXC_CH0: | |
| 149 | ret_irq = IRQ_PIXC_CH0; | |
| 150 | break; | |
| 151 | case CH_PIXC_CH1: | |
| 152 | ret_irq = IRQ_PIXC_CH1; | |
| 153 | break; | |
| 154 | case CH_PIXC_CH2: | |
| 155 | ret_irq = IRQ_PIXC_CH2; | |
| 156 | break; | |
| 157 | case CH_PVP_CPDOB: | |
| 158 | ret_irq = IRQ_PVP_CPDOB; | |
| 159 | break; | |
| 160 | case CH_PVP_CPDOC: | |
| 161 | ret_irq = IRQ_PVP_CPDOC; | |
| 162 | break; | |
| 163 | case CH_PVP_CPSTAT: | |
| 164 | ret_irq = IRQ_PVP_CPSTAT; | |
| 165 | break; | |
| 166 | case CH_PVP_CPCI: | |
| 167 | ret_irq = IRQ_PVP_CPCI; | |
| 168 | break; | |
| 169 | case CH_PVP_MPDO: | |
| 170 | ret_irq = IRQ_PVP_MPDO; | |
| 171 | break; | |
| 172 | case CH_PVP_MPDI: | |
| 173 | ret_irq = IRQ_PVP_MPDI; | |
| 174 | break; | |
| 175 | case CH_PVP_MPSTAT: | |
| 176 | ret_irq = IRQ_PVP_MPSTAT; | |
| 177 | break; | |
| 178 | case CH_PVP_MPCI: | |
| 179 | ret_irq = IRQ_PVP_MPCI; | |
| 180 | break; | |
| 181 | case CH_PVP_CPDOA: | |
| 182 | ret_irq = IRQ_PVP_CPDOA; | |
| 183 | break; | |
| 184 | case CH_MEM_STREAM0_SRC: | |
| 185 | case CH_MEM_STREAM0_DEST: | |
| 186 | ret_irq = IRQ_MDMAS0; | |
| 187 | break; | |
| 188 | case CH_MEM_STREAM1_SRC: | |
| 189 | case CH_MEM_STREAM1_DEST: | |
| 190 | ret_irq = IRQ_MDMAS1; | |
| 191 | break; | |
| 192 | case CH_MEM_STREAM2_SRC: | |
| 193 | case CH_MEM_STREAM2_DEST: | |
| 194 | ret_irq = IRQ_MDMAS2; | |
| 195 | break; | |
| 196 | case CH_MEM_STREAM3_SRC: | |
| 197 | case CH_MEM_STREAM3_DEST: | |
| 198 | ret_irq = IRQ_MDMAS3; | |
| 199 | break; | |
| 200 | } | |
| 201 | return ret_irq; | |
| 202 | } |