[linux-2.6-block.git] / arch / blackfin / mach-bf548 / Kconfig

if (BF54x)

source "arch/blackfin/mach-bf548/boards/Kconfig"

menu "BF548 Specific Configuration"

config DEB_DMA_URGENT
	bool "DMA has priority over core for ext. accesses"
	depends on BF54x
	default y
	help
	  Treat any DEB1, DEB2 and DEB3 request as Urgent

config BF548_ATAPI_ALTERNATIVE_PORT
	bool "BF548 ATAPI alternative port via GPIO"
	help
	  BF548 ATAPI data and address PINs can be routed through
	  async address or GPIO port F and G. Select y to route it
	  to GPIO.

comment "Interrupt Priority Assignment"
menu "Priority"

config IRQ_PLL_WAKEUP
	int "IRQ_PLL_WAKEUP"
	default 7
config IRQ_DMAC0_ERR
	int "IRQ_DMAC0_ERR"
	default 7
config IRQ_EPPI0_ERR
	int "IRQ_EPPI0_ERR"
	default 7
config IRQ_SPORT0_ERR
	int "IRQ_SPORT0_ERR"
	default 7
config IRQ_SPORT1_ERR
	int "IRQ_SPORT1_ERR"
	default 7
config IRQ_SPI0_ERR
	int "IRQ_SPI0_ERR"
	default 7
config IRQ_UART0_ERR
	int "IRQ_UART0_ERR"
	default 7
config IRQ_RTC
	int "IRQ_RTC"
	default 8
config IRQ_EPPI0
	int "IRQ_EPPI0"
	default 8
config IRQ_SPORT0_RX
	int "IRQ_SPORT0_RX"
	default 9
config IRQ_SPORT0_TX
	int "IRQ_SPORT0_TX"
	default 9
config IRQ_SPORT1_RX
	int "IRQ_SPORT1_RX"
	default 9
config IRQ_SPORT1_TX
	int "IRQ_SPORT1_TX"
	default 9
config IRQ_SPI0
	int "IRQ_SPI0"
	default 10
config IRQ_UART0_RX
	int "IRQ_UART0_RX"
	default 10
config IRQ_UART0_TX
	int "IRQ_UART0_TX"
	default 10
config IRQ_TIMER8
	int "IRQ_TIMER8"
	default 11
config IRQ_TIMER9
	int "IRQ_TIMER9"
	default 11
config IRQ_TIMER10
	int "IRQ_TIMER10"
	default 11
config IRQ_PINT0
	int "IRQ_PINT0"
	default 12
config IRQ_PINT1
	int "IRQ_PINT0"
	default 12
config IRQ_MDMAS0
	int "IRQ_MDMAS0"
	default 13
config IRQ_MDMAS1
	int "IRQ_DMDMAS1"
	default 13
config IRQ_WATCHDOG
	int "IRQ_WATCHDOG"
	default 13
config IRQ_DMAC1_ERR
	int "IRQ_DMAC1_ERR"
	default 7
config IRQ_SPORT2_ERR
	int "IRQ_SPORT2_ERR"
	default 7
config IRQ_SPORT3_ERR
	int "IRQ_SPORT3_ERR"
	default 7
config IRQ_MXVR_DATA
	int "IRQ MXVR Data"
	default 7
config IRQ_SPI1_ERR
	int "IRQ_SPI1_ERR"
	default 7
config IRQ_SPI2_ERR
	int "IRQ_SPI2_ERR"
	default 7
config IRQ_UART1_ERR
	int "IRQ_UART1_ERR"
	default 7
config IRQ_UART2_ERR
	int "IRQ_UART2_ERR"
	default 7
config IRQ_CAN0_ERR
	int "IRQ_CAN0_ERR"
	default 7
config IRQ_SPORT2_RX
	int "IRQ_SPORT2_RX"
	default 9
config IRQ_SPORT2_TX
	int "IRQ_SPORT2_TX"
	default 9
config IRQ_SPORT3_RX
	int "IRQ_SPORT3_RX"
	default 9
config IRQ_SPORT3_TX
	int "IRQ_SPORT3_TX"
	default 9
config IRQ_EPPI1
	int "IRQ_EPPI1"
	default 9
config IRQ_EPPI2
	int "IRQ_EPPI2"
	default 9
config IRQ_SPI1
	int "IRQ_SPI1"
	default 10
config IRQ_SPI2
	int "IRQ_SPI2"
	default 10
config IRQ_UART1_RX
	int "IRQ_UART1_RX"
	default 10
config IRQ_UART1_TX
	int "IRQ_UART1_TX"
	default 10
config IRQ_ATAPI_RX
	int "IRQ_ATAPI_RX"
	default 10
config IRQ_ATAPI_TX
	int "IRQ_ATAPI_TX"
	default 10
config IRQ_TWI0
	int "IRQ_TWI0"
	default 11
config IRQ_TWI1
	int "IRQ_TWI1"
	default 11
config IRQ_CAN0_RX
	int "IRQ_CAN_RX"
	default 11
config IRQ_CAN0_TX
	int "IRQ_CAN_TX"
	default 11
config IRQ_MDMAS2
	int "IRQ_MDMAS2"
	default 13
config IRQ_MDMAS3
	int "IRQ_DMMAS3"
	default 13
config IRQ_MXVR_ERR
	int "IRQ_MXVR_ERR"
	default 11
config IRQ_MXVR_MSG
	int "IRQ_MXVR_MSG"
	default 11
config IRQ_MXVR_PKT
	int "IRQ_MXVR_PKT"
	default 11
config IRQ_EPPI1_ERR
	int "IRQ_EPPI1_ERR"
	default 7
config IRQ_EPPI2_ERR
	int "IRQ_EPPI2_ERR"
	default 7
config IRQ_UART3_ERR
	int "IRQ_UART3_ERR"
	default 7
config IRQ_HOST_ERR
	int "IRQ_HOST_ERR"
	default 7
config IRQ_PIXC_ERR
	int "IRQ_PIXC_ERR"
	default 7
config IRQ_NFC_ERR
	int "IRQ_NFC_ERR"
	default 7
config IRQ_ATAPI_ERR
	int "IRQ_ATAPI_ERR"
	default 7
config IRQ_CAN1_ERR
	int "IRQ_CAN1_ERR"
	default 7
config IRQ_HS_DMA_ERR
	int "IRQ Handshake DMA Status"
	default 7
config IRQ_PIXC_IN0
	int "IRQ PIXC IN0"
	default 8
config IRQ_PIXC_IN1
	int "IRQ PIXC IN1"
	default 8
config IRQ_PIXC_OUT
	int "IRQ PIXC OUT"
	default 8
config IRQ_SDH
	int "IRQ SDH"
	default 8
config IRQ_CNT
	int "IRQ CNT"
	default 8
config IRQ_KEY
	int "IRQ KEY"
	default 8
config IRQ_CAN1_RX
	int "IRQ CAN1 RX"
	default 11
config IRQ_CAN1_TX
	int "IRQ_CAN1_TX"
	default 11
config IRQ_SDH_MASK0
	int "IRQ_SDH_MASK0"
	default 11
config IRQ_SDH_MASK1
	int "IRQ_SDH_MASK1"
	default 11
config IRQ_USB_INT0
	int "IRQ USB INT0"
	default 11
config IRQ_USB_INT1
	int "IRQ USB INT1"
	default 11
config IRQ_USB_INT2
	int "IRQ USB INT2"
	default 11
config IRQ_USB_DMA
	int "IRQ USB DMA"
	default 11
config IRQ_OTPSEC
	int "IRQ OPTSEC"
	default 11
config IRQ_TIMER0
	int "IRQ_TIMER0"
	default 8
config IRQ_TIMER1
	int "IRQ_TIMER1"
	default 11
config IRQ_TIMER2
	int "IRQ_TIMER2"
	default 11
config IRQ_TIMER3
	int "IRQ_TIMER3"
	default 11
config IRQ_TIMER4
	int "IRQ_TIMER4"
	default 11
config IRQ_TIMER5
	int "IRQ_TIMER5"
	default 11
config IRQ_TIMER6
	int "IRQ_TIMER6"
	default 11
config IRQ_TIMER7
	int "IRQ_TIMER7"
	default 11
config IRQ_PINT2
	int "IRQ_PIN2"
	default 11
config IRQ_PINT3
	int "IRQ_PIN3"
	default 11

	help
	  Enter the priority numbers between 7-13 ONLY.  Others are Reserved.
	  This applies to all the above.  It is not recommended to assign the
	  highest priority number 7 to UART or any other device.

endmenu

comment "Pin Interrupt to Port Assignment"
menu "Assignment"

config PINTx_REASSIGN
	bool "Reprogram PINT Assignment"
	default y
	help
	  The interrupt assignment registers controls the pin-to-interrupt
	  assignment in a byte-wide manner. Each option allows you to select
	  a set of pins (High/Low Byte) of an specific Port being mapped
	  to one of the four PIN Interrupts IRQ_PINTx.

	  You shouldn't change any of these unless you know exactly what you're doing.
	  Please consult the Blackfin BF54x Processor Hardware Reference Manual.

config PINT0_ASSIGN
	hex "PINT0_ASSIGN"
	depends on PINTx_REASSIGN
	default 0x00000101
config PINT1_ASSIGN
	hex "PINT1_ASSIGN"
	depends on PINTx_REASSIGN
	default 0x01010000
config PINT2_ASSIGN
	hex "PINT2_ASSIGN"
	depends on PINTx_REASSIGN
	default 0x07000101
config PINT3_ASSIGN
	hex "PINT3_ASSIGN"
	depends on PINTx_REASSIGN
	default 0x02020303

endmenu

endmenu

endif
Commit	Line	Data
24a07a12 RH	1	if (BF54x)
24a07a12 RH	2
4f25eb85 MF	3	source "arch/blackfin/mach-bf548/boards/Kconfig"
4f25eb85 MF	4
24a07a12 RH	5	menu "BF548 Specific Configuration"
24a07a12 RH	6
a924db7c MH	7	config DEB_DMA_URGENT
	8	bool "DMA has priority over core for ext. accesses"
	9	depends on BF54x
b8aab6f6	10	default y
a924db7c MH	11	help
	12	Treat any DEB1, DEB2 and DEB3 request as Urgent
	13
8d5c2f03 SZ	14	config BF548_ATAPI_ALTERNATIVE_PORT
	15	bool "BF548 ATAPI alternative port via GPIO"
	16	help
	17	BF548 ATAPI data and address PINs can be routed through
	18	async address or GPIO port F and G. Select y to route it
	19	to GPIO.
	20
24a07a12 RH	21	comment "Interrupt Priority Assignment"
	22	menu "Priority"
	23
	24	config IRQ_PLL_WAKEUP
	25	int "IRQ_PLL_WAKEUP"
	26	default 7
	27	config IRQ_DMAC0_ERR
	28	int "IRQ_DMAC0_ERR"
	29	default 7
	30	config IRQ_EPPI0_ERR
	31	int "IRQ_EPPI0_ERR"
	32	default 7
	33	config IRQ_SPORT0_ERR
	34	int "IRQ_SPORT0_ERR"
	35	default 7
	36	config IRQ_SPORT1_ERR
	37	int "IRQ_SPORT1_ERR"
	38	default 7
	39	config IRQ_SPI0_ERR
	40	int "IRQ_SPI0_ERR"
	41	default 7
	42	config IRQ_UART0_ERR
	43	int "IRQ_UART0_ERR"
	44	default 7
	45	config IRQ_RTC
	46	int "IRQ_RTC"
	47	default 8
	48	config IRQ_EPPI0
	49	int "IRQ_EPPI0"
	50	default 8
	51	config IRQ_SPORT0_RX
	52	int "IRQ_SPORT0_RX"
	53	default 9
	54	config IRQ_SPORT0_TX
	55	int "IRQ_SPORT0_TX"
	56	default 9
	57	config IRQ_SPORT1_RX
	58	int "IRQ_SPORT1_RX"
	59	default 9
	60	config IRQ_SPORT1_TX
	61	int "IRQ_SPORT1_TX"
	62	default 9
	63	config IRQ_SPI0
	64	int "IRQ_SPI0"
	65	default 10
	66	config IRQ_UART0_RX
	67	int "IRQ_UART0_RX"
	68	default 10
	69	config IRQ_UART0_TX
	70	int "IRQ_UART0_TX"
	71	default 10
	72	config IRQ_TIMER8
	73	int "IRQ_TIMER8"
	74	default 11
	75	config IRQ_TIMER9
	76	int "IRQ_TIMER9"
	77	default 11
	78	config IRQ_TIMER10
	79	int "IRQ_TIMER10"
	80	default 11
	81	config IRQ_PINT0
	82	int "IRQ_PINT0"
	83	default 12
	84	config IRQ_PINT1
85	int "IRQ_PINT0"
86	default 12
87	config IRQ_MDMAS0
88	int "IRQ_MDMAS0"
89	default 13
90	config IRQ_MDMAS1
91	int "IRQ_DMDMAS1"
92	default 13
93	config IRQ_WATCHDOG
94	int "IRQ_WATCHDOG"
95	default 13
96	config IRQ_DMAC1_ERR
97	int "IRQ_DMAC1_ERR"
98	default 7
99	config IRQ_SPORT2_ERR
100	int "IRQ_SPORT2_ERR"
101	default 7
102	config IRQ_SPORT3_ERR
103	int "IRQ_SPORT3_ERR"
104	default 7
105	config IRQ_MXVR_DATA
106	int "IRQ MXVR Data"
107	default 7
108	config IRQ_SPI1_ERR
109	int "IRQ_SPI1_ERR"
110	default 7
111	config IRQ_SPI2_ERR
112	int "IRQ_SPI2_ERR"
113	default 7
114	config IRQ_UART1_ERR
115	int "IRQ_UART1_ERR"
116	default 7
117	config IRQ_UART2_ERR
118	int "IRQ_UART2_ERR"
119	default 7
120	config IRQ_CAN0_ERR
121	int "IRQ_CAN0_ERR"
122	default 7
123	config IRQ_SPORT2_RX
124	int "IRQ_SPORT2_RX"
125	default 9
126	config IRQ_SPORT2_TX
127	int "IRQ_SPORT2_TX"
128	default 9
129	config IRQ_SPORT3_RX
130	int "IRQ_SPORT3_RX"
131	default 9
132	config IRQ_SPORT3_TX
133	int "IRQ_SPORT3_TX"
134	default 9
135	config IRQ_EPPI1
136	int "IRQ_EPPI1"
137	default 9
138	config IRQ_EPPI2
139	int "IRQ_EPPI2"
140	default 9
141	config IRQ_SPI1
142	int "IRQ_SPI1"
143	default 10
144	config IRQ_SPI2
145	int "IRQ_SPI2"
146	default 10
147	config IRQ_UART1_RX
148	int "IRQ_UART1_RX"
149	default 10
150	config IRQ_UART1_TX
151	int "IRQ_UART1_TX"
152	default 10
153	config IRQ_ATAPI_RX
154	int "IRQ_ATAPI_RX"
155	default 10
156	config IRQ_ATAPI_TX
157	int "IRQ_ATAPI_TX"
158	default 10
159	config IRQ_TWI0
160	int "IRQ_TWI0"
161	default 11
162	config IRQ_TWI1
163	int "IRQ_TWI1"
164	default 11
165	config IRQ_CAN0_RX
166	int "IRQ_CAN_RX"
167	default 11
168	config IRQ_CAN0_TX
169	int "IRQ_CAN_TX"
170	default 11
171	config IRQ_MDMAS2
172	int "IRQ_MDMAS2"
173	default 13
174	config IRQ_MDMAS3
175	int "IRQ_DMMAS3"
176	default 13
177	config IRQ_MXVR_ERR
178	int "IRQ_MXVR_ERR"
179	default 11
180	config IRQ_MXVR_MSG
181	int "IRQ_MXVR_MSG"
182	default 11
183	config IRQ_MXVR_PKT
184	int "IRQ_MXVR_PKT"
185	default 11
186	config IRQ_EPPI1_ERR
187	int "IRQ_EPPI1_ERR"
188	default 7
189	config IRQ_EPPI2_ERR
190	int "IRQ_EPPI2_ERR"
191	default 7
192	config IRQ_UART3_ERR
193	int "IRQ_UART3_ERR"
194	default 7
195	config IRQ_HOST_ERR
196	int "IRQ_HOST_ERR"
197	default 7
198	config IRQ_PIXC_ERR
199	int "IRQ_PIXC_ERR"
200	default 7
201	config IRQ_NFC_ERR
202	int "IRQ_NFC_ERR"
203	default 7
204	config IRQ_ATAPI_ERR
205	int "IRQ_ATAPI_ERR"
206	default 7
207	config IRQ_CAN1_ERR
208	int "IRQ_CAN1_ERR"
209	default 7
210	config IRQ_HS_DMA_ERR
211	int "IRQ Handshake DMA Status"
212	default 7
213	config IRQ_PIXC_IN0
214	int "IRQ PIXC IN0"
215	default 8
216	config IRQ_PIXC_IN1
217	int "IRQ PIXC IN1"
218	default 8
219	config IRQ_PIXC_OUT
220	int "IRQ PIXC OUT"
221	default 8
222	config IRQ_SDH
223	int "IRQ SDH"
224	default 8
225	config IRQ_CNT
226	int "IRQ CNT"
227	default 8
228	config IRQ_KEY
229	int "IRQ KEY"
230	default 8
231	config IRQ_CAN1_RX
232	int "IRQ CAN1 RX"
233	default 11
234	config IRQ_CAN1_TX
235	int "IRQ_CAN1_TX"
236	default 11
237	config IRQ_SDH_MASK0
238	int "IRQ_SDH_MASK0"
239	default 11
240	config IRQ_SDH_MASK1
241	int "IRQ_SDH_MASK1"
242	default 11
243	config IRQ_USB_INT0
244	int "IRQ USB INT0"
245	default 11
246	config IRQ_USB_INT1
247	int "IRQ USB INT1"
248	default 11
249	config IRQ_USB_INT2
250	int "IRQ USB INT2"
251	default 11
252	config IRQ_USB_DMA
253	int "IRQ USB DMA"
254	default 11
255	config IRQ_OTPSEC
256	int "IRQ OPTSEC"
257	default 11
258	config IRQ_TIMER0
259	int "IRQ_TIMER0"
6a01f230	260	default 8
24a07a12 RH	261	config IRQ_TIMER1
	262	int "IRQ_TIMER1"
	263	default 11
	264	config IRQ_TIMER2
	265	int "IRQ_TIMER2"
	266	default 11
	267	config IRQ_TIMER3
	268	int "IRQ_TIMER3"
	269	default 11
	270	config IRQ_TIMER4
	271	int "IRQ_TIMER4"
	272	default 11
	273	config IRQ_TIMER5
	274	int "IRQ_TIMER5"
	275	default 11
	276	config IRQ_TIMER6
	277	int "IRQ_TIMER6"
	278	default 11
	279	config IRQ_TIMER7
	280	int "IRQ_TIMER7"
	281	default 11
	282	config IRQ_PINT2
	283	int "IRQ_PIN2"
	284	default 11
	285	config IRQ_PINT3
	286	int "IRQ_PIN3"
	287	default 11
	288
	289	help
	290	Enter the priority numbers between 7-13 ONLY. Others are Reserved.
	291	This applies to all the above. It is not recommended to assign the
	292	highest priority number 7 to UART or any other device.
	293
	294	endmenu
	295
34e0fc89 MH	296	comment "Pin Interrupt to Port Assignment"
	297	menu "Assignment"
	298
	299	config PINTx_REASSIGN
	300	bool "Reprogram PINT Assignment"
31430ba5	301	default y
34e0fc89 MH	302	help
	303	The interrupt assignment registers controls the pin-to-interrupt
	304	assignment in a byte-wide manner. Each option allows you to select
	305	a set of pins (High/Low Byte) of an specific Port being mapped
	306	to one of the four PIN Interrupts IRQ_PINTx.
	307
	308	You shouldn't change any of these unless you know exactly what you're doing.
	309	Please consult the Blackfin BF54x Processor Hardware Reference Manual.
	310
	311	config PINT0_ASSIGN
	312	hex "PINT0_ASSIGN"
	313	depends on PINTx_REASSIGN
	314	default 0x00000101
	315	config PINT1_ASSIGN
	316	hex "PINT1_ASSIGN"
	317	depends on PINTx_REASSIGN
	318	default 0x01010000
	319	config PINT2_ASSIGN
	320	hex "PINT2_ASSIGN"
	321	depends on PINTx_REASSIGN
31430ba5	322	default 0x07000101
34e0fc89 MH	323	config PINT3_ASSIGN
	324	hex "PINT3_ASSIGN"
	325	depends on PINTx_REASSIGN
	326	default 0x02020303
	327
	328	endmenu
	329
24a07a12 RH	330	endmenu
	331
	332	endif