[linux-2.6-block.git] / arch / blackfin / mach-bf537 / boards / dnp5370.c

/*
 * This is the configuration for SSV Dil/NetPC DNP/5370 board.
 *
 * DIL module:         http://www.dilnetpc.com/dnp0086.htm
 * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
 *
 * Copyright 2010 3ality Digital Systems
 * Copyright 2005 National ICT Australia (NICTA)
 * Copyright 2004-2006 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/device.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/plat-ram.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/spi/mmc_spi.h>
#include <linux/phy.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/reboot.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>

/*
 * Name the Board for the /proc/cpuinfo
 */
const char bfin_board_name[] = "DNP/5370";
#define FLASH_MAC               0x202f0000
#define CONFIG_MTD_PHYSMAP_LEN  0x300000

#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
static struct platform_device rtc_device = {
	.name = "rtc-bfin",
	.id   = -1,
};
#endif

#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
#include <linux/bfin_mac.h>
static const unsigned short bfin_mac_peripherals[] = P_RMII0;

static struct bfin_phydev_platform_data bfin_phydev_data[] = {
	{
		.addr = 1,
		.irq = PHY_POLL, /* IRQ_MAC_PHYINT */
	},
};

static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
	.phydev_number   = 1,
	.phydev_data     = bfin_phydev_data,
	.phy_mode        = PHY_INTERFACE_MODE_RMII,
	.mac_peripherals = bfin_mac_peripherals,
};

static struct platform_device bfin_mii_bus = {
	.name = "bfin_mii_bus",
	.dev = {
		.platform_data = &bfin_mii_bus_data,
	}
};

static struct platform_device bfin_mac_device = {
	.name = "bfin_mac",
	.dev = {
		.platform_data = &bfin_mii_bus,
	}
};
#endif

#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static struct mtd_partition asmb_flash_partitions[] = {
	{
		.name       = "bootloader(nor)",
		.size       = 0x30000,
		.offset     = 0,
	}, {
		.name       = "linux kernel and rootfs(nor)",
		.size       = 0x300000 - 0x30000 - 0x10000,
		.offset     = MTDPART_OFS_APPEND,
	}, {
		.name       = "MAC address(nor)",
		.size       = 0x10000,
		.offset     = MTDPART_OFS_APPEND,
		.mask_flags = MTD_WRITEABLE,
	}
};

static struct physmap_flash_data asmb_flash_data = {
	.width      = 1,
	.parts      = asmb_flash_partitions,
	.nr_parts   = ARRAY_SIZE(asmb_flash_partitions),
};

static struct resource asmb_flash_resource = {
	.start = 0x20000000,
	.end   = 0x202fffff,
	.flags = IORESOURCE_MEM,
};

/* 4 MB NOR flash attached to async memory banks 0-2,
 * therefore only 3 MB visible.
 */
static struct platform_device asmb_flash_device = {
	.name	  = "physmap-flash",
	.id	  = 0,
	.dev = {
		.platform_data = &asmb_flash_data,
	},
	.num_resources = 1,
	.resource      = &asmb_flash_resource,
};
#endif

#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)

#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)

static struct bfin5xx_spi_chip mmc_spi_chip_info = {
	.enable_dma    = 0,	 /* use no dma transfer with this chip*/
};

#endif

#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
/* This mapping is for at45db642 it has 1056 page size,
 * partition size and offset should be page aligned
 */
static struct mtd_partition bfin_spi_dataflash_partitions[] = {
	{
		.name   = "JFFS2 dataflash(nor)",
#ifdef CONFIG_MTD_PAGESIZE_1024
		.offset = 0x40000,
		.size   = 0x7C0000,
#else
		.offset = 0x0,
		.size   = 0x840000,
#endif
	}
};

static struct flash_platform_data bfin_spi_dataflash_data = {
	.name     = "mtd_dataflash",
	.parts    = bfin_spi_dataflash_partitions,
	.nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
	.type     = "mtd_dataflash",
};

static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
	.enable_dma    = 0,	 /* use no dma transfer with this chip*/
};
#endif

static struct spi_board_info bfin_spi_board_info[] __initdata = {
/* SD/MMC card reader at SPI bus */
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
	{
		.modalias	 = "mmc_spi",
		.max_speed_hz    = 20000000,
		.bus_num	 = 0,
		.chip_select     = 1,
		.controller_data = &mmc_spi_chip_info,
		.mode	         = SPI_MODE_3,
	},
#endif

/* 8 Megabyte Atmel NOR flash chip at SPI bus */
#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
	{
	.modalias        = "mtd_dataflash",
	.max_speed_hz    = 16700000,
	.bus_num         = 0,
	.chip_select     = 2,
	.platform_data   = &bfin_spi_dataflash_data,
	.controller_data = &spi_dataflash_chip_info,
	.mode            = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
	},
#endif
};

/* SPI controller data */
/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
	[0] = {
		.start = SPI0_REGBASE,
		.end   = SPI0_REGBASE + 0xFF,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = CH_SPI,
		.end   = CH_SPI,
		.flags = IORESOURCE_DMA,
	},
	[2] = {
		.start = IRQ_SPI,
		.end   = IRQ_SPI,
		.flags = IORESOURCE_IRQ,
	},
};

static struct bfin5xx_spi_master spi_bfin_master_info = {
	.num_chipselect = 8,
	.enable_dma     = 1,  /* master has the ability to do dma transfer */
	.pin_req        = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};

static struct platform_device spi_bfin_master_device = {
	.name          = "bfin-spi",
	.id            = 0, /* Bus number */
	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
	.resource      = bfin_spi0_resource,
	.dev           = {
		.platform_data = &spi_bfin_master_info, /* Passed to driver */
	},
};
#endif

#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
#ifdef CONFIG_SERIAL_BFIN_UART0
static struct resource bfin_uart0_resources[] = {
	{
		.start = UART0_THR,
		.end = UART0_GCTL+2,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_UART0_TX,
		.end = IRQ_UART0_TX,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = IRQ_UART0_RX,
		.end = IRQ_UART0_RX,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = IRQ_UART0_ERROR,
		.end = IRQ_UART0_ERROR,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = CH_UART0_TX,
		.end = CH_UART0_TX,
		.flags = IORESOURCE_DMA,
	},
	{
		.start = CH_UART0_RX,
		.end = CH_UART0_RX,
		.flags = IORESOURCE_DMA,
	},
};

static unsigned short bfin_uart0_peripherals[] = {
	P_UART0_TX, P_UART0_RX, 0
};

static struct platform_device bfin_uart0_device = {
	.name = "bfin-uart",
	.id = 0,
	.num_resources = ARRAY_SIZE(bfin_uart0_resources),
	.resource = bfin_uart0_resources,
	.dev = {
		.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
	},
};
#endif

#ifdef CONFIG_SERIAL_BFIN_UART1
static struct resource bfin_uart1_resources[] = {
	{
		.start = UART1_THR,
		.end   = UART1_GCTL+2,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_UART1_TX,
		.end   = IRQ_UART1_TX,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = IRQ_UART1_RX,
		.end   = IRQ_UART1_RX,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = IRQ_UART1_ERROR,
		.end   = IRQ_UART1_ERROR,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = CH_UART1_TX,
		.end   = CH_UART1_TX,
		.flags = IORESOURCE_DMA,
	},
	{
		.start = CH_UART1_RX,
		.end   = CH_UART1_RX,
		.flags = IORESOURCE_DMA,
	},
};

static unsigned short bfin_uart1_peripherals[] = {
	P_UART1_TX, P_UART1_RX, 0
};

static struct platform_device bfin_uart1_device = {
	.name          = "bfin-uart",
	.id            = 1,
	.num_resources = ARRAY_SIZE(bfin_uart1_resources),
	.resource      = bfin_uart1_resources,
	.dev = {
		.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
	},
};
#endif
#endif

#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
	[0] = {
		.start = TWI0_REGBASE,
		.end   = TWI0_REGBASE + 0xff,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_TWI,
		.end   = IRQ_TWI,
		.flags = IORESOURCE_IRQ,
	},
};

static struct platform_device i2c_bfin_twi_device = {
	.name          = "i2c-bfin-twi",
	.id            = 0,
	.num_resources = ARRAY_SIZE(bfin_twi0_resource),
	.resource      = bfin_twi0_resource,
};
#endif

static struct platform_device *dnp5370_devices[] __initdata = {

#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
#ifdef CONFIG_SERIAL_BFIN_UART0
	&bfin_uart0_device,
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
	&bfin_uart1_device,
#endif
#endif

#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
	&asmb_flash_device,
#endif

#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
	&bfin_mii_bus,
	&bfin_mac_device,
#endif

#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
	&spi_bfin_master_device,
#endif

#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
	&i2c_bfin_twi_device,
#endif

#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
	&rtc_device,
#endif

};

static int __init dnp5370_init(void)
{
	printk(KERN_INFO "DNP/5370: registering device resources\n");
	platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
	printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
	       ARRAY_SIZE(bfin_spi_board_info));
	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
	printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
	return 0;
}
arch_initcall(dnp5370_init);

/*
 * Currently the MAC address is saved in Flash by U-Boot
 */
void bfin_get_ether_addr(char *addr)
{
	*(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
	*(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
}
EXPORT_SYMBOL(bfin_get_ether_addr);
Commit	Line	Data
3ea9f2bf AS	1	/*
	2	* This is the configuration for SSV Dil/NetPC DNP/5370 board.
	3	*
	4	* DIL module: http://www.dilnetpc.com/dnp0086.htm
	5	* SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
	6	*
	7	* Copyright 2010 3ality Digital Systems
	8	* Copyright 2005 National ICT Australia (NICTA)
	9	* Copyright 2004-2006 Analog Devices Inc.
	10	*
	11	* Licensed under the GPL-2 or later.
	12	*/
	13
	14	#include <linux/device.h>
90590543	15	#include <linux/export.h>
3ea9f2bf AS	16	#include <linux/kernel.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/io.h>
	19	#include <linux/mtd/mtd.h>
	20	#include <linux/mtd/nand.h>
	21	#include <linux/mtd/partitions.h>
	22	#include <linux/mtd/plat-ram.h>
	23	#include <linux/mtd/physmap.h>
	24	#include <linux/spi/spi.h>
	25	#include <linux/spi/flash.h>
	26	#include <linux/irq.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/i2c.h>
	29	#include <linux/spi/mmc_spi.h>
	30	#include <linux/phy.h>
	31	#include <asm/dma.h>
	32	#include <asm/bfin5xx_spi.h>
	33	#include <asm/reboot.h>
	34	#include <asm/portmux.h>
	35	#include <asm/dpmc.h>
	36
	37	/*
	38	* Name the Board for the /proc/cpuinfo
	39	*/
	40	const char bfin_board_name[] = "DNP/5370";
	41	#define FLASH_MAC 0x202f0000
	42	#define CONFIG_MTD_PHYSMAP_LEN 0x300000
	43
	44	#if defined(CONFIG_RTC_DRV_BFIN) \|\| defined(CONFIG_RTC_DRV_BFIN_MODULE)
	45	static struct platform_device rtc_device = {
	46	.name = "rtc-bfin",
	47	.id = -1,
	48	};
	49	#endif
	50
	51	#if defined(CONFIG_BFIN_MAC) \|\| defined(CONFIG_BFIN_MAC_MODULE)
	52	#include <linux/bfin_mac.h>
	53	static const unsigned short bfin_mac_peripherals[] = P_RMII0;
	54
	55	static struct bfin_phydev_platform_data bfin_phydev_data[] = {
	56	{
	57	.addr = 1,
	58	.irq = PHY_POLL, /* IRQ_MAC_PHYINT */
	59	},
	60	};
	61
	62	static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
	63	.phydev_number = 1,
	64	.phydev_data = bfin_phydev_data,
	65	.phy_mode = PHY_INTERFACE_MODE_RMII,
	66	.mac_peripherals = bfin_mac_peripherals,
	67	};
	68
	69	static struct platform_device bfin_mii_bus = {
	70	.name = "bfin_mii_bus",
	71	.dev = {
	72	.platform_data = &bfin_mii_bus_data,
	73	}
	74	};
	75
	76	static struct platform_device bfin_mac_device = {
	77	.name = "bfin_mac",
	78	.dev = {
	79	.platform_data = &bfin_mii_bus,
80	}
81	};
82	#endif
83
84	#if defined(CONFIG_MTD_PHYSMAP) \|\| defined(CONFIG_MTD_PHYSMAP_MODULE)
85	static struct mtd_partition asmb_flash_partitions[] = {
86	{
87	.name = "bootloader(nor)",
88	.size = 0x30000,
89	.offset = 0,
90	}, {
91	.name = "linux kernel and rootfs(nor)",
92	.size = 0x300000 - 0x30000 - 0x10000,
93	.offset = MTDPART_OFS_APPEND,
94	}, {
95	.name = "MAC address(nor)",
96	.size = 0x10000,
97	.offset = MTDPART_OFS_APPEND,
98	.mask_flags = MTD_WRITEABLE,
99	}
100	};
101
102	static struct physmap_flash_data asmb_flash_data = {
103	.width = 1,
104	.parts = asmb_flash_partitions,
105	.nr_parts = ARRAY_SIZE(asmb_flash_partitions),
106	};
107
108	static struct resource asmb_flash_resource = {
109	.start = 0x20000000,
110	.end = 0x202fffff,
111	.flags = IORESOURCE_MEM,
112	};
113
114	/* 4 MB NOR flash attached to async memory banks 0-2,
115	* therefore only 3 MB visible.
116	*/
117	static struct platform_device asmb_flash_device = {
118	.name = "physmap-flash",
119	.id = 0,
120	.dev = {
121	.platform_data = &asmb_flash_data,
122	},
123	.num_resources = 1,
124	.resource = &asmb_flash_resource,
125	};
126	#endif
127
128	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
129
130	#if defined(CONFIG_MMC_SPI) \|\| defined(CONFIG_MMC_SPI_MODULE)
131
3ea9f2bf AS	132	static struct bfin5xx_spi_chip mmc_spi_chip_info = {
3ea9f2bf AS	133	.enable_dma = 0, /* use no dma transfer with this chip*/
3ea9f2bf AS	134	};
3ea9f2bf AS	135
3ea9f2bf AS	136	#endif
	137
	138	#if defined(CONFIG_MTD_DATAFLASH) \|\| defined(CONFIG_MTD_DATAFLASH_MODULE)
	139	/* This mapping is for at45db642 it has 1056 page size,
	140	* partition size and offset should be page aligned
	141	*/
	142	static struct mtd_partition bfin_spi_dataflash_partitions[] = {
	143	{
	144	.name = "JFFS2 dataflash(nor)",
	145	#ifdef CONFIG_MTD_PAGESIZE_1024
	146	.offset = 0x40000,
	147	.size = 0x7C0000,
	148	#else
	149	.offset = 0x0,
	150	.size = 0x840000,
	151	#endif
	152	}
	153	};
	154
	155	static struct flash_platform_data bfin_spi_dataflash_data = {
	156	.name = "mtd_dataflash",
	157	.parts = bfin_spi_dataflash_partitions,
	158	.nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
	159	.type = "mtd_dataflash",
	160	};
	161
	162	static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
	163	.enable_dma = 0, /* use no dma transfer with this chip*/
3ea9f2bf AS	164	};
	165	#endif
	166
	167	static struct spi_board_info bfin_spi_board_info[] __initdata = {
	168	/* SD/MMC card reader at SPI bus */
	169	#if defined(CONFIG_MMC_SPI) \|\| defined(CONFIG_MMC_SPI_MODULE)
	170	{
	171	.modalias = "mmc_spi",
	172	.max_speed_hz = 20000000,
	173	.bus_num = 0,
	174	.chip_select = 1,
3ea9f2bf AS	175	.controller_data = &mmc_spi_chip_info,
	176	.mode = SPI_MODE_3,
	177	},
	178	#endif
	179
	180	/* 8 Megabyte Atmel NOR flash chip at SPI bus */
	181	#if defined(CONFIG_MTD_DATAFLASH) \|\| defined(CONFIG_MTD_DATAFLASH_MODULE)
	182	{
	183	.modalias = "mtd_dataflash",
	184	.max_speed_hz = 16700000,
	185	.bus_num = 0,
	186	.chip_select = 2,
	187	.platform_data = &bfin_spi_dataflash_data,
	188	.controller_data = &spi_dataflash_chip_info,
	189	.mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
	190	},
	191	#endif
	192	};
	193
	194	/* SPI controller data */
	195	/* SPI (0) */
	196	static struct resource bfin_spi0_resource[] = {
	197	[0] = {
	198	.start = SPI0_REGBASE,
	199	.end = SPI0_REGBASE + 0xFF,
	200	.flags = IORESOURCE_MEM,
	201	},
	202	[1] = {
	203	.start = CH_SPI,
	204	.end = CH_SPI,
	205	.flags = IORESOURCE_DMA,
	206	},
	207	[2] = {
	208	.start = IRQ_SPI,
	209	.end = IRQ_SPI,
	210	.flags = IORESOURCE_IRQ,
	211	},
	212	};
	213
	214	static struct bfin5xx_spi_master spi_bfin_master_info = {
	215	.num_chipselect = 8,
	216	.enable_dma = 1, /* master has the ability to do dma transfer */
	217	.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
	218	};
	219
	220	static struct platform_device spi_bfin_master_device = {
	221	.name = "bfin-spi",
	222	.id = 0, /* Bus number */
	223	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
	224	.resource = bfin_spi0_resource,
	225	.dev = {
	226	.platform_data = &spi_bfin_master_info, /* Passed to driver */
	227	},
	228	};
	229	#endif
	230
	231	#if defined(CONFIG_SERIAL_BFIN) \|\| defined(CONFIG_SERIAL_BFIN_MODULE)
	232	#ifdef CONFIG_SERIAL_BFIN_UART0
	233	static struct resource bfin_uart0_resources[] = {
	234	{
	235	.start = UART0_THR,
	236	.end = UART0_GCTL+2,
	237	.flags = IORESOURCE_MEM,
	238	},
edb0a640 SZ	239	{
	240	.start = IRQ_UART0_TX,
	241	.end = IRQ_UART0_TX,
	242	.flags = IORESOURCE_IRQ,
	243	},
3ea9f2bf AS	244	{
3ea9f2bf AS	245	.start = IRQ_UART0_RX,
edb0a640	246	.end = IRQ_UART0_RX,
3ea9f2bf AS	247	.flags = IORESOURCE_IRQ,
	248	},
	249	{
	250	.start = IRQ_UART0_ERROR,
	251	.end = IRQ_UART0_ERROR,
	252	.flags = IORESOURCE_IRQ,
	253	},
	254	{
	255	.start = CH_UART0_TX,
	256	.end = CH_UART0_TX,
	257	.flags = IORESOURCE_DMA,
	258	},
	259	{
	260	.start = CH_UART0_RX,
	261	.end = CH_UART0_RX,
	262	.flags = IORESOURCE_DMA,
	263	},
	264	};
	265
	266	static unsigned short bfin_uart0_peripherals[] = {
	267	P_UART0_TX, P_UART0_RX, 0
	268	};
	269
	270	static struct platform_device bfin_uart0_device = {
	271	.name = "bfin-uart",
	272	.id = 0,
	273	.num_resources = ARRAY_SIZE(bfin_uart0_resources),
	274	.resource = bfin_uart0_resources,
	275	.dev = {
	276	.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
	277	},
	278	};
	279	#endif
	280
	281	#ifdef CONFIG_SERIAL_BFIN_UART1
	282	static struct resource bfin_uart1_resources[] = {
	283	{
	284	.start = UART1_THR,
	285	.end = UART1_GCTL+2,
	286	.flags = IORESOURCE_MEM,
	287	},
edb0a640 SZ	288	{
	289	.start = IRQ_UART1_TX,
	290	.end = IRQ_UART1_TX,
	291	.flags = IORESOURCE_IRQ,
	292	},
3ea9f2bf AS	293	{
3ea9f2bf AS	294	.start = IRQ_UART1_RX,
edb0a640	295	.end = IRQ_UART1_RX,
3ea9f2bf AS	296	.flags = IORESOURCE_IRQ,
	297	},
	298	{
	299	.start = IRQ_UART1_ERROR,
	300	.end = IRQ_UART1_ERROR,
	301	.flags = IORESOURCE_IRQ,
	302	},
	303	{
	304	.start = CH_UART1_TX,
	305	.end = CH_UART1_TX,
	306	.flags = IORESOURCE_DMA,
	307	},
	308	{
	309	.start = CH_UART1_RX,
	310	.end = CH_UART1_RX,
	311	.flags = IORESOURCE_DMA,
	312	},
	313	};
	314
	315	static unsigned short bfin_uart1_peripherals[] = {
	316	P_UART1_TX, P_UART1_RX, 0
	317	};
	318
	319	static struct platform_device bfin_uart1_device = {
	320	.name = "bfin-uart",
	321	.id = 1,
	322	.num_resources = ARRAY_SIZE(bfin_uart1_resources),
	323	.resource = bfin_uart1_resources,
	324	.dev = {
	325	.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
	326	},
	327	};
	328	#endif
	329	#endif
	330
	331	#if defined(CONFIG_I2C_BLACKFIN_TWI) \|\| defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
	332	static struct resource bfin_twi0_resource[] = {
	333	[0] = {
	334	.start = TWI0_REGBASE,
	335	.end = TWI0_REGBASE + 0xff,
	336	.flags = IORESOURCE_MEM,
	337	},
	338	[1] = {
	339	.start = IRQ_TWI,
	340	.end = IRQ_TWI,
	341	.flags = IORESOURCE_IRQ,
	342	},
	343	};
	344
	345	static struct platform_device i2c_bfin_twi_device = {
	346	.name = "i2c-bfin-twi",
	347	.id = 0,
	348	.num_resources = ARRAY_SIZE(bfin_twi0_resource),
	349	.resource = bfin_twi0_resource,
	350	};
	351	#endif
	352
	353	static struct platform_device *dnp5370_devices[] __initdata = {
	354
	355	#if defined(CONFIG_SERIAL_BFIN) \|\| defined(CONFIG_SERIAL_BFIN_MODULE)
	356	#ifdef CONFIG_SERIAL_BFIN_UART0
	357	&bfin_uart0_device,
	358	#endif
	359	#ifdef CONFIG_SERIAL_BFIN_UART1
360	&bfin_uart1_device,
361	#endif
362	#endif
363
364	#if defined(CONFIG_MTD_PHYSMAP) \|\| defined(CONFIG_MTD_PHYSMAP_MODULE)
365	&asmb_flash_device,
366	#endif
367
368	#if defined(CONFIG_BFIN_MAC) \|\| defined(CONFIG_BFIN_MAC_MODULE)
369	&bfin_mii_bus,
370	&bfin_mac_device,
371	#endif
372
373	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
374	&spi_bfin_master_device,
375	#endif
376
377	#if defined(CONFIG_I2C_BLACKFIN_TWI) \|\| defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
378	&i2c_bfin_twi_device,
379	#endif
380
381	#if defined(CONFIG_RTC_DRV_BFIN) \|\| defined(CONFIG_RTC_DRV_BFIN_MODULE)
382	&rtc_device,
383	#endif
384
385	};
386
387	static int __init dnp5370_init(void)
388	{
389	printk(KERN_INFO "DNP/5370: registering device resources\n");
390	platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
391	printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
392	ARRAY_SIZE(bfin_spi_board_info));
393	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
394	printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
395	return 0;
396	}
397	arch_initcall(dnp5370_init);
398
399	/*
400	* Currently the MAC address is saved in Flash by U-Boot
401	*/
402	void bfin_get_ether_addr(char *addr)
403	{
404	(u32 )(&(addr[0])) = bfin_read32(FLASH_MAC);
405	(u16 )(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
406	}
407	EXPORT_SYMBOL(bfin_get_ether_addr);