[linux-block.git] / arch / blackfin / mach-bf533 / head.S

/*
 * File:         arch/blackfin/mach-bf533/head.S
 * Based on:
 * Author:       Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
 *
 * Created:      1998
 * Description:  bf533 startup file
 *
 * Modified:
 *               Copyright 2004-2006 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif

.global __rambase
.global __ramstart
.global __ramend
.extern ___bss_stop
.extern ___bss_start
.extern _bf53x_relocate_l1_mem

#define INITIAL_STACK	0xFFB01000

__INIT

ENTRY(__start)
	/* R0: argument of command line string, passed from uboot, save it */
	R7 = R0;
	/* Enable Cycle Counter and Nesting Of Interrupts */
#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
	R0 = SYSCFG_SNEN;
#else
	R0 = SYSCFG_SNEN | SYSCFG_CCEN;
#endif
	SYSCFG = R0;
	R0 = 0;

	/* Clear Out All the data and pointer Registers */
	R1 = R0;
	R2 = R0;
	R3 = R0;
	R4 = R0;
	R5 = R0;
	R6 = R0;

	P0 = R0;
	P1 = R0;
	P2 = R0;
	P3 = R0;
	P4 = R0;
	P5 = R0;

	LC0 = r0;
	LC1 = r0;
	L0 = r0;
	L1 = r0;
	L2 = r0;
	L3 = r0;

	/* Clear Out All the DAG Registers */
	B0 = r0;
	B1 = r0;
	B2 = r0;
	B3 = r0;

	I0 = r0;
	I1 = r0;
	I2 = r0;
	I3 = r0;

	M0 = r0;
	M1 = r0;
	M2 = r0;
	M3 = r0;

	trace_buffer_init(p0,r0);
	P0 = R1;
	R0 = R1;

	p0.h = hi(FIO_MASKA_C);
	p0.l = lo(FIO_MASKA_C);
	r0 = 0xFFFF(Z);
	w[p0] = r0.L;	/* Disable all interrupts */
	ssync;

	p0.h = hi(FIO_MASKB_C);
	p0.l = lo(FIO_MASKB_C);
	r0 = 0xFFFF(Z);
	w[p0] = r0.L;	/* Disable all interrupts */
	ssync;

	/* Turn off the icache */
	p0.l = LO(IMEM_CONTROL);
	p0.h = HI(IMEM_CONTROL);
	R1 = [p0];
	R0 = ~ENICPLB;
	R0 = R0 & R1;

	/* Anomaly 05000125 */
#if ANOMALY_05000125
	CLI R2;
	SSYNC;
#endif
	[p0] = R0;
	SSYNC;
#if ANOMALY_05000125
	STI R2;
#endif

	/* Turn off the dcache */
	p0.l = LO(DMEM_CONTROL);
	p0.h = HI(DMEM_CONTROL);
	R1 = [p0];
	R0 = ~ENDCPLB;
	R0 = R0 & R1;

	/* Anomaly 05000125 */
#if ANOMALY_05000125
	CLI R2;
	SSYNC;
#endif
	[p0] = R0;
	SSYNC;
#if ANOMALY_05000125
	STI R2;
#endif

	/* Initialise UART - when booting from u-boot, the UART is not disabled
	 * so if we dont initalize here, our serial console gets hosed */
	p0.h = hi(UART_LCR);
	p0.l = lo(UART_LCR);
	r0 = 0x0(Z);
	w[p0] = r0.L;	/* To enable DLL writes */
	ssync;

	p0.h = hi(UART_DLL);
	p0.l = lo(UART_DLL);
	r0 = 0x0(Z);
	w[p0] = r0.L;
	ssync;

	p0.h = hi(UART_DLH);
	p0.l = lo(UART_DLH);
	r0 = 0x00(Z);
	w[p0] = r0.L;
	ssync;

	p0.h = hi(UART_GCTL);
	p0.l = lo(UART_GCTL);
	r0 = 0x0(Z);
	w[p0] = r0.L;	/* To enable UART clock */
	ssync;

	/* Initialize stack pointer */
	sp.l = lo(INITIAL_STACK);
	sp.h = hi(INITIAL_STACK);
	fp = sp;
	usp = sp;

	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
	call _bf53x_relocate_l1_mem;
#if CONFIG_BFIN_KERNEL_CLOCK
	call _start_dma_code;
#endif

	/* Code for initializing Async memory banks */

	p2.h = hi(EBIU_AMBCTL1);
	p2.l = lo(EBIU_AMBCTL1);
	r0.h = hi(AMBCTL1VAL);
	r0.l = lo(AMBCTL1VAL);
	[p2] = r0;
	ssync;

	p2.h = hi(EBIU_AMBCTL0);
	p2.l = lo(EBIU_AMBCTL0);
	r0.h = hi(AMBCTL0VAL);
	r0.l = lo(AMBCTL0VAL);
	[p2] = r0;
	ssync;

	p2.h = hi(EBIU_AMGCTL);
	p2.l = lo(EBIU_AMGCTL);
	r0 = AMGCTLVAL;
	w[p2] = r0;
	ssync;

	/* This section keeps the processor in supervisor mode
	 * during kernel boot.  Switches to user mode at end of boot.
	 * See page 3-9 of Hardware Reference manual for documentation.
	 */

	/* EVT15 = _real_start */

	p0.l = lo(EVT15);
	p0.h = hi(EVT15);
	p1.l = _real_start;
	p1.h = _real_start;
	[p0] = p1;
	csync;

	p0.l = lo(IMASK);
	p0.h = hi(IMASK);
	p1.l = IMASK_IVG15;
	p1.h = 0x0;
	[p0] = p1;
	csync;

	raise 15;
	p0.l = .LWAIT_HERE;
	p0.h = .LWAIT_HERE;
	reti = p0;
#if ANOMALY_05000281
	nop; nop; nop;
#endif
	rti;

.LWAIT_HERE:
	jump .LWAIT_HERE;
ENDPROC(__start)

ENTRY(_real_start)
	[ -- sp ] = reti;
	p0.l = lo(WDOG_CTL);
	p0.h = hi(WDOG_CTL);
	r0 = 0xAD6(z);
	w[p0] = r0;	/* watchdog off for now */
	ssync;

	/* Code update for BSS size == 0
	 * Zero out the bss region.
	 */

	p1.l = ___bss_start;
	p1.h = ___bss_start;
	p2.l = ___bss_stop;
	p2.h = ___bss_stop;
	r0 = 0;
	p2 -= p1;
	lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
.L_clear_bss:
	B[p1++] = r0;

	/* In case there is a NULL pointer reference
	 * Zero out region before stext
	 */

	p1.l = 0x0;
	p1.h = 0x0;
	r0.l = __stext;
	r0.h = __stext;
	r0 = r0 >> 1;
	p2 = r0;
	r0 = 0;
	lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
.L_clear_zero:
	W[p1++] = r0;

	/* pass the uboot arguments to the global value command line */
	R0 = R7;
	call _cmdline_init;

	p1.l = __rambase;
	p1.h = __rambase;
	r0.l = __sdata;
	r0.h = __sdata;
	[p1] = r0;

	p1.l = __ramstart;
	p1.h = __ramstart;
	p3.l = ___bss_stop;
	p3.h = ___bss_stop;

	r1 = p3;
	[p1] = r1;

	/*
	 * load the current thread pointer and stack
	 */
	r1.l = _init_thread_union;
	r1.h = _init_thread_union;

	r2.l = 0x2000;
	r2.h = 0x0000;
	r1 = r1 + r2;
	sp = r1;
	usp = sp;
	fp = sp;
	jump.l _start_kernel;
ENDPROC(_real_start)

__FINIT

.section .l1.text
#if CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)
	p0.h = hi(SIC_IWR);
	p0.l = lo(SIC_IWR);
	r0.l = 0x1;
	r0.h = 0x0;
	[p0] = r0;
	SSYNC;

	/*
	 *  Set PLL_CTL
	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
	 *   - [7]     = output delay (add 200ps of delay to mem signals)
	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
	 *   - [5]     = PDWN      : 1=All Clocks off
	 *   - [3]     = STOPCK    : 1=Core Clock off
	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
	 *   all other bits set to zero
	 */

	p0.h = hi(PLL_LOCKCNT);
	p0.l = lo(PLL_LOCKCNT);
	r0 = 0x300(Z);
	w[p0] = r0.l;
	ssync;

	P2.H = hi(EBIU_SDGCTL);
	P2.L = lo(EBIU_SDGCTL);
	R0 = [P2];
	BITSET (R0, 24);
	[P2] = R0;
	SSYNC;

	r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
	r0 = r0 << 9;                    /* Shift it over,                  */
	r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
	r0 = r1 | r0;
	r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
	r1 = r1 << 8;                    /* Shift it over                   */
	r0 = r1 | r0;                    /* add them all together           */

	p0.h = hi(PLL_CTL);
	p0.l = lo(PLL_CTL);              /* Load the address                */
	cli r2;                          /* Disable interrupts              */
	ssync;
	w[p0] = r0.l;                    /* Set the value                   */
	idle;                            /* Wait for the PLL to stablize    */
	sti r2;                          /* Enable interrupts               */

.Lcheck_again:
	p0.h = hi(PLL_STAT);
	p0.l = lo(PLL_STAT);
	R0 = W[P0](Z);
	CC = BITTST(R0,5);
	if ! CC jump .Lcheck_again;

	/* Configure SCLK & CCLK Dividers */
	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
	p0.h = hi(PLL_DIV);
	p0.l = lo(PLL_DIV);
	w[p0] = r0.l;
	ssync;

	p0.l = lo(EBIU_SDRRC);
	p0.h = hi(EBIU_SDRRC);
	r0 = mem_SDRRC;
	w[p0] = r0.l;
	ssync;

	p0.l = LO(EBIU_SDBCTL);
	p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */
	r0 = mem_SDBCTL;
	w[p0] = r0.l;
	ssync;

	P2.H = hi(EBIU_SDGCTL);
	P2.L = lo(EBIU_SDGCTL);
	R0 = [P2];
	BITCLR (R0, 24);
	p0.h = hi(EBIU_SDSTAT);
	p0.l = lo(EBIU_SDSTAT);
	r2.l = w[p0];
	cc = bittst(r2,3);
	if !cc jump .Lskip;
	NOP;
	BITSET (R0, 23);
.Lskip:
	[P2] = R0;
	SSYNC;

	R0.L = lo(mem_SDGCTL);
	R0.H = hi(mem_SDGCTL);
	R1 = [p2];
	R1 = R1 | R0;
	[P2] = R1;
	SSYNC;

	p0.h = hi(SIC_IWR);
	p0.l = lo(SIC_IWR);
	r0.l = lo(IWR_ENABLE_ALL);
	r0.h = hi(IWR_ENABLE_ALL);
	[p0] = r0;
	SSYNC;

	RTS;
ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */

.data

/*
 * Set up the usable of RAM stuff. Size of RAM is determined then
 * an initial stack set up at the end.
 */

.align 4
__rambase:
.long   0
__ramstart:
.long   0
__ramend:
.long   0
Commit	Line	Data
1394f032 BW	1	/*
	2	* File: arch/blackfin/mach-bf533/head.S
	3	* Based on:
	4	* Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
	5	*
	6	* Created: 1998
	7	* Description: bf533 startup file
	8	*
	9	* Modified:
	10	* Copyright 2004-2006 Analog Devices Inc.
	11	*
	12	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, see the file COPYING, or write
	26	* to the Free Software Foundation, Inc.,
	27	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	28	*/
	29
	30	#include <linux/linkage.h>
52a07812	31	#include <linux/init.h>
1394f032	32	#include <asm/blackfin.h>
669b792c	33	#include <asm/trace.h>
1394f032	34	#if CONFIG_BFIN_KERNEL_CLOCK
f16295e7	35	#include <asm/mach-common/clocks.h>
1394f032 BW	36	#include <asm/mach/mem_init.h>
1394f032 BW	37	#endif
1394f032 BW	38
	39	.global __rambase
	40	.global __ramstart
	41	.global __ramend
	42	.extern ___bss_stop
	43	.extern ___bss_start
	44	.extern _bf53x_relocate_l1_mem
	45
	46	#define INITIAL_STACK 0xFFB01000
	47
52a07812	48	__INIT
1394f032 BW	49
1394f032 BW	50	ENTRY(__start)
1394f032 BW	51	/* R0: argument of command line string, passed from uboot, save it */
1394f032 BW	52	R7 = R0;
f0b5d12f MF	53	/* Enable Cycle Counter and Nesting Of Interrupts */
	54	#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
	55	R0 = SYSCFG_SNEN;
	56	#else
	57	R0 = SYSCFG_SNEN \| SYSCFG_CCEN;
	58	#endif
1394f032 BW	59	SYSCFG = R0;
	60	R0 = 0;
	61
83a5c3e3	62	/* Clear Out All the data and pointer Registers */
1394f032 BW	63	R1 = R0;
	64	R2 = R0;
	65	R3 = R0;
	66	R4 = R0;
	67	R5 = R0;
	68	R6 = R0;
	69
	70	P0 = R0;
	71	P1 = R0;
	72	P2 = R0;
	73	P3 = R0;
	74	P4 = R0;
	75	P5 = R0;
	76
	77	LC0 = r0;
	78	LC1 = r0;
	79	L0 = r0;
	80	L1 = r0;
	81	L2 = r0;
	82	L3 = r0;
	83
83a5c3e3	84	/* Clear Out All the DAG Registers */
1394f032 BW	85	B0 = r0;
	86	B1 = r0;
	87	B2 = r0;
	88	B3 = r0;
	89
	90	I0 = r0;
	91	I1 = r0;
	92	I2 = r0;
	93	I3 = r0;
	94
	95	M0 = r0;
	96	M1 = r0;
	97	M2 = r0;
	98	M3 = r0;
	99
518039bc	100	trace_buffer_init(p0,r0);
669b792c RG	101	P0 = R1;
	102	R0 = R1;
	103
1394f032 BW	104	p0.h = hi(FIO_MASKA_C);
	105	p0.l = lo(FIO_MASKA_C);
	106	r0 = 0xFFFF(Z);
	107	w[p0] = r0.L; /* Disable all interrupts */
	108	ssync;
	109
	110	p0.h = hi(FIO_MASKB_C);
	111	p0.l = lo(FIO_MASKB_C);
	112	r0 = 0xFFFF(Z);
	113	w[p0] = r0.L; /* Disable all interrupts */
	114	ssync;
	115
	116	/* Turn off the icache */
e208f83a MF	117	p0.l = LO(IMEM_CONTROL);
e208f83a MF	118	p0.h = HI(IMEM_CONTROL);
1394f032 BW	119	R1 = [p0];
	120	R0 = ~ENICPLB;
	121	R0 = R0 & R1;
	122
	123	/* Anomaly 05000125 */
1aafd909	124	#if ANOMALY_05000125
1394f032 BW	125	CLI R2;
	126	SSYNC;
	127	#endif
	128	[p0] = R0;
	129	SSYNC;
1aafd909	130	#if ANOMALY_05000125
1394f032 BW	131	STI R2;
	132	#endif
	133
	134	/* Turn off the dcache */
e208f83a MF	135	p0.l = LO(DMEM_CONTROL);
e208f83a MF	136	p0.h = HI(DMEM_CONTROL);
1394f032 BW	137	R1 = [p0];
	138	R0 = ~ENDCPLB;
	139	R0 = R0 & R1;
	140
	141	/* Anomaly 05000125 */
1aafd909	142	#if ANOMALY_05000125
1394f032 BW	143	CLI R2;
	144	SSYNC;
	145	#endif
	146	[p0] = R0;
	147	SSYNC;
1aafd909	148	#if ANOMALY_05000125
1394f032 BW	149	STI R2;
	150	#endif
	151
5079df99 MF	152	/* Initialise UART - when booting from u-boot, the UART is not disabled
5079df99 MF	153	* so if we dont initalize here, our serial console gets hosed */
1394f032 BW	154	p0.h = hi(UART_LCR);
	155	p0.l = lo(UART_LCR);
	156	r0 = 0x0(Z);
	157	w[p0] = r0.L; /* To enable DLL writes */
	158	ssync;
	159
	160	p0.h = hi(UART_DLL);
	161	p0.l = lo(UART_DLL);
	162	r0 = 0x0(Z);
	163	w[p0] = r0.L;
	164	ssync;
	165
	166	p0.h = hi(UART_DLH);
	167	p0.l = lo(UART_DLH);
	168	r0 = 0x00(Z);
	169	w[p0] = r0.L;
	170	ssync;
	171
	172	p0.h = hi(UART_GCTL);
	173	p0.l = lo(UART_GCTL);
	174	r0 = 0x0(Z);
	175	w[p0] = r0.L; /* To enable UART clock */
	176	ssync;
	177
	178	/* Initialize stack pointer */
	179	sp.l = lo(INITIAL_STACK);
	180	sp.h = hi(INITIAL_STACK);
	181	fp = sp;
	182	usp = sp;
	183
	184	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
	185	call _bf53x_relocate_l1_mem;
	186	#if CONFIG_BFIN_KERNEL_CLOCK
	187	call _start_dma_code;
	188	#endif
	189
	190	/* Code for initializing Async memory banks */
	191
	192	p2.h = hi(EBIU_AMBCTL1);
	193	p2.l = lo(EBIU_AMBCTL1);
	194	r0.h = hi(AMBCTL1VAL);
	195	r0.l = lo(AMBCTL1VAL);
	196	[p2] = r0;
	197	ssync;
	198
	199	p2.h = hi(EBIU_AMBCTL0);
	200	p2.l = lo(EBIU_AMBCTL0);
	201	r0.h = hi(AMBCTL0VAL);
	202	r0.l = lo(AMBCTL0VAL);
	203	[p2] = r0;
	204	ssync;
	205
	206	p2.h = hi(EBIU_AMGCTL);
	207	p2.l = lo(EBIU_AMGCTL);
	208	r0 = AMGCTLVAL;
	209	w[p2] = r0;
	210	ssync;
	211
	212	/* This section keeps the processor in supervisor mode
	213	* during kernel boot. Switches to user mode at end of boot.
	214	* See page 3-9 of Hardware Reference manual for documentation.
	215	*/
	216
	217	/* EVT15 = _real_start */
218
219	p0.l = lo(EVT15);
220	p0.h = hi(EVT15);
221	p1.l = _real_start;
222	p1.h = _real_start;
223	[p0] = p1;
224	csync;
225
226	p0.l = lo(IMASK);
227	p0.h = hi(IMASK);
228	p1.l = IMASK_IVG15;
229	p1.h = 0x0;
230	[p0] = p1;
231	csync;
232
233	raise 15;
234	p0.l = .LWAIT_HERE;
235	p0.h = .LWAIT_HERE;
236	reti = p0;
1aafd909	237	#if ANOMALY_05000281
1394f032 BW	238	nop; nop; nop;
	239	#endif
	240	rti;
	241
	242	.LWAIT_HERE:
	243	jump .LWAIT_HERE;
52a07812	244	ENDPROC(__start)
1394f032 BW	245
	246	ENTRY(_real_start)
	247	[ -- sp ] = reti;
	248	p0.l = lo(WDOG_CTL);
	249	p0.h = hi(WDOG_CTL);
	250	r0 = 0xAD6(z);
	251	w[p0] = r0; /* watchdog off for now */
	252	ssync;
	253
	254	/* Code update for BSS size == 0
	255	* Zero out the bss region.
	256	*/
	257
	258	p1.l = ___bss_start;
	259	p1.h = ___bss_start;
	260	p2.l = ___bss_stop;
	261	p2.h = ___bss_stop;
	262	r0 = 0;
	263	p2 -= p1;
	264	lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
	265	.L_clear_bss:
	266	B[p1++] = r0;
	267
	268	/* In case there is a NULL pointer reference
	269	* Zero out region before stext
	270	*/
	271
	272	p1.l = 0x0;
	273	p1.h = 0x0;
	274	r0.l = __stext;
	275	r0.h = __stext;
	276	r0 = r0 >> 1;
	277	p2 = r0;
	278	r0 = 0;
	279	lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
	280	.L_clear_zero:
	281	W[p1++] = r0;
	282
83a5c3e3	283	/* pass the uboot arguments to the global value command line */
1394f032 BW	284	R0 = R7;
	285	call _cmdline_init;
	286
	287	p1.l = __rambase;
	288	p1.h = __rambase;
	289	r0.l = __sdata;
	290	r0.h = __sdata;
	291	[p1] = r0;
	292
	293	p1.l = __ramstart;
	294	p1.h = __ramstart;
	295	p3.l = ___bss_stop;
	296	p3.h = ___bss_stop;
	297
	298	r1 = p3;
	299	[p1] = r1;
	300
	301	/*
83a5c3e3	302	* load the current thread pointer and stack
1394f032 BW	303	*/
	304	r1.l = _init_thread_union;
	305	r1.h = _init_thread_union;
	306
	307	r2.l = 0x2000;
	308	r2.h = 0x0000;
	309	r1 = r1 + r2;
	310	sp = r1;
	311	usp = sp;
	312	fp = sp;
52a07812 MF	313	jump.l _start_kernel;
	314	ENDPROC(_real_start)
	315
	316	__FINIT
1394f032 BW	317
	318	.section .l1.text
	319	#if CONFIG_BFIN_KERNEL_CLOCK
	320	ENTRY(_start_dma_code)
	321	p0.h = hi(SIC_IWR);
	322	p0.l = lo(SIC_IWR);
	323	r0.l = 0x1;
	324	r0.h = 0x0;
	325	[p0] = r0;
	326	SSYNC;
	327
	328	/*
	329	* Set PLL_CTL
	330	* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
	331	* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
	332	* - [7] = output delay (add 200ps of delay to mem signals)
	333	* - [6] = input delay (add 200ps of input delay to mem signals)
	334	* - [5] = PDWN : 1=All Clocks off
	335	* - [3] = STOPCK : 1=Core Clock off
	336	* - [1] = PLL_OFF : 1=Disable Power to PLL
	337	* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
	338	* all other bits set to zero
	339	*/
	340
	341	p0.h = hi(PLL_LOCKCNT);
	342	p0.l = lo(PLL_LOCKCNT);
	343	r0 = 0x300(Z);
	344	w[p0] = r0.l;
	345	ssync;
	346
	347	P2.H = hi(EBIU_SDGCTL);
	348	P2.L = lo(EBIU_SDGCTL);
	349	R0 = [P2];
	350	BITSET (R0, 24);
	351	[P2] = R0;
	352	SSYNC;
	353
	354	r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
	355	r0 = r0 << 9; /* Shift it over, */
	356	r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
	357	r0 = r1 \| r0;
	358	r1 = PLL_BYPASS; /* Bypass the PLL? */
	359	r1 = r1 << 8; /* Shift it over */
	360	r0 = r1 \| r0; /* add them all together */
	361
	362	p0.h = hi(PLL_CTL);
	363	p0.l = lo(PLL_CTL); /* Load the address */
	364	cli r2; /* Disable interrupts */
	365	ssync;
	366	w[p0] = r0.l; /* Set the value */
	367	idle; /* Wait for the PLL to stablize */
	368	sti r2; /* Enable interrupts */
	369
	370	.Lcheck_again:
	371	p0.h = hi(PLL_STAT);
	372	p0.l = lo(PLL_STAT);
	373	R0 = W[P0](Z);
	374	CC = BITTST(R0,5);
	375	if ! CC jump .Lcheck_again;
	376
	377	/* Configure SCLK & CCLK Dividers */
	378	r0 = (CONFIG_CCLK_ACT_DIV \| CONFIG_SCLK_DIV);
	379	p0.h = hi(PLL_DIV);
	380	p0.l = lo(PLL_DIV);
381	w[p0] = r0.l;
382	ssync;
383
384	p0.l = lo(EBIU_SDRRC);
385	p0.h = hi(EBIU_SDRRC);
386	r0 = mem_SDRRC;
387	w[p0] = r0.l;
388	ssync;
389
e208f83a MF	390	p0.l = LO(EBIU_SDBCTL);
e208f83a MF	391	p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
1394f032 BW	392	r0 = mem_SDBCTL;
	393	w[p0] = r0.l;
	394	ssync;
	395
	396	P2.H = hi(EBIU_SDGCTL);
	397	P2.L = lo(EBIU_SDGCTL);
	398	R0 = [P2];
	399	BITCLR (R0, 24);
	400	p0.h = hi(EBIU_SDSTAT);
	401	p0.l = lo(EBIU_SDSTAT);
	402	r2.l = w[p0];
	403	cc = bittst(r2,3);
	404	if !cc jump .Lskip;
	405	NOP;
	406	BITSET (R0, 23);
	407	.Lskip:
	408	[P2] = R0;
	409	SSYNC;
	410
	411	R0.L = lo(mem_SDGCTL);
	412	R0.H = hi(mem_SDGCTL);
	413	R1 = [p2];
	414	R1 = R1 \| R0;
	415	[P2] = R1;
	416	SSYNC;
	417
	418	p0.h = hi(SIC_IWR);
	419	p0.l = lo(SIC_IWR);
83a5c3e3 MF	420	r0.l = lo(IWR_ENABLE_ALL);
83a5c3e3 MF	421	r0.h = hi(IWR_ENABLE_ALL);
1394f032 BW	422	[p0] = r0;
	423	SSYNC;
	424
	425	RTS;
52a07812	426	ENDPROC(_start_dma_code)
1394f032 BW	427	#endif /* CONFIG_BFIN_KERNEL_CLOCK */
1394f032 BW	428
1394f032 BW	429	.data
	430
	431	/*
	432	* Set up the usable of RAM stuff. Size of RAM is determined then
	433	* an initial stack set up at the end.
	434	*/
	435
	436	.align 4
	437	__rambase:
	438	.long 0
	439	__ramstart:
	440	.long 0
	441	__ramend:
	442	.long 0